Amplifier circuit

Abstract

The embodiment of the invention relates to the technical field of electronic circuits, in particular to an amplifier circuit, and the amplifier circuit comprises a first amplifier circuit which comprises a first transconductance amplifier circuit and a current limiting circuit which are electrically connected with each other, and the current limiting circuit is used for adjusting the output current of the first transconductance amplifier circuit based on a preset current limiting value; the second amplifier circuit comprises a second transconductance amplifier circuit and a pressure swing regulation and control circuit which are electrically connected with each other, and the input end of the second transconductance amplifier circuit and the input end of the first transconductance amplifier circuit are both used for being connected with a signal source to be amplified and conducting signal amplification on the signal source to be amplified; the output end of the pressure swing regulation and control circuit is electrically connected with the current control end of the current limiting circuit, and the pressure swing regulation and control circuit is used for regulating the preset current limiting value. A transconductance amplifier that can provide a small slew rate in a small signal stage is provided.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and more particularly, to an amplifier circuit. Background Art

[0002] The current mirror transconductance amplifier is one of the commonly used amplifier types in the industry. It has only a single pole, can be stable without frequency compensation, has a wide output swing, and is simple to design. The settling time of an amplifier is one of the important parameters for evaluating its performance. This settling time mainly includes two stages: The first stage (large signal stage, also known as the Slew rate stage): The output voltage of the operational amplifier reaches near the target value from the starting value. The main influencing factor is the slew rate of the operational amplifier; The second stage (small signal stage), the main influencing factor is the amplifier bandwidth (such as the transconductance (gm) of the increasing signal and small signal). Therefore, in order to accelerate the settling time of the amplifier, the amplifier is usually designed with a larger gm to obtain a larger bandwidth.

[0003] However, a large bandwidth design usually requires a large operating current, along with a large slew rate. However, for traditional transconductance amplifiers with slew rate enhancement, the tail current source / output stage current is increased in a large transient to increase the slew rate; it is easy to obtain a small transconductance - large slew rate or a large transconductance, large slew rate, but it is difficult to obtain the combined effect of a large transconductance - small slew rate in the small signal state and a large slew rate in the large signal state.

[0004] That is, the traditional transconductance amplifier design:

[0005] Small signal stage: small gm / small SR --- easy to obtain; large gm / large SR ----- easy to obtain;

[0006] Large signal stage: large SR ----- easy to obtain;

[0007] However, in the small signal stage: large gm / small SR and in the large signal stage: large SR ---- difficult to obtain.

[0008] Therefore, there is an urgent need for a transconductance amplifier that can provide a small slew rate in the small signal stage. Summary of the Invention

[0009] To solve the above technical problems, an amplifier circuit is provided in an embodiment of this application.

[0010] In a first aspect of the embodiments of this application, an amplifier circuit is provided, including:

[0011] A first amplifier circuit, including a first transconductance amplifier circuit and a current limiting circuit that are electrically connected to each other, where the current limiting circuit is configured to adjust the output current of the first transconductance amplifier circuit based on a preset current limiting value;

[0012] A second amplifier circuit, comprising a second transconductance amplifier circuit and a slew rate control circuit that are electrically connected to each other. The input terminals of the second transconductance amplifier circuit and the first transconductance amplifier circuit are both used to connect to a signal source to be amplified and amplify the signal source to be amplified. The output terminal of the slew rate control circuit is electrically connected to the current control terminal of the current limiting circuit, and the slew rate control circuit is used to adjust the magnitude of the preset current limiting value.

[0013] In an optional embodiment of the present application, the current limiting circuit includes:

[0014] A first sampling circuit, connected in parallel with the first transconductance amplifier circuit, for performing current sampling on both ends of the first transconductance amplifier circuit based on a preset first current limiting value;

[0015] A first current regulation circuit, the input terminal of the first current regulation circuit is electrically connected to the output terminal of the first sampling circuit, the output terminal of the first current regulation circuit is electrically connected to the first DC bias voltage terminal of the first transconductance amplifier circuit, and the current control terminal of the first current regulation circuit is electrically connected to the first output terminal of the slew rate control circuit. The first current regulation circuit is used to, when the sampled current of the first sampling circuit is less than a preset first threshold, lower the current of the DC bias voltage terminal of the first transconductance amplifier circuit based on the preset first current limiting value, thereby reducing the output current of the first transconductance amplifier circuit.

[0016] In an optional embodiment of the present application, the first current regulation circuit includes: a plurality of transistors; among them, the transistor electrically connected to the output terminal of the first sampling circuit and the first output terminal of the slew rate control circuit is a P-type transistor; the transistor electrically connected to the first DC bias voltage terminal of the first transconductance amplifier circuit is an N-type transistor.

[0017] In an optional embodiment of the present application, the current limiting circuit further includes:

[0018] A second sampling circuit, connected in parallel with the first transconductance amplifier circuit, for performing current sampling on both ends of the first transconductance amplifier circuit based on a preset second current limiting value;

[0019] A second current regulation circuit, the input end of the second current regulation circuit is electrically connected to the output end of the second sampling circuit, the output end of the second current regulation circuit is electrically connected to the second DC bias voltage terminal of the first transconductance amplifier circuit, the current control end of the second current regulation circuit is electrically connected to the second output end of the slew rate regulation circuit, and the second current regulation circuit is configured to, when the sampling current of the second sampling circuit is greater than a preset second threshold, reduce the output current of the first transconductance amplifier circuit by pulling down the current of the second DC bias voltage terminal of the first transconductance amplifier circuit based on a preset second current limiting value.

[0020] In an optional embodiment of the present application, the second current regulation circuit includes: at least one N-type transistor.

[0021] In an optional embodiment of the present application, both the first sampling circuit and the second sampling circuit each include at least one set of N-type transistors and P-type transistors that are electrically connected to each other.

[0022] In an optional embodiment of the present application, the slew rate regulation circuit includes:

[0023] A third sampling circuit, connected in parallel with the second transconductance amplifier circuit, for sampling the current at both ends of the second transconductance amplifier circuit;

[0024] A third current regulation circuit, the control end of the third current regulation circuit is electrically connected to the output end of the third sampling circuit, and the output end of the third current regulation circuit is respectively electrically connected to the second output end of the second transconductance amplifier circuit and the second current control end of the current limiting circuit.

[0025] In an optional embodiment of the present application, the third current regulation circuit includes at least two N-type transistors that are electrically connected to each other.

[0026] In an optional embodiment of the present application, the slew rate regulation circuit further includes:

[0027] A fourth sampling circuit, connected in parallel with the second transconductance amplifier circuit, for sampling the current at both ends of the second transconductance amplifier circuit;

[0028] A fourth current regulation circuit, the control end of the fourth current regulation circuit is electrically connected to the output end of the fourth sampling circuit, and the output end of the fourth current regulation circuit is respectively electrically connected to the first output end of the second transconductance amplifier circuit and the first current control end of the current limiting circuit.

[0029] In an optional embodiment of the present application, the fourth current regulation circuit includes at least two P-type transistors that are electrically connected to each other.

[0030] In an optional embodiment of the present application, the power inputs of the first transconductance amplifier circuit and the second transconductance amplifier circuit are the same.

[0031] The amplifier circuit provided in the embodiment of the present application includes a first amplifier circuit and a second amplifier circuit. Among them, the first amplifier circuit includes a first transconductance amplifier circuit and a current limiting circuit that are electrically connected to each other. The second amplifier circuit includes a second transconductance amplifier circuit and a slew rate regulation circuit that are electrically connected to each other. The output end of the slew rate regulation circuit is electrically connected to the current control end of the current limiting circuit and is used to adjust the magnitude of a preset current limit value. The current limiting circuit adjusts the output current of the first transconductance amplifier circuit based on the preset current limit value, thereby realizing the control of the slew rate of the output current of the first transconductance amplifier circuit. For example, the slew rate regulation circuit 122 dynamically adjusts the magnitude of the input / output current of the first transconductance amplifier circuit 111 according to the value of the output current change amount (VINP - VINN). If VINP - VINN is small, the current limit value of the first transconductance amplifier circuit 111 is also small; if the value of VINP - VINN is large, the output current limit value of the first transconductance amplifier circuit 111 will be dynamically increased.

[0032] In the first aspect, in this way, the output current of the first transconductance amplifier circuit is stabilized within a small range, and the output current change amount is small, thereby achieving the purpose that the first transconductance amplifier circuit has a small slew rate, that is, a transconductance amplifier that can provide a small slew rate in the small signal stage is provided.

[0033] In the second aspect, as Figure 4 shown, in the traditional scheme, due to the large output current change amount (VINP - VINN), it is very easy to cause a large slew rate. The amplifier circuit provided in the embodiment of the present application can stabilize the output current of the first transconductance amplifier circuit within a small range regardless of the magnitude of the current input of the first transconductance amplifier circuit and the magnitude of the change amount. The preset current limit value can be flexibly adjusted by the slew rate regulation circuit. Correspondingly, the slew rate of the first transconductance amplifier can also be flexibly adjusted, with higher applicability and a wider application range.

[0034] In the third aspect, the amplifier circuit provided in the embodiment of the present application has a large transconductance (gm). The preset current limit value can be flexibly adjusted, and the corresponding slew rate can also be flexibly adjusted. It can obtain a large transconductance in the small signal stage while maintaining a small slew rate, and at the same time provide the adjustment ability of dynamic slew rate limitation in the transient state, enhancing the transient response of the amplifier under large signals. At the same time, please refer to Figure 5 and Figure 6 , the dynamic slew rate limitation will reduce the overshoot and undershoot caused by large output current changes, and can shorten the settling time of the amplifier compared with the traditional method. Description of the Drawings

[0035] The drawings described herein are provided to further understand the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0036] Figure 1 is a schematic structural diagram of an amplifier circuit provided by an embodiment of the present application;

[0037] Figure 2 is a schematic structural diagram of a first amplifier circuit provided by an embodiment of the present application;

[0038] Figure 3 is a schematic structural diagram of a second amplifier circuit provided by an embodiment of the present application;

[0039] Figure 4 is a graph showing the variation relationship between the input voltage and the slew rate in the amplifier circuit provided by an embodiment of the present application;

[0040] Figure 5 is a schematic diagram showing the corresponding relationship between the amplifier settling time and the overshoot voltage in the amplifier circuit provided by an embodiment of the present application;

[0041] Figure 6 is a waveform comparison diagram between the amplifier circuit provided by an embodiment of the present application and a traditional amplifier circuit.

[0042] Wherein: 10, amplifier circuit; 110, first amplifier circuit; 111, first transconductance amplifier circuit; 112, current limiting circuit; 120, second amplifier circuit; 121, second transconductance amplifier circuit; 122, slew rate control circuit. Detailed Embodiments

[0043] In the process of implementing the present application, the inventors found that there is an urgent need for a transconductance amplifier that can provide a small slew rate in the small signal stage.

[0044] In view of the above problems, the embodiments of the present application provide an amplifier circuit. In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further details the exemplary embodiments of the present application with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0045] The serial numbers assigned to components in this text itself, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. And the "connection" and "coupling" mentioned in this application, unless otherwise specifically stated, both include direct and indirect connection (coupling). In the description of this application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application.

[0046] In this application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0047] The current mirror transconductance amplifier is one of the commonly used amplifier types in the industry. It has only a single pole, can be stabilized without frequency compensation, and has a wide output swing and a simple design. The settling time of the amplifier is one of the important parameters for evaluating its performance. This settling time mainly includes two stages: The first stage (large signal stage): The process in which the output voltage of the operational amplifier reaches near the target value from the starting value, and the main influencing factor is the slew rate of the operational amplifier; The second stage (small signal stage), and the main influencing factor is the amplifier bandwidth (such as the transconductance (gm) of the increasing signal and small signal). Therefore, in order to accelerate the settling time of the amplifier, the amplifier is usually designed with a larger gm to obtain a larger bandwidth.

[0048] However, a large bandwidth design usually requires a large operating current, along with a large slew rate. However, for traditional transconductance amplifiers with slew rate enhancement, the current of the tail current source / output stage is increased in a large transient to improve the slew rate; it is easy to obtain a small transconductance - large slew rate or a large transconductance, large slew rate, but it is difficult to obtain the combined effect of a large transconductance - small slew rate under small signals and a large slew rate under large signals.

[0049] That is, the traditional transconductance amplifier design:

[0050] Small signal stage: small gm / small SR --- easy to obtain; large gm / large SR ----- easy to obtain;

[0051] Large-signal stage: large SR ----- easily obtained;

[0052] However, in the small-signal stage: large gm / small SR and in the large-signal stage: large SR ---- difficult to obtain.

[0053] Therefore, there is an urgent need for a transconductance amplifier that can provide a small slew rate in the small-signal stage.

[0054] Please also refer to Figure 1 、 Figure 2 and Figure 3 In this embodiment of the application, an amplifier circuit 10 is provided, including: a first amplifier circuit 110 and a second amplifier circuit 120, where:

[0055] As Figure 2 shown, the first amplifier circuit 110 includes a first transconductance amplifier circuit 111 and a current limiting circuit 112 that are electrically connected to each other. The first transconductance amplifier circuit 111 includes at least one transconductance amplifier for implementing signal amplification processing. The first transconductance amplifier includes a power input terminal VINP (positive electrode) and VINN (negative electrode). Other ports or memory devices of the first transconductance amplifier are not enumerated here and can be flexibly adjusted according to actual situations, as long as the amplification function can be achieved.

[0056] The current limiting circuit 112 is used to adjust the output current of the first transconductance amplifier circuit 111 based on a preset current limiting value, that is, regardless of the change in the input current of the first transconductance amplifier circuit 111, its output current remains within a set fixed current range, so that the first amplifier circuit 110 operates in a current limiting mode. The current limiting range can be flexibly adjusted according to actual situations and is not specifically limited here. The slew rate refers to the change rate of the output current of the first transconductance amplifier circuit 111. The larger the change in the output current, the larger the slew rate. On the contrary, the smaller the change in the output current, the smaller the slew rate. In an actual circuit, the size of the output current can be adjusted through the preset current limiting value to control the change amount of the output current, so as to achieve the purpose of adjusting the slew rate of the amplifier circuit 10.

[0057] As Figure 3 shown, the second amplifier circuit 120 includes a second transconductance amplifier circuit 121 and a slew rate control circuit 122 that are electrically connected to each other. The second transconductance amplifier circuit 121 and the input terminal of the first transconductance amplifier circuit 111 are both used to connect to a signal source to be amplified and amplify the signal source to be amplified; the output terminal of the slew rate control circuit 122 is electrically connected to the current control terminal of the current limiting circuit 112, and the slew rate control circuit 122 is used to adjust the size of the preset current limiting value.

[0058] That is, the input ends of the second amplifier circuit 120 and the first amplifier circuit 110 are both used to connect to the signal source to be amplified, and amplify the signal source to be amplified. Moreover, the second amplifier circuit 120 acts on the first amplifier circuit 110 to adjust the magnitude of the output current of the first amplifier circuit 110 by adjusting the preset current limit value.

[0059] The circuit structure of the second transconductance amplifier circuit 121 and the above-mentioned first transconductance amplifier circuit 111 may be the same or different, and no specific limitation is made here. It only needs to be able to achieve the function of amplifying the signal. The output of the slew rate control circuit 122 is the control signal of the above-mentioned current limiting circuit 112. The output of the current limiting circuit 112 is adjusted through the output current of the slew rate control circuit 122, so as to achieve the function of slew rate. The specific circuit structure of the slew rate control circuit 122 is not limited here and can be flexibly set according to the actual situation. It only needs to be able to achieve the purpose of controlling the preset current value of the current limiting circuit 112.

[0060] The amplifier circuit 10 provided by the embodiment of the present application includes a first amplifier circuit 110 and a second amplifier circuit 120. Among them, the first amplifier circuit 110 includes a first transconductance amplifier circuit 111 and a current limiting circuit 112 that are electrically connected to each other. The second amplifier circuit 120 includes a second transconductance amplifier circuit 121 and a slew rate control circuit 122 that are electrically connected to each other. The output end of the slew rate control circuit 122 is electrically connected to the current control end of the current limiting circuit 112 to adjust the magnitude of the preset current limit value. The current limiting circuit 112 adjusts the output current of the first transconductance amplifier circuit 111 based on the preset current limit value, thereby realizing the slew rate of controlling the output current of the first transconductance amplifier circuit 111. For example, the slew rate control circuit 122 dynamically adjusts the magnitude of the input / output current of the first transconductance amplifier circuit 111 following the value of the output current change amount (VINP - VINN). If VINP - VINN is small, the current limit value of the first transconductance amplifier circuit 111 is also small; if the value of VINP - VINN is large, the output current limit value of the first transconductance amplifier circuit 111 will be dynamically increased.

[0061] In the first aspect, in this way, the output current of the first transconductance amplifier circuit 111 is stabilized within a small range, and the output current change amount is small, thereby achieving the purpose that the first transconductance amplifier circuit 111 has a small slew rate, that is, a transconductance amplifier that can provide a small slew rate in the small signal stage is provided.

[0062] In the second aspect, as Figure 4As shown, in the traditional solution, since the change in the output current (VINP - VINN) is large, it is easy to cause a large slew rate. Regardless of the magnitude of the current input to the first transconductance amplifier circuit 111 and the magnitude of the change in the amplifier circuit 10 provided in the embodiment of the present application, the output current of the first transconductance amplifier circuit 111 can be stabilized within a small range through the current limiting circuit 112 with an adjustable preset current limiting value. The preset current limiting value can be flexibly adjusted by the slew rate control circuit 122. Correspondingly, the slew rate of the first transconductance amplifier can also be flexibly adjusted, with higher applicability and a wider application range.

[0063] In a third aspect, the transconductance set by the first amplifier circuit 110 in the amplifier circuit 10 provided in the embodiment of the present application is greater than a preset threshold (for example, 0.2 mS), that is, the first amplifier circuit 110 has a large transconductance (gm). With a large transconductance, a larger small-signal bandwidth can be obtained. The first amplifier circuit 110 can obtain a small-signal bandwidth based on the large transconductance. At the same time, the preset current limiting value in the first amplifier circuit 110 can be flexibly adjusted, and the corresponding slew rate can also be flexibly adjusted. It is possible to obtain a large transconductance while maintaining a small slew rate in the small-signal stage, and at the same time provide the ability to adjust the dynamic slew rate limit in the transient state. When a large output current capacity is required in the large-signal state, a large slew rate will provide a greater output current capacity, thereby enhancing the transient response of the amplifier in the large-signal state. At the same time, please refer to Figure 5 and Figure 6 , the dynamic slew rate limit will reduce the overshoot and undershoot caused by a large change in the output current, and can shorten the settling time of the amplifier compared to the traditional method.

[0064] In an optional embodiment of the present application, the current limiting circuit 112 includes: a first sampling circuit and a first current adjustment circuit, where:

[0065] The first sampling circuit is connected in parallel with the first transconductance amplifier circuit 111 and is used to sample the current at both ends of the first transconductance amplifier circuit 111 based on a preset first current limiting value.

[0066] The first sampling circuit includes at least one set of N-type transistors and P-type transistors that are electrically connected to each other, and the first sampling circuit is used to collect the current at both ends of the first transconductance amplifier. For example, please continue to refer to Figure 2:The first sampling circuit includes two transistors, PM3 and NM5. Among them, transistor PM3 is used to sample the current at the PM2 terminal of the first transconductance amplifier, and transistor NM5 is used to sample the current at the NM4 terminal of the first transconductance amplifier. The sampling ratio of the second sampling circuit is K2, that is, the sizes of transistor PM2 and transistor PM3 are (K2:1), the sizes of NM4 and NM5 are (K2:1), the current of PM3 transistor is 1 / K2 of the current of PM2, and the current of NM5 transistor is 1 / K2 of the current of NM4.

[0067] The input end of the first current regulation circuit is electrically connected to the output end of the first sampling circuit, the output end of the first current regulation circuit is electrically connected to the first DC bias voltage terminal VBN1 of the first transconductance amplifier circuit 111, and the current control end of the first current regulation circuit is electrically connected to the first output end Iin-limit of the slew rate regulation circuit 122. The first current regulation circuit is used to, when the sampled current of the first sampling circuit is less than a preset first threshold, based on a preset first current limit value, reduce the current at the DC bias voltage terminal of the first transconductance amplifier circuit 111 by pulling it down, thereby reducing the output current of the first transconductance amplifier circuit 111.

[0068] In an alternative embodiment of the present application, the first current regulation circuit includes: a plurality of transistors. Among them, the transistor electrically connected to the output end of the first sampling circuit and the first output end Iin-limit of the slew rate regulation circuit 122 is a P-type transistor; the transistor electrically connected to the first DC bias voltage terminal VBN1 of the first transconductance amplifier circuit 111 is an N-type transistor.

[0069] For example, please continue to refer to Figure 2 , the first DC bias voltage terminal is VBN1. The first current regulation circuit may include: a circuit formed by electrically connecting transistor PM7, transistor NM7, and transistor NM8. The drain of transistor NM7 is electrically connected to the first DC bias voltage terminal VBN1 of the first transconductance amplifier circuit 111. During operation, the current output by the first output end Iin-limit of the slew rate regulation circuit 122 controls the connection and disconnection of transistor PM7.

[0070] The current signal provided by the first output terminal of the voltage swing control circuit 122 in the second amplifier circuit 120 is multiplied as the current limiting point of the negative output current of VINN (negative terminal) of the first amplifier circuit 110. Specifically, when the output negative current of the first amplifier circuit 110 < Iin_limit * K2, at this time PM7 is turned off and does not affect normal operation. When the output negative current of the first amplifier circuit 110 > Iin_limit * K2, PM7 is turned on, and through NM7 and NM8, the voltage of VBN1 is pulled down to control the magnitude of the output negative current of the main OTA. That is to say, the output current of the first amplifier circuit 110 triggers the current limiting point of K2 * Iin_Ilimit, rather than the active change of Ilin_Ilimit triggering the current limiting action of the first amplifier.

[0071] In this way, the output negative current of the first transconductance amplifier circuit 111 can be current limited to Iin_limit * K2. This first current regulation circuit (i.e., transistor PM7, transistor NM7, transistor NM8) and PM3 and NM5 together constitute a current limiting circuit 112 for the output negative current (inflow), which is used to current limit the output negative current (inflow) of the first amplifier circuit 110 to Iin_limit * K2.

[0072] In an alternative embodiment of the present application, the current limiting circuit 112 further includes: a second sampling circuit, where:

[0073] This second sampling circuit is connected in parallel with the first transconductance amplifier circuit 111 and is used to perform current sampling on both ends of the first transconductance amplifier circuit 111 based on a preset second current limiting value;

[0074] This second sampling circuit at least includes a set of N-type transistors and P-type transistors that are electrically connected to each other, and this second sampling circuit is used to collect the current at both ends of the first transconductance amplifier. For example, please continue to refer to Figure 2 : This second sampling circuit includes a circuit formed by electrically connecting two transistors, PM4 and NM6. Among them, transistor PM4 is used to collect the current at the PM2 end of the first transconductance amplifier, and transistor NM6 is used to collect the current at the NM4 end of the first transconductance amplifier. The sampling ratio of the second sampling circuit is K1, that is, the sizes of transistor PM2 and transistor PM4 are (K1:1), the sizes of NM4 and NM6 are (K1:1), the current of PM4 tube is 1 / K1 of the current of PM2, and the current of NM6 tube is 1 / K1 of the current of NM4.

[0075] The input terminal of the second current regulation circuit is electrically connected to the output terminal of the second sampling circuit. The output terminal of the second current regulation circuit is electrically connected to the second DC bias voltage terminal VBN2 of the first transconductance amplifier circuit 111. The current control terminal of the second current regulation circuit is electrically connected to the second output terminal Iout-limit of the slew rate regulation circuit 122. The second current regulation circuit is configured to, when the sampled current of the second sampling circuit is greater than a preset second threshold, reduce the output current of the first transconductance amplifier circuit 111 by pulling down the current of the second DC bias voltage terminal of the first transconductance amplifier circuit 111 based on a preset second current limiting value.

[0076] In an alternative embodiment of the present application, the second current regulation circuit includes: at least one N-type transistor, such as Figure 2 transistor NM9 in. During operation, the current output from the second output terminal Iout-limit of the slew rate regulation circuit 122 controls the connection and disconnection of the transistor NM9. The second current regulation circuit (i.e., transistor NM9), together with PM4 and NM6, constitutes a current limiting circuit 112 for outputting positive current (flowing out), which is used to limit the output positive current (flowing out) of the first amplifier circuit 110 to Iin_limit*K1.

[0077] The Iout_limit multiplied by the second amplifier circuit 120 is used as the current limiting point of the positive output current of the first amplifier circuit 110. Specifically: when the output positive current of the first amplifier circuit 110 < Iout_limit*K1, at this time NM9 is turned off and does not affect the operation of the first amplifier circuit 110. When the output positive current of the first amplifier circuit 110 > Iout_limit*K1, NM9 is turned on, pulling down the voltage of VBN2, thereby controlling the magnitude of the output positive current of the first amplifier circuit 110. In this way, the output positive current of the first transconductance amplifier circuit 111 can be limited to Iout_limit*K1.

[0078] In an alternative embodiment of the present application, the above-mentioned slew rate regulation circuit 122 includes: a third sampling circuit, a third current regulation circuit, a fourth sampling circuit, and a third current regulation circuit, where:

[0079] The third sampling circuit is connected in parallel with the second transconductance amplifier circuit 121 and is configured to sample the current at both ends of the second transconductance amplifier circuit 121.

[0080] For example, please continue to refer to Figure 3 : The third sampling circuit includes two transistors, PM11 and NM13. Among them, the transistor PM11 is used to collect the current at the PM10 terminal of the second transconductance amplifier, and the transistor NM13 is used to collect the current at the NM10 terminal of the second transconductance amplifier.

[0081] The third current regulation circuit has its control end electrically connected to the output end of the third sampling circuit, and its output end is respectively electrically connected to the second output end of the second transconductance amplifier circuit 121 and the second current control end of the current limiting circuit 112.

[0082] In an optional embodiment of the present application, the third current regulation circuit includes at least two N-type transistors electrically connected to each other. For example Figure 3 NM15 and NM16 in, the drain of NM16 serves as the second output end Iout-limit of the slew rate control circuit 122 and is electrically connected to the control end of the second current regulation circuit (transistor NM9).

[0083] The embodiment of the present application realizes the regulation ability of the second current regulation circuit through the third sampling circuit and the third current regulation circuit, that is, realizes the flexible adjustment of the first preset current limiting value of the current limiting circuit 112, with a wider adaptation range and higher flexibility.

[0084] The fourth sampling circuit is connected in parallel with the second transconductance amplifier circuit 121 and is used to sample the current at both ends of the second transconductance amplifier circuit 121.

[0085] For example, please continue to refer to Figure 3 : The third sampling circuit includes two transistors PM12 and NM14 electrically connected to each other. Among them, transistor PM12 is used to collect the current at the PM10 end of the second transconductance amplifier, and transistor NM14 is used to collect the current at the NM10 end of the second transconductance amplifier.

[0086] The control end of the fourth current regulation circuit is electrically connected to the output end of the fourth sampling circuit, and its output end is respectively electrically connected to the first output end of the second transconductance amplifier circuit 121 and the first current control end of the current limiting circuit 112.

[0087] In an optional embodiment of the present application, the fourth current regulation circuit includes at least two P-type transistors electrically connected to each other. For example Figure 3 PM13 and PM14 in, the drain of PM14 serves as the first output end Iin-limit of the slew rate control circuit 122 and is electrically connected to the control end of the slew rate control circuit 122 (transistor PM7).

[0088] The embodiment of the present application realizes the regulation ability of the second current regulation circuit through the fourth sampling circuit and the fourth current regulation circuit, that is, realizes the flexible adjustment of the second preset current limiting value of the current limiting circuit 112, with a wider adaptation range and higher flexibility.

[0089] In an optional embodiment of the present application, the power inputs of the first transconductance amplifier circuit 111 and the second transconductance amplifier circuit 121 are the same.

[0090] That is, the input currents of the first transconductance amplifier circuit 111 and the second transconductance amplifier circuit 121 are the same. The slew rate control circuit 122 is used to control the operating mode and output of the second transconductance amplifier circuit 121, and the current limiting circuit 112 controls the output of the first transconductance amplifier circuit 111. The current limiting mode (i.e., the preset current limiting value) of the current limiting circuit 112 is controlled by the slew rate control circuit 122. Therefore, the same power supply input of the first transconductance amplifier circuit 111 and the second transconductance amplifier circuit 121 in the embodiments of the present application can improve the consistency of the control modes of the first transconductance amplifier circuit 111 and the second transconductance amplifier circuit 121, thereby improving the operating stability and reliability of the amplifier circuit 10 in the embodiments of the present application.

[0091] Such as Figure 6 FIG. is a comparison diagram of simulation waveform diagrams provided by embodiments of the present application. The top curve 1 is the waveform of a traditional large gm (transconductance) and large slew rate. An overshoot phenomenon occurs at 52.0 microseconds. The climb is fast in the initial stage but the overshoot is large, and finally the amplifier settling time is also large, requiring 54.0 microseconds.

[0092] The bottom curve 3 is the waveform of small gm and small slew rate. Although there is no overshoot phenomenon, the amplifier settling time is relatively long, requiring 56.5 microseconds.

[0093] The middle curve 2 is the waveform of the amplifier circuit 10 provided by the embodiments of the present application, which is the simulation waveform of the settling time of an OTA with large gm and dynamically adjustable slew rate. The overshoot is significantly reduced, and the amplifier settling time is also relatively short, only requiring 52.5 microseconds, and the settling duration converges to within 3%.

[0094] From Figure 6 it can be clearly seen that the waveform is smooth. The overshoot of the amplifier circuit 10 provided by the embodiments of the present application drops ideally, and at the same time, the slew rate is small, and it has a fast settling time. While ordinary designs are prone to overshoot / undershoot, resulting in a longer settling time.

[0095] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims. Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0096] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to cover these changes and modifications.

Claims

1. An amplifier circuit, characterized in that, Including: A first amplifier circuit, comprising a first transconductance amplifier circuit and a current limiting circuit electrically connected to each other, where the current limiting circuit is used to adjust the output current of the first transconductance amplifier circuit based on a preset current limiting value; A second amplifier circuit, comprising a second transconductance amplifier circuit and a slew rate control circuit electrically connected to each other. The input terminals of the second transconductance amplifier circuit and the first transconductance amplifier circuit are both used to connect to a signal source to be amplified and amplify the signal source to be amplified. The output terminal of the slew rate control circuit is electrically connected to the current control terminal of the current limiting circuit, and the slew rate control circuit is used to adjust the magnitude of the preset current limiting value.

2. The amplifier circuit according to claim 1, wherein The current limiting circuit includes: A first sampling circuit, connected in parallel with the first transconductance amplifier circuit, for sampling the current at both ends of the first transconductance amplifier circuit based on a preset first current limiting value; A first current adjustment circuit, where the input terminal of the first current adjustment circuit is electrically connected to the output terminal of the first sampling circuit, the output terminal of the first current adjustment circuit is electrically connected to the first DC bias voltage terminal of the first transconductance amplifier circuit, and the current control terminal of the first current adjustment circuit is electrically connected to the first output terminal of the slew rate control circuit. The first current adjustment circuit is used to, when the sampled current of the first sampling circuit is less than a preset first threshold, lower the output current of the first transconductance amplifier circuit by pulling down the current of the DC bias voltage terminal of the first transconductance amplifier circuit based on the preset first current limiting value.

3. The amplifier circuit according to claim 2, characterized in that, The first current adjustment circuit includes: a plurality of transistors; among them, the transistor electrically connected to the output terminal of the first sampling circuit and the first output terminal of the slew rate control circuit is a P-type transistor; the transistor electrically connected to the first DC bias voltage terminal of the first transconductance amplifier circuit is an N-type transistor.

4. The amplifier circuit according to claim 2, characterized in that, The current limiting circuit further includes: A second sampling circuit, connected in parallel with the first transconductance amplifier circuit, for sampling the current at both ends of the first transconductance amplifier circuit based on a preset second current limiting value; A second current adjustment circuit, where the input terminal of the second current adjustment circuit is electrically connected to the output terminal of the second sampling circuit, the output terminal of the second current adjustment circuit is electrically connected to the second DC bias voltage terminal of the first transconductance amplifier circuit, and the current control terminal of the second current adjustment circuit is electrically connected to the second output terminal of the slew rate control circuit. The second current adjustment circuit is used to, when the sampled current of the second sampling circuit is greater than a preset second threshold, lower the output current of the first transconductance amplifier circuit by pulling down the current of the second DC bias voltage terminal of the first transconductance amplifier circuit based on the preset second current limiting value.

5. The amplifier circuit according to claim 4, wherein The second current adjustment circuit includes: at least one N-type transistor.

6. The amplifier circuit according to claim 4, wherein, Both the first sampling circuit and the second sampling circuit each include at least one group of N-type transistors and P-type transistors electrically connected to each other.

7. The amplifier circuit according to claim 1, wherein The slew rate control circuit includes: A third sampling circuit, connected in parallel with the second transconductance amplifier circuit, for sampling the current at both ends of the second transconductance amplifier circuit; The third current regulation circuit, the control end of the third current regulation circuit is electrically connected to the output end of the third sampling circuit, and the output end of the third current regulation circuit is respectively electrically connected to the second output end of the second transconductance amplifier circuit and the second current control end of the current limiting circuit.

8. The amplifier circuit according to claim 7, wherein The third current regulation circuit includes at least two N-type transistors electrically connected to each other.

9. The amplifier circuit according to claim 7, wherein The slew rate regulation circuit further includes: The fourth sampling circuit, which is connected in parallel with the second transconductance amplifier circuit, is used for current sampling at both ends of the second transconductance amplifier circuit; The fourth current regulation circuit, the control end of the fourth current regulation circuit is electrically connected to the output end of the fourth sampling circuit, and the output end of the fourth current regulation circuit is respectively electrically connected to the first output end of the second transconductance amplifier circuit and the first current control end of the current limiting circuit.

10. The amplifier circuit according to claim 9, wherein, The fourth current regulation circuit includes at least two P-type crystals electrically connected to each other.

11. The amplifier circuit according to any one of claims 1-10, characterized in that, The power supplies of the first transconductance amplifier circuit and the second transconductance amplifier circuit are input in the same way.

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