Multi-voltage-domain circuit considering failure safety and high voltage resistance

Abstract

The invention discloses a multi-voltage-domain circuit giving consideration to failure safety and high voltage resistance. The multi-voltage-domain circuit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P19, NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N17 and resistors R1-R3. According to the method, the failure safety and the high voltage resistance are both considered on the multi-voltage-domain IO, and the method can also be applied to the condition that the PAD is in a high-speed waveform, so that the application scene of the failure safety and the high voltage resistance is ensured. The IO is very useful for situations with very complex application scenes, such as FPGA application and some universal industrial chip scenes.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and particularly to a circuit that takes into account failsafe and high voltage tolerance in multiple voltage domains. Background Art

[0002] GPIO is the most important module for a chip to communicate with the outside. For CMOS processes, the common signal voltages are 1.8V, 2.5V, and 3.3V. There are many scenarios where the chip needs to meet the requirements of multiple voltages simultaneously; however, due to speed requirements, the IO devices can only be 1.8V, and the 1.8V devices themselves cannot withstand 2.5V and 3.3V voltages, resulting in a more complex circuit to handle reliability issues. In application scenarios, there are failsafe and HV tolerant situations. Failsafe means that the supply voltage of the IO is 0 while there is voltage on the PAD, which will lead to a large leakage current in the circuit. HV tolerant means that the IO has power supply, but the voltage of the external PAD is greater than the supply voltage of the IO, which will also lead to a large leakage current.

[0003] Although failsafe and HV tolerant seem to be similar, due to the reliability issues of 1.8V devices in multiple voltage domains, it is not easy to be compatible with these two problems, and currently, no circuit that can be compatible with these two functions has been seen.

[0004] Figure 1 It is a schematic diagram of the driving principle in multiple voltage domains. VDDIO and VSSIO are the supply voltage and ground of the IO, and PAD is the point where the IO communicates with the outside. Two PMOS transistors are connected in series to the PAD. The gate terminal of the upper PMOS transistor is connected to the P gate terminal, and the P gate terminal is used to transmit signals. The gate terminal of the lower PMOS transistor is connected to PBIAS, and PBIAS is an isolation voltage used to prevent the PMOS transistor from being damaged. Two NMOS transistors are connected in series to the PAD. The gate terminal of the upper NMOS transistor is connected to NBIAS, and NBIAS is an isolation voltage used to prevent the NMOS transistor from being damaged. The gate terminal of the lower NMOS transistor is connected to the N gate terminal, and the N gate terminal is used to transmit signals.

[0005] Generally, in a multi-voltage domain, VDDIO is used to generate VGND and the 1.8V voltage V1P8. VGND changes with the change of VDDIO. When VDDIO is 1.8V, VGDN = 0V; when VDDIO is 2.5V, VGND = 0.7V; when VDDIO = 3.3V, VGND = 1.5V. When working normally, PBIAS is connected to VGND and NBIAS is connected to V1P8. However, when VDDIO = 0V, both PBIAS and NBIAS are 0, which will not only result in a large current but also reliability problems. Similarly, when the PAD voltage is greater than VDDIO, too low a voltage of VGND will also cause large current and reliability problems. Therefore, a circuit for specially processing PBIAS and NBIAS must be provided. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-voltage domain circuit that takes into account fail-safe and high-voltage resistance to solve the problems in the background technology.

[0007] To solve the above technical problems, the present invention provides a multi-voltage domain circuit that takes into account fail-safe and high-voltage resistance, including: The first module, including PMOS transistors P1 to P3 and resistors R1 to R2; the first module is used to generate the first dynamic supply voltage PAD_1P8. When the external PAD voltage > power supply VDDIO, PAD_1P8 = PAD / 2; when the external PAD voltage <= power supply VDDIO, PAD_1P8 = 0; The second module, including PMOS transistors P4 to P7 and NMOS transistor N1; the second module is used to generate the second dynamic supply voltage ALL_18. When the power supply VDDIO is not powered on, ALL_18 = PAD / 2; when the power supply VDDIO is powered on, ALL_18 = 1.8V; The third module, including PMOS transistors P8 to P11 and NMOS transistor N2; the third module is used to generate the third dynamic supply voltage 18TOVDDIO. When the power supply VDDIO is not powered on, 18TOVDDIO = PAD / 2; when the power supply VDDIO is powered on, 18TOVDDIO = VDDIO; The fourth module, including PMOS transistors P12 to P13 and NMOS transistors N3 to N4; the fourth module is used to generate the isolation voltage PBIAS. When the external PAD voltage > power supply VDDIO, the isolation voltage PBIAS = external PAD voltage; when the external PAD voltage <= VDDIO, the isolation voltage PBIAS = VGND; The fifth module includes PMOS transistors P14 to P19, NMOS transistors N5 to N17, and resistor R3; the fifth module is used to generate the control voltage E required in the fourth module. When the external PAD voltage > power supply VDDIO, the control voltage E = VGND; when the external PAD voltage <= power supply VDDIO, the control voltage E = VDDIO.

[0008] In one implementation, in the first module, The source terminal of PMOS transistor P1 is connected to PAD, the gate terminal is connected to the ALL_18 voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P2; the gate terminal of PMOS transistor P2 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P3; the gate terminal of PMOS transistor P3 is connected to the ALL_18 voltage node, the drain terminal is connected to the first terminal of resistor R1, the second terminal of resistor R1 is connected to the first terminal of resistor R2, the second terminal of resistor R2 is connected to ground VSSIO, and the connection point between resistor R1 and resistor R2 is the PAD_1P8 voltage node.

[0009] In one implementation, in the second module, The source terminal of PMOS transistor P4 is connected to the PAD_1P8 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N1, the source terminal of NMOS transistor N1 is connected to ground VSSIO, and the gate terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the V1P8 voltage node; the drain terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the gate terminal of PMOS transistor P5, the source terminal of PMOS transistor P5 is connected to the V1P8 voltage node, and the drain terminals of PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 are commonly connected to the ALL_18 voltage node; the source terminals of PMOS transistor P6 and the gate terminal of PMOS transistor P7 are both connected to the PAD_1P8 voltage node, and the source terminal of PMOS transistor P7 and the gate terminal of PMOS transistor P6 are both connected to the V1P8 voltage node.

[0010] In one implementation, in the third module, The source terminal of PMOS transistor P8 is connected to the ALL_18 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N2, the source terminal of NMOS transistor N2 is connected to ground VGND, and the gate terminals of PMOS transistor P8 and NMOS transistor N2 are both connected to power supply VDDIO; the drain terminals of PMOS transistor P8 and NMOS transistor N2 are commonly connected to the gate terminal of PMOS transistor P9, the source terminal of PMOS transistor P9 is connected to power supply VDDIO, and the drain terminals of PMOS transistor P9, PMOS transistor P10, and PMOS transistor P11 are commonly connected to the 18TOVDDIO voltage node; the source terminals of PMOS transistor P10 and the gate terminal of PMOS transistor P11 are both connected to the ALL_18 voltage node, and the gate terminal of PMOS transistor P10 and the source terminal of PMOS transistor P11 are both connected to power supply VDDIO.

[0011] In one embodiment, in the fourth module, The source terminal of NMOS transistor N3 is grounded to VGND, the gate terminal is connected to node E, the drain terminal is connected to the source terminal of NMOS transistor N4, the gate terminal of NMOS transistor N4 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the isolation voltage PBIAS; the drain terminal of PMOS transistor P12 is connected to the isolation voltage PBIAS, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of PMOS transistor P13, the gate terminal of PMOS transistor P13 is connected to the ALL_18 voltage node, and the source terminal is connected to PAD.

[0012] In one embodiment, in the fifth module, The drain terminal of PMOS transistor P14 is connected to PAD, the gate terminal is connected to the ALL_18 voltage node, the source terminal is connected to the drain terminal of PMOS transistor P15, the gate terminal of PMOS transistor P15 is connected to the 18TOVDDIO voltage node, and the source terminal is connected to node F; the first terminal of resistor R3 is connected to the power supply VDDIO, the second terminal is simultaneously connected to the drain terminal and the gate terminal of NMOS transistor N5, and the source terminal of NMOS transistor N5 is grounded to VGND; the drain terminal of NMOS transistor N7 is connected to node F, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6 is connected to the drain terminal of NMOS transistor N5, and the source terminal is grounded to VGND; The gate terminal of NMOS transistor N8 is connected to the 18TOVDDIO voltage node, the drain terminal is connected to node F, and the source terminal is simultaneously connected to the gate terminal of NMOS transistor N10 and the gate terminal of PMOS transistor P16; the gate terminal of NMOS transistor N9 is connected to node F, the drain terminal is connected to the 18TOVDDIO voltage node, and the source terminal is simultaneously connected to the gate terminal of NMOS transistor N10 and the gate terminal of PMOS transistor P16; the source terminal of PMOS transistor P16 is connected to the 18TOVDDIO voltage node, the source terminal of NMOS transistor N10 is grounded, and the drain terminal of NMOS transistor N10 and the drain terminal of PMOS transistor P16 are commonly connected to node K; the drain terminal of NMOS transistor N11 is connected to node F, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N12, the source terminal of NMOS transistor N12 is grounded to VGND, and the gate terminal is connected to node K; The drain terminal of the NMOS tube N13 is connected to the 18TOVDDIO voltage node, the gate terminal is connected to the F node, and the source terminal is connected to the G node; the gate terminal and the source terminal of the PMOS tube P17 are both connected to the F node, and the drain terminal is connected to the G node; the source terminal of the PMOS tube P18 is connected to the power supply VDDIO, the gate terminal is connected to the G node, and the drain terminal is connected to the H node; the drain terminal of the NMOS tube N14 is connected to the H node, the gate terminal is connected to the G node, and the source terminal is grounded VGND; the drain terminal of the NMOS tube N16 is connected to the G node, the gate terminal is connected to the power supply VDDIO, the source terminal is connected to the drain terminal of the NMOS tube N15, the gate terminal of the NMOS tube N15 is connected to the H node, and the source terminal is grounded VGND; the source terminal of the PMOS tube P19 is connected to the power supply VDDIO, the gate terminal is connected to the G node, and the drain terminal is connected to the E node; the drain terminal of the NMOS tube N17 is connected to the E node, the gate terminal is connected to the F node, and the source terminal is grounded VGND.

[0013] The present invention provides a multi-voltage domain circuit that takes into account both failsafe and high voltage tolerance. It takes into account both failsafe and HV tolerant on multi-voltage domain IO, and can also be used in the case where PAD is a high-speed waveform, ensuring the application scenarios of failsafe and HV tolerant. This IO is very useful for very complex application scenarios, such as FPGA applications and some general industrial chip scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the multi-voltage domain driving principle.

[0015] Figure 2a It is a structural diagram of part PART1 of a multi-voltage domain circuit that takes into account both failure safety and high voltage resistance provided by the present invention.

[0016] Figure 2b It is a structural diagram of part PART2 of a multi-voltage domain circuit that takes into account both failure safety and high voltage resistance provided by the present invention.

[0017] Figure 2c It is a structural diagram of part PART3 of a multi-voltage domain circuit that takes into account both failure safety and high voltage resistance provided by the present invention.

[0018] Figure 2d It is a structural schematic diagram of PART4 of a multi-voltage domain circuit that takes into account both failure safety and high voltage resistance provided by the present invention.

[0019] Figure 2e It is a structural diagram of part PART5 of a multi-voltage domain circuit that takes into account both failure safety and high voltage resistance provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the PBIAS voltage, ALL_18 voltage, and VDDIO leakage current when PAD=1.8V under Failsafe.

[0021] Figure 4 It is a schematic diagram of the leakage current of the PBIAS voltage, ALL_18 voltage, and VDDIO when PAD = 2.5V under Failsafe.

[0022] Figure 5 It is a schematic diagram of the leakage current of the PBIAS voltage, ALL_18 voltage, and VDDIO when PAD = 3.3V under Failsafe.

[0023] Figure 6 It is a schematic diagram of the leakage current of the PBIAS voltage, ALL_18 voltage, and VDDIO when VDDIO = 1.8V and PAD = 2.5V.

[0024] Figure 7 It is a schematic diagram of the leakage current of the PBIAS voltage, ALL_18 voltage, and VDDIO when VDDIO = 1.8V and PAD = 3.3V.

[0025] Figure 8 It is a schematic diagram of the leakage current of the PBIAS voltage, ALL_18 voltage, and VDDIO when VDDIO = 2.5V and PAD = 3.3V. Detailed implementation mode

[0026] The following further elaborates in detail on a circuit for a multi-voltage domain that takes into account failsafe and high voltage tolerance proposed by the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a circuit for a multi-voltage domain that takes into account failsafe and high voltage tolerance to solve the difficulties in simultaneously handling failsafe and high voltage tolerance in the current multi-voltage domain. Its circuit structure is divided into five parts: The first module PART1 is used to generate a dynamic supply voltage PAD_1P8. When the external PAD voltage > power supply VDDIO, PAD_1P8 = PAD / 2; when the external PAD voltage <= power supply VDDIO, PAD_1P8 = 0; The second module PART2 is used to generate a dynamic supply voltage ALL_18. When the power supply VDDIO is not powered on, ALL_18 = PAD / 2, and when the power supply VDDIO is powered on, ALL_18 = 1.8V; The third module PART3 is used to generate a dynamic supply voltage 18TOVDDIO. When the power supply VDDIO is not powered on, 18TOVDDIO = PAD / 2, and when the power supply VDDIO is powered on, 18TOVDDIO = VDDIO; The fourth module, PART4, is used to generate the isolation voltage PBIAS. When the external PAD voltage > the power supply VDDIO, the isolation voltage PBIAS = the external PAD voltage; when the external PAD voltage <= VDDIO, the isolation voltage PBIAS = VGND. The fifth module, PART5, is used to generate the control voltage E required in the fourth module. When the external PAD voltage > the power supply VDDIO, the control voltage E = VGND; when the external PAD voltage <= the power supply VDDIO, the control voltage E = VDDIO.

[0028] As Figures 2a to 2e shown, these five parts together include: PMOS transistors P1 to P19, NMOS transistors N1 to N17, and resistors R1 to R3.

[0029] PART1: The source terminal of PMOS transistor P1 is connected to PAD, the gate terminal is connected to the ALL_18 voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P2; the gate terminal of PMOS transistor P2 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P3; the gate terminal of PMOS transistor P3 is connected to the ALL_18 voltage node, the drain terminal is connected to the first terminal of resistor R1, the second terminal of resistor R1 is connected to the first terminal of resistor R2, the second terminal of resistor R2 is connected to the ground VSSIO, and the connection point between resistor R1 and resistor R2 is the PAD_1P8 voltage node.

[0030] PART2: The source terminal of PMOS transistor P4 is connected to the PAD_1P8 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N1, the source terminal of NMOS transistor N1 is connected to the ground VSSIO, and the gate terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the V1P8 voltage node; the drain terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the gate terminal of PMOS transistor P5, the source terminal of PMOS transistor P5 is connected to the V1P8 voltage node, and the drain terminals of PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 are commonly connected to the ALL_18 voltage node; the source terminals of PMOS transistor P6 and the gate terminal of PMOS transistor P7 are both connected to the PAD_1P8 voltage node, and the source terminal of PMOS transistor P7 and the gate terminal of PMOS transistor P6 are both connected to the V1P8 voltage node.

[0031] PART 3: The source terminal of PMOS transistor P8 is connected to the ALL_18 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N2, the source terminal of NMOS transistor N2 is grounded to VGND, and the gate terminals of both PMOS transistor P8 and NMOS transistor N2 are connected to the power supply VDDIO; the drain terminals of PMOS transistor P8 and NMOS transistor N2 are jointly connected to the gate terminal of PMOS transistor P9, the source terminal of PMOS transistor P9 is connected to the power supply VDDIO, and the drain terminals of PMOS transistor P9, PMOS transistor P10, and PMOS transistor P11 are jointly connected to the 18TOVDDIO voltage node; the source terminals of PMOS transistor P10 and the gate terminal of PMOS transistor P11 are both connected to the ALL_18 voltage node, and the gate terminal of PMOS transistor P10 and the source terminal of PMOS transistor P11 are both connected to the power supply VDDIO.

[0032] PART 4: The source terminal of NMOS transistor N3 is grounded to VGND, the gate terminal is connected to node E, the drain terminal is connected to the source terminal of NMOS transistor N4, the gate terminal of NMOS transistor N4 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the isolation voltage PBIAS; the drain terminal of PMOS transistor P12 is connected to the isolation voltage PBIAS, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of PMOS transistor P13, the gate terminal of PMOS transistor P13 is connected to the ALL_18 voltage node, and the source terminal is connected to PAD.

[0033] PART 5: The drain terminal of PMOS transistor P14 is connected to PAD, the gate terminal is connected to the ALL_18 voltage node, the source terminal is connected to the drain terminal of PMOS transistor P15, the gate terminal of PMOS transistor P15 is connected to the 18TOVDDIO voltage node, and the source terminal is connected to node F; the first terminal of resistor R3 is connected to the power supply VDDIO, and the second terminal is simultaneously connected to the drain terminal and the gate terminal of NMOS transistor N5, and the source terminal of NMOS transistor N5 is grounded to VGND; the drain terminal of NMOS transistor N7 is connected to node F, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6 is connected to the drain terminal of NMOS transistor N5, and the source terminal is grounded to VGND; The gate terminal of NMOS transistor N8 is connected to the 18TOVDDIO voltage node, the drain terminal is connected to node F, and the source terminal is simultaneously connected to the gate terminals of NMOS transistor N10 and PMOS transistor P16; the gate terminal of NMOS transistor N9 is connected to node F, the drain terminal is connected to the 18TOVDDIO voltage node, and the source terminal is simultaneously connected to the gate terminals of NMOS transistor N10 and PMOS transistor P16; the source terminal of PMOS transistor P16 is connected to the 18TOVDDIO voltage node, the source terminal of NMOS transistor N10 is grounded, and the drain terminals of NMOS transistor N10 and PMOS transistor P16 are jointly connected to node K; the drain terminal of NMOS transistor N11 is connected to node F, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N12, the source terminal of NMOS transistor N12 is grounded to VGND, and the gate terminal is connected to node K; The drain terminal of NMOS transistor N13 is connected to the 18TOVDDIO voltage node, the gate terminal is connected to node F, and the source terminal is connected to node G; the gate terminal and the source terminal of PMOS transistor P17 are both connected to node F, and the drain terminal is connected to node G; the source terminal of PMOS transistor P18 is connected to power supply VDDIO, the gate terminal is connected to node G, and the drain terminal is connected to node H; the drain terminal of NMOS transistor N14 is connected to node H, the gate terminal is connected to node G, and the source terminal is grounded to VGND; the drain terminal of NMOS transistor N16 is connected to node G, the gate terminal is connected to power supply VDDIO, the source terminal is connected to the drain terminal of NMOS transistor N15, the gate terminal of NMOS transistor N15 is connected to node H, and the source terminal is grounded to VGND; the source terminal of PMOS transistor P19 is connected to power supply VDDIO, the gate terminal is connected to node G, and the drain terminal is connected to node E; the drain terminal of NMOS transistor N17 is connected to node E, the gate terminal is connected to node F, and the source terminal is grounded to VGND.

[0034] The circuit structure of the present invention will be explained below: 1. For the structure of PART1, please refer to Figure 2a , three PMOS transistors (P1, P2, P3) and two resistors (R1 and R2) are connected in series from PAD to ground VSSIO. The gate terminals of PMOS transistors P1 and P3 are both connected to the ALL_18 voltage node, and the gate terminal of the middle PMOS transistor P2 is connected to the 18TOVDDIO voltage node. The resistances of resistor R1 and resistor R2 are equal, and the connection point of resistor R1 and resistor R2 is the PAD_1P8 voltage node.

[0035] 2. For the structure of PART2, please refer to Figure 2b , on the leftmost side is an inverter composed of NMOS transistor N1 and PMOS transistor P4, the power supply is the voltage of node PAD_1P8, and the ground is VSSIO. The output of the inverter is connected to the gate terminal of PMOS transistor P5, the source terminal of PMOS transistor P5 is connected to the V1P8 voltage node, and the drain terminal is connected to the ALL_18 voltage node. On the right is a latch composed of PMOS transistors P6 and P7. The inputs of the latch are the PAD_1P8 voltage node (i.e., the connection terminal of resistor R1 and resistor R2) and the V1P8 voltage node, and the output of the latch is the ALL_18 voltage node.

[0036] 3. For the structure of PART3, please refer to Figure 2c , on the leftmost side is an inverter composed of NMOS transistor N2 and PMOS transistor P8, the power supply is the voltage of node ALL_18, and the ground is VGND. The output of the inverter is connected to the gate terminal of PMOS transistor P9, the source terminal of PMOS transistor P9 is connected to the supply voltage VDDIO, and the drain terminal is connected to the 18TOVDDIO voltage node. On the right is a latch composed of PMOS transistors P10 and P11. The inputs of the latch are the ALL_18 voltage node and the supply voltage VDDIO, and the output of the latch is the 18TOVDDIO voltage node.

[0037] 4. For the structure of PART4, please refer to Figure 2d . On the left, NMOS transistors N3 and N4 are connected in series. The gate terminal of NMOS transistor N3 is connected to point E, and the source terminal is connected to VGND. The gate terminal of NMOS transistor N4 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the isolation voltage PBIAS. On the right, PMOS transistors P12 and P13 are connected in series. The drain terminal of PMOS transistor P12 is connected to the isolation voltage PBIAS, and the gate terminal is connected to the 18TOVDDIO voltage node. The gate terminal of PMOS transistor P13 is connected to the ALL_18 voltage node, and the source terminal is connected to PAD.

[0038] 5. For the structure of PART5, please refer to Figure 2e . In the upper left corner, PMOS transistors P14 and P15 are connected in series. The gate terminals of PMOS transistors P14 and P15 are connected to the ALL_18 voltage node and the 18TOVDDIO voltage node respectively. The drain terminal of PMOS transistor P14 is connected to PAD, and the source terminal of PMOS transistor P15 is connected to point F.

[0039] NMOS transistor N5 is connected in diode mode. Its source terminal is connected to VGND, and the gate terminal and drain terminal are both connected to one end of resistor R3, and also connected to the gate terminal of NMOS transistor N6. The other end of resistor R3 is connected to VDDIO. NMOS transistors N6 and N7 are connected in series. The source terminal of NMOS transistor N6 is connected to VGND, the drain terminal of NMOS transistor N7 is connected to point F, and the gate terminal of NMOS transistor N7 is connected to the 18TOVDDIO voltage node.

[0040] The gate terminal of NMOS transistor N8 is connected to the 18TOVDDIO voltage node, the source terminal is connected to the gate terminals of PMOS transistor P16 and NMOS transistor N10, and the drain terminal of NMOS transistor N8 is connected to point F. The gate terminal of NMOS transistor N9 is connected to point F, the drain terminal is connected to the 18TOVDDIO voltage node, and the source terminal is connected to the gate terminals of PMOS transistor P16 and NMOS transistor N10.

[0041] PMOS transistor P16 and NMOS transistor N10 form an inverter. The power supply is the voltage of the 18TOVDDIO voltage node, the ground is VGND, and the output is the K node. NMOS transistors N11 and N12 are connected in series. The drain terminal of NMOS transistor N11 is connected to point F, and the gate terminal is connected to the 18TOVDDIO voltage node. The gate terminal of NMOS transistor N13 is connected to point F, the drain terminal is connected to the 18TOVDDIO voltage node, and the source terminal is connected to point G. PMOS transistor P17 is connected in diode mode. Its gate terminal and source terminal are connected to point F, and the drain terminal is connected to point G.

[0042] The PMOS transistor P18 and the NMOS transistor N14 form an inverter. The input of the inverter is connected to the G node. The source terminal of the PMOS transistor P18 is connected to the power supply VDDIO, and the source terminal of the NMOS transistor N14 is grounded to VGND. The output of the inverter is the H node. The NMOS transistors N15 and N16 are connected in series. The gate terminal of the NMOS transistor N16 is connected to the power supply voltage VDDIO, and the drain terminal is connected to the G node. The gate terminal of the NMOS transistor N5 is connected to the H node, and the source terminal is grounded to VGND. The PMOS transistor P19 and the NMOS transistor N17 form an inverter. The input of the inverter is connected to the G node, and the output is connected to the E node. The source terminal of the PMOS transistor P19 is connected to the power supply VDDIO, and the source terminal of the NMOS transistor N17 is grounded to VGND.

[0043] The working principle of the circuit of the present invention will be described below: 1. In PART1, when the voltage of the PAD is greater than the power supply voltage VDDIO, the resistors R1 and R2 divide the voltage of the PAD. Therefore, the maximum voltage of the PAD_1P8 voltage node is 1.8V. When the voltage of the PAD is less than or equal to VDDIO, the voltage of the PAD is isolated. Therefore, the voltage of the PAD_1P8 voltage node is 0. The PMOS transistors P1 and P3 play an isolation and protection role.

[0044] 2. In PART2, when VDDIO = 0, the voltage of the ALL_18 voltage node is equal to the voltage of the PAD_1P8 node. When VDDIO is powered on, the voltage of the ALL_18 node is 1.8V. However, when the voltages of the PAD_1P8 node and the V1P8 node are very close, the driving ability of the ALL_18 voltage node is too small. Therefore, the PMOS transistor P5 is used to solve this problem. When VDDIO is not powered on, the gate terminal of the PMOS transistor P5 is equal to the voltage of the PAD_1P8 node, preventing the voltage of the ALL_18 voltage node from flowing to the ground and causing inaccurate voltage. When VDDIO is powered on, the gate terminal of the PMOS transistor P5 is connected to 0. At this time, the PMOS transistor P5 can provide the driving ability of the ALL_18 voltage node.

[0045] 3. The principle of PART3 is similar to that of PART2, but the voltage generated is from 1.8V to VDDIO. When VDDIO is not powered on, the voltage of the PAD_1P8 node is generated. When VDDIO is powered on, the voltage of VDDIO is generated.

[0046] 4. PART4 is used to generate the isolation voltage PBIAS. When the voltage of the PAD is greater than VDDIO, the PAD transfers the voltage to the isolation voltage PBIAS through the PMOS transistors P12 and P13. At this time, the voltage of the E node is VGND, preventing the isolation voltage PBIAS from connecting to VGND. The NMOS transistor N4 plays an isolation and protection role. When the voltage of the PAD is less than or equal to VDDIO, the isolation voltage PBIAS is connected to VGND through the NMOS transistors N3 and N4, while the PMOS transistors P12 and P13 isolate PBIAS and the PAD.

[0047] 5. PART5 is used to generate the voltage of the E node. When the PAD voltage is greater than VDDIO, the voltage of the E node is VGND. When the voltage of the PAD is less than or equal to VDDIO, the voltage of the E node is VDDIO. The resistor R3 is a very large resistor in series with the NMOS transistor N5. As a result, the difference between the gate voltage of the NMOS transistor N6 and VGND is close to the threshold voltage Vth. Therefore, there is a very small current from the NMOS transistor N6 to VGND. When the voltage of the PAD is less than or equal to VDDIO, the PMOS transistors P14 and P15 isolate the F node and the PAD point. Therefore, the voltage of the F node is VGND. Here, the NMOS transistors N8, N9, N10, N11, N12 and the PMOS transistor P16 form a positive feedback circuit, fixing the F node at VGND. Due to the effect of the PMOS transistor P17, the voltage of the G node cannot be higher than VGND + Vth. Since the PMOS transistor P18, the NMOS transistors N14, N15 and N16 form a positive feedback circuit, the voltage of the G node will be fixed at VGND. At this time, the voltage of the E node is VDDIO. When the voltage of the PAD is greater than VDDIO, the voltage of the F node is the voltage of the PAD. At this time, the voltage of the K node is VGND. Therefore, the F node is isolated from VGND. At this time, the voltage of the G node is VDDIO. At this time, the connection between the G node and VGND is interrupted. Therefore, the voltage of the E node is VGND.

[0048] The isolation voltage PBIAS in the circuit of the present invention is used to connect to Figure 1 the PBIAS point in Figure 1 The ALL_18 voltage node is used to connect to

[0049] Based on the GF22FDX process, simulations were carried out at a typical 25 0 °C.

[0050] Figures 3 to 5Under failsafe, it is the voltages of PBIAS and ALL_18 nodes and the leakage current of VDDIO when PAD is 1.8V, 2.5V, and 3.3V respectively. It can be seen from the figure that both the voltage and current meet the expected values. Figure 6 and Figure 7 It is the voltages of PBIAS and ALL_18 and the leakage current of VDDIO when VDDIO = 1.8V and PAD is 2.5V and 3.3V respectively; Figure 8 It is the voltages of PBIAS and ALL_18 and the leakage current of VDDIO when VDDIO = 2.5V and PAD = 3.3V.

[0051] The circuit structure of PART1 ensures that when the PAD voltage is less than or equal to VDDIO, the PAD will not be directly applied to resistors R1 and R2, reducing the current; The circuit structures of PART2 and PART3 ingeniously generate ALL_18 and 18TOVDDIO voltages, which play very important roles in the reliability of the circuit.

[0052] In the circuit structure of PART5, when the PAD voltage is greater than VDDIO, the voltage of node E is VGND. When the PAD voltage is less than or equal to VDDIO, the voltage of node E is VDDIO. Resistor R3 is a very large resistor in series with NMOS transistor N5. As a result, the voltage difference between the gate terminal of NMOS transistor N6 and VGND is close to Vth. Therefore, there is a very small current from NMOS transistor N6 to VGND. When the PAD voltage is less than or equal to VDDIO, PMOS transistors P14 and P15 isolate node F and the PAD point. Therefore, the voltage of node F is VGND. This is where NMOS transistors N8, N9, N10, N11, N12 and PMOS transistor P16 form a positive feedback circuit to fix node F at VGND. Due to the effect of PMOS transistor P17, the voltage of node G cannot be higher than VGND + Vth. Since PMOS transistor P18, NMOS transistors N14, N15, and N16 form a positive feedback circuit, the voltage of node G will be fixed at VGND. At this time, the voltage of node E is VDDIO. When the PAD voltage is greater than VDDIO, the voltage of node F is the PAD voltage. At this time, the voltage of node K is VGND. Therefore, node F to VGND is isolated. At this time, the voltage of node G is VDDIO. At this time, the connection between node G and VGND is cut off. Therefore, the voltage of node E is VGND. This circuit ingeniously uses the positive feedback structure to solve the problem that when the PAD voltage is less than VDDIO, PBIAS can decrease quickly. Therefore, this circuit can actually be used for failsafe and HV tolerant applications where PAD is under high-speed waveforms.

[0053] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A multi-voltage domain circuit that takes into account fail-safe and high-voltage tolerance, characterized in that Comprising: A first module, including PMOS transistors P1 to P3 and resistors R1 to R2; the first module is used to generate a first dynamic supply voltage PAD_1P8, when the external PAD voltage > power supply VDDIO, PAD_1P8 = PAD / 2; when the external PAD voltage <= power supply VDDIO, PAD_1P8 = 0; A second module, including PMOS transistors P4 to P7 and NMOS transistor N1; the second module is used to generate a second dynamic supply voltage ALL_18, when the power supply VDDIO is not powered on, ALL_18 = PAD / 2, when the power supply VDDIO is powered on, ALL_18 = 1.8V; A third module, including PMOS transistors P8 to P11 and NMOS transistor N2; the third module is used to generate a third dynamic supply voltage 18TOVDDIO, when the power supply VDDIO is not powered on, 18TOVDDIO = PAD / 2, when the power supply VDDIO is powered on, 18TOVDDIO = VDDIO; A fourth module, including PMOS transistors P12 to P13 and NMOS transistors N3 to N4; the fourth module is used to generate an isolation voltage PBIAS, when the external PAD voltage > power supply VDDIO, the isolation voltage PBIAS = external PAD voltage; when the external PAD voltage <= VDDIO, the isolation voltage PBIAS = VGND; A fifth module, including PMOS transistors P14 to P19, NMOS transistors N5 to N17 and resistor R3; the fifth module is used to generate the control voltage E required in the fourth module, when the external PAD voltage > power supply VDDIO, the control voltage E = VGND; when the external PAD voltage <= power supply VDDIO, the control voltage E = VDDIO.

2. The circuit with multiple voltage domains considering fail-safe and high-voltage tolerance as claimed in claim 1, wherein In the first module, The source terminal of PMOS transistor P1 is connected to PAD, the gate terminal is connected to the ALL_18 voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P2; the gate terminal of PMOS transistor P2 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the source terminal of PMOS transistor P3; the gate terminal of PMOS transistor P3 is connected to the ALL_18 voltage node, the drain terminal is connected to the first end of resistor R1, the second end of resistor R1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to ground VSSIO, and the connection point between resistor R1 and resistor R2 is the PAD_1P8 voltage node.

3. The multi-voltage-domain circuit that takes into account fail-safe and high-voltage tolerance as described in claim 1, wherein In the second module, The source terminal of PMOS transistor P4 is connected to the PAD_1P8 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N1, the source terminal of NMOS transistor N1 is grounded to VSSIO, and the gate terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the V1P8 voltage node; the drain terminals of PMOS transistor P4 and NMOS transistor N1 are commonly connected to the gate terminal of PMOS transistor P5, the source terminal of PMOS transistor P5 is connected to the V1P8 voltage node, and the drain terminals of PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 are commonly connected to the ALL_18 voltage node; the source terminal of PMOS transistor P6 and the gate terminal of PMOS transistor P7 are both connected to the PAD_1P8 voltage node, and the source terminal of PMOS transistor P7 and the gate terminal of PMOS transistor P6 are both connected to the V1P8 voltage node.

4. The multi-voltage domain circuit that takes into account fail-safe and high-voltage tolerance as described in claim 1, wherein, In the third module, The source terminal of PMOS transistor P8 is connected to the ALL_18 voltage node, the drain terminal is connected to the drain terminal of NMOS transistor N2, the source terminal of NMOS transistor N2 is grounded to VGND, and the gate terminals of PMOS transistor P8 and NMOS transistor N2 are both connected to the power supply VDDIO; the drain terminals of PMOS transistor P8 and NMOS transistor N2 are commonly connected to the gate terminal of PMOS transistor P9, the source terminal of PMOS transistor P9 is connected to the power supply VDDIO, and the drain terminals of PMOS transistor P9, PMOS transistor P10, and PMOS transistor P11 are commonly connected to the 18TOVDDIO voltage node; the source terminal of PMOS transistor P10 and the gate terminal of PMOS transistor P11 are both connected to the ALL_18 voltage node, and the gate terminal of PMOS transistor P10 and the source terminal of PMOS transistor P11 are both connected to the power supply VDDIO.

5. The circuit with multiple voltage domains that takes into account fail-safe and high-voltage tolerance as described in claim 1, characterized in that In the fourth module, The source terminal of NMOS transistor N3 is grounded to VGND, the gate terminal is connected to the E node, the drain terminal is connected to the source terminal of NMOS transistor N4, the gate terminal of NMOS transistor N4 is connected to the 18TOVDDIO voltage node, and the drain terminal is connected to the isolation voltage PBIAS; the drain terminal of PMOS transistor P12 is connected to the isolation voltage PBIAS, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of PMOS transistor P13, the gate terminal of PMOS transistor P13 is connected to the ALL_18 voltage node, and the source terminal is connected to the PAD.

6. The circuit with multiple voltage domains considering fail-safe and high voltage tolerance as claimed in claim 1, wherein In the fifth module, The drain terminal of PMOS transistor P14 is connected to the PAD, the gate terminal is connected to the ALL_18 voltage node, the source terminal is connected to the drain terminal of PMOS transistor P15, the gate terminal of PMOS transistor P15 is connected to the 18TOVDDIO voltage node, and the source terminal is connected to the F node; the first terminal of resistor R3 is connected to the power supply VDDIO, the second terminal is simultaneously connected to the drain terminal and the gate terminal of NMOS transistor N5, and the source terminal of NMOS transistor N5 is grounded to VGND; the drain terminal of NMOS transistor N7 is connected to the F node, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N6, the gate terminal of NMOS transistor N6 is connected to the drain terminal of NMOS transistor N5, and the source terminal is grounded to VGND; The gate terminal of NMOS transistor N8 is connected to the 18TOVDDIO voltage node, the drain terminal is connected to the F node, and the source terminal is simultaneously connected to the gate terminals of NMOS transistor N10 and PMOS transistor P16; the gate terminal of NMOS transistor N9 is connected to the F node, the drain terminal is connected to the 18TOVDDIO voltage node, and the source terminal is simultaneously connected to the gate terminals of NMOS transistor N10 and PMOS transistor P16; the source terminal of PMOS transistor P16 is connected to the 18TOVDDIO voltage node, the source terminal of NMOS transistor N10 is grounded, and the drain terminals of NMOS transistor N10 and PMOS transistor P16 are commonly connected to the K node; the drain terminal of NMOS transistor N11 is connected to the F node, the gate terminal is connected to the 18TOVDDIO voltage node, the source terminal is connected to the drain terminal of NMOS transistor N12, the source terminal of NMOS transistor N12 is grounded to VGND, and the gate terminal is connected to the K node; The drain terminal of NMOS transistor N13 is connected to the 18TOVDDIO voltage node, the gate terminal is connected to the F node, and the source terminal is connected to the G node; the gate terminal and the source terminal of PMOS transistor P17 are both connected to the F node, and the drain terminal is connected to the G node; the source terminal of PMOS transistor P18 is connected to the power supply VDDIO, the gate terminal is connected to the G node, and the drain terminal is connected to the H node; the drain terminal of NMOS transistor N14 is connected to the H node, the gate terminal is connected to the G node, and the source terminal is grounded to VGND; the drain terminal of NMOS transistor N16 is connected to the G node, the gate terminal is connected to the power supply VDDIO, the source terminal is connected to the drain terminal of NMOS transistor N15, the gate terminal of NMOS transistor N15 is connected to the H node, and the source terminal is grounded to VGND; the source terminal of PMOS transistor P19 is connected to the power supply VDDIO, the gate terminal is connected to the G node, and the drain terminal is connected to the E node; the drain terminal of NMOS transistor N17 is connected to the E node, the gate terminal is connected to the F node, and the source terminal is grounded to VGND.

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