Six-input 4-bit successive approximation quantizer with embedded feedforward coefficient

Abstract

The invention provides a six-input 4-bit successive approximation type quantizer with an embedded feed-forward coefficient, and relates to an analog integrated circuit. The quantizer comprises a capacitive digital-to-analog converter, a comparator and an asynchronous successive approximation digital logic circuit; the capacitive digital-to-analog converter is composed of a group of binary increasing capacitors. According to the quantizer, the operation of proportionally adding a feed-forward path and the output of each stage of integrator is embedded on a capacitance type digital-to-analog converter capacitor of a 4-bit successive approximation type analog-to-digital converter. During sampling, upper and lower polar plates of a capacitor of the capacitive digital-to-analog converter perform sampling operation at the same time. After sampling is completed, the upper and lower polar plates of the capacitor are disconnected with the six input sources. The lower electrode plates of the capacitors are connected to a common mode voltage VCM, at the moment, signals are input at the joint of the upper electrode plates of the capacitors and the input end of the comparator after proportional addition, the addition result is sent to asynchronous logic for dichotomy search, 4-bit digital codes are obtained in sequence, and therefore the quantization process is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly relates to a six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient. Background Art

[0002] Delta-Sigma data converters have been widely used in fields such as low-power high-precision narrow-bandwidth sensor signal data conversion and high-precision audio signal data conversion, and have become one of the most popular converter structures at present. First-order Delta-Sigma data converters require a larger oversampling ratio to meet the expected accuracy requirements and are more susceptible to idle tones. In contrast, second-order Delta-Sigma data converters are more widely used. To reduce the output swing of the integrator and improve linearity, the second-order structure usually contains a feedforward branch. As Figure 1 shown, the Silva–Steensgaard structure is a common second-order feedforward structure. It needs to add the input signal, the first-stage integrator signal, and the second-stage integrator signal in the ratio of 1:2:1, and the added signal is sent to the quantizer for multi-bit quantization. To achieve this goal, passive capacitor addition is usually used to add the signals of each stage and subtract them from the quantization level signals of each stage for multi-bit quantization and then sent to a two-input comparator. A 4-bit quantizer requires 16 different reference levels, which requires a voltage-dividing resistor string that consumes static power to generate. In addition, 16 passive adders are needed to achieve the proportional addition of the signals of each branch, and 16 flash-type comparators are needed to perform comparisons respectively. This will lead to additional circuit overhead, occupy a larger chip area, and consume more power.

[0003] In view of the prior art, the present invention aims to improve the quantizer of the traditional feedforward structure second-order Delta-Sigma data converter to solve the problem that the traditional multi-bit quantizer requires reference levels and multiple sets of passive adders and quantizers, thereby increasing the hardware overhead. Summary of the Invention

[0004] The object of the present invention is to provide a multi-bit quantizer circuit structure with low power consumption, simple structure, small chip area occupation, and an embedded feedforward coefficient to meet the implementation of the transfer function of a second-order Delta-Sigma data converter with a feedforward branch. To achieve the above object, the technical solution adopted by the present invention is as follows:

[0005] A six-input 4-bit successive approximation quantizer with embedded feedforward coefficients. The successive approximation quantizer includes a capacitive digital-to-analog converter, a comparator, and an asynchronous successive approximation digital logic circuit. The upper and lower plates of the capacitors in the capacitive digital-to-analog converter are disconnected from the input signal after sampling is completed, so that the capacitive digital-to-analog converter performs charge redistribution. The difference between the voltages of the upper and lower plates is the input signal after proportional addition.

[0006] Optionally, after the charge redistribution of the capacitive digital-to-analog converter, the comparator is triggered to perform a comparison, thereby completing the first comparison. The asynchronous successive approximation digital logic circuit is used to latch the result after the comparison. The capacitive digital-to-analog converter is used to connect the lower plate of the MSB capacitor on the higher-level side to GND according to the logical value of the first comparison, and connect the lower plate of the MSB capacitor on the lower-level side to V REF , thus raising the level of the originally lower-level end and lowering the level of the originally higher-level end. After the capacitive digital-to-analog converter is re-established, the asynchronous successive approximation digital logic circuit is used to trigger the comparator to enter the second comparison. The result after the second comparison and the result after the first comparison are jointly latched in the asynchronous successive approximation digital logic circuit. The capacitive digital-to-analog converter is used to execute the step of connecting the lower plate of the MSB capacitor on the higher-level side to GND according to the logical value of the first comparison and connecting the lower plate of the MSB capacitor on the lower-level side to VREF according to the result after the second comparison, thereby raising the level of the originally lower-level end and lowering the level of the originally higher-level end. After the comparator triggers four comparisons, the asynchronous successive approximation digital logic circuit is used to merge and output the results after each comparison to obtain the 4-bit quantized result.

[0007] Optionally, during the charge redistribution process after sampling is completed in the successive approximation quantizer, the upper and lower plates of half of the capacitors in the capacitive digital-to-analog converter are sequentially connected to V REF or GND according to the result of the comparison by the comparator, and the lower plates of the other half of the capacitors in the capacitive digital-to-analog converter are always connected to the common-mode voltage V CM , which is equivalent to multiplying by a coefficient of 0.5 on V REF , thereby reducing the voltage change amount of each successive approximation by half.

[0008] Optionally, the digital code obtained by each comparison of the comparator is stored by a dynamic logic chain. The dynamic logic chain is used to store the digital code obtained by the current comparison, reset the comparator, and trigger the next comparison clock until all comparisons are completed.

[0009] Optionally, the successive approximation quantizer is implemented using a fully differential circuit.

[0010] The six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient of the present invention has the following beneficial effects compared with the prior art:

[0011] On the premise of realizing the same transfer function, by embedding the feedforward addition into the capacitive digital-to-analog converter of the successive approximation analog-to-digital converter and using the successive approximation method to implement the binary search and serial comparison, the multi-bit quantization results are output one by one. The circuit scale is small and the implementation method is simple. Brief Description of the Drawings

[0012] Figure 1 is a structural block diagram of an exemplary second-order feedforward structure Delta-Sigma data converter;

[0013] Figure 2 is a schematic diagram of the overall structural framework of the six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient of the present invention;

[0014] Figure 3 is a circuit implementation diagram of a 4-bit successive approximation quantizer with an embedded feedforward coefficient;

[0015] Figure 4 is a circuit timing diagram of a 4-bit successive approximation quantizer with an embedded feedforward coefficient;

[0016] Figure 5 is a circuit implementation diagram of a dynamic logic circuit module;

[0017] Figure 6 is a circuit implementation diagram of a dynamic logic chain.

[0018] Reference Numerals: 1 - Capacitive Digital-to-Analog Converter (CDAC), 2 - Comparator, 3 - Asynchronous Successive Approximation (SAR) Digital Logic Circuit. Detailed Embodiment

[0019] The present invention will be further described below with reference to the embodiments and the accompanying drawings, but the protection scope of the present invention should not be limited thereby.

[0020] Refer to Figure 2 , this embodiment provides a six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient, and the successive approximation quantizer includes: a capacitive digital-to-analog converter (CDAC), a comparator, and an asynchronous successive approximation digital logic circuit.

[0021] Among them, the six input ends complete the addition operation according to the set ratio during the CDAC sampling, and then the CDAC performs a reset operation. The voltage difference between the positive and negative input ends of the comparator is satisfies the proportional relationship. During the successive approximation quantization operation, the capacitors with capacitances of 4C, 2C, and C on the CDAC are connected to V at the lower plates in sequence according to the result of the previous comparison REFOr GND, which is equivalent to the added signal and V REF / 2 comparison. The added signal and V REF are both reduced by half, which is equivalent to 2·(V 1P -V 1N ) + 1·(V IP -V IN ) + 1·(V 2P -V 2N ) and V REF comparison, satisfying the relationship of the transfer function in Figure 1 .

[0022] Preferably, as shown in Figure 3 , the CDAC capacitor array of this embodiment is composed of 5 capacitors with sizes of 8C, 4C, 2C, 1C, and 1C. The lower plate of the 8C capacitor is used to sample the output signal from the second integrator. The lower plates of the 4C, 2C, and two 1C capacitors are connected together during sampling for sampling the input signal. The output signal of the first-stage integrator is sampled on the upper plates of all capacitors. After sampling is completed, the lower plates of all capacitors are connected to the common-mode voltage V CM . At this time, the voltage at the positive input terminal of the comparator is and the voltage at the negative input terminal is . Subtracting the two gives V CMP .

[0023] Preferably, the timing of the successive approximation quantizer in this embodiment is as shown in Figure 4 . ck s is the sampling clock, and the sampling time accounts for 1 / 6 of the total quantization time. After sampling is completed, the SPOVER clock is pulled high, and the lower plates of all CDAC capacitors are connected to V CM . The weighted signal voltage starts to be established at the connection between the CDAC and the input terminal of the comparator. CMP is the comparator control clock. When CMP is high, the comparator starts to compare. When it is low, the comparator is reset, and both the positive and negative terminals output high levels. After four comparisons, through the delay of the inverter chain, the sampling of the four comparison results is triggered respectively. The clocks ck1 to ck4 control four dynamic logic modules as shown in Figure 5 . This module locks the bit comparison result after receiving a high level at the Q terminal. After four comparisons are completed, the CMPOK signal is pulled high to indicate that quantization is completed, and the dynamic logic chain outputs the 4-bit comparison result and updates it on the DOUT bus.

[0024] To further illustrate the solution of the present invention, a more detailed description of the implementation manner will be given next.

[0025] This embodiment implements a six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient.

[0026] Still referring toFigure 2 The six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient includes a capacitive digital-to-analog converter (CDAC) 1, a comparator 2, and a successive approximation (SAR) logic circuit 3. The output terminal of the capacitive digital-to-analog converter 1 is connected to the input terminal of the comparator 2, and the digital code output by the comparator is connected to the input terminal of the successive approximation logic circuit 3.

[0027] Figure 3 It is a circuit schematic diagram of the four-bit successive approximation quantizer with an embedded feedforward coefficient of the present invention. As Figure 3 shown, the CDAC module is respectively composed of 8-fold, 4-fold, 2-fold, and two 1-fold unit capacitance capacitors. Figure 1 The switch state in the figure is in the sampling state. V 1P and V 1N represent the positive and negative terminal voltages of the output from the first-stage integrator, V 2P and V 2N represent the positive and negative voltages of the output from the second-stage integrator, V IP and V IN represent the voltages of the positive and negative input signals, with a total of six input terminals.

[0028] After the sampling is completed, the electric charge Q1 stored on the upper plate of the positive-terminal CDAC capacitor is equal to the electric charge Q2 stored on the upper plate of the positive-terminal CDAC capacitor after the sampling ends. There is (V 1P -V IN )·8C+(V 1P -V 2N )·8C=(V P (1)-V CM )·16C. From this, Similarly, By subtracting the two, we can get Satisfying the relationship of the transfer function in Figure 1 .

[0029] The successive approximation logic uses the binary search method to find the corresponding input voltage. After the sampling is completed and the CDAC voltage is established, the first comparison is first completed to distinguish the voltage levels of the positive and negative input terminals of the comparator. During successive approximation, according to the output result of the first comparator, the input terminal with the higher voltage is reduced by V REF / 8, and the input terminal with the lower voltage is raised by V REF / 8, and then sent to the comparator for the second comparison again. The input terminal with the higher voltage is reduced by V REF / 16, and the input terminal with the lower voltage is raised by V REF / 16. In this way, a total of four comparisons are made to generate the output code of the 4-bit quantizer. In the way of this binary search, it is equivalent to between +V REF and -V REFWithin the interval, the weighted input signal 2·(V 1P -V 1N ) + 1·(V IP -V IN ) + 1·(V 2P -V 2N ) is quantized in 16 steps.

[0030] Figure 4 is the circuit timing of the four-bit successive approximation quantizer with the feedforward coefficient embedded in the present invention. The sampling clock ck s is used to control the sampling state of the quantizer. The sampling end clock SPOVER controls the connection of the lower plates of the capacitors of the CDAC to V CM after the sampling ends. CMP is the comparator comparison clock. The data valid clocks ck1~ck4 control the dynamic logic to sample the comparison results sequentially. The CMPOK clock is used to indicate the end of all comparisons and update the 4-bit DOUT digital code.

[0031] Figure 5 is the schematic diagram of the dynamic logic circuit adopted in the successive approximation logic of the present invention. The dynamic logic module locks the IP and IN digital codes from the comparator after receiving the falling edge signal of VALID, and transfers the D high-level signal to Q, thereby starting to receive the comparison results of the next comparator. D is the enable signal of the dynamic logic. When D is high, the module is enabled. IP and IN are the comparison results output by the comparator and serve as the input signals of the dynamic logic. VALID is the latch signal. At the falling edge of VALID, the dynamic logic latches the comparison results of the comparator. OP and ON output the stored results of the dynamic logic. Q is the latch completion indication signal. After the dynamic logic module completes the latching, Q is raised to a high level to indicate that the next-level dynamic logic enters the sampling state. DVDD and DVSS are the digital power supply and digital ground for powering the dynamic logic.

[0032] Figure 6 is a dynamic logic chain composed of dynamic logics and is a key module in the successive approximation digital logic. The quantization results after each successive approximation are latched in four cascaded dynamic logic gates and trigger the next successive approximation operation until the four comparisons are completed. At the rising edge of the CMPOK clock, the four-bit comparison results are read out from this chain and the logic chain is reset.

[0033] The four-bit successive approximation quantizer with the feedforward coefficient embedded in this embodiment, on the premise of keeping the original transfer function unchanged, embeds the operation of adding the input signals in proportion into the CDAC, and then uses the binary search method to successively approximate the result after the addition is completed to obtain the 4-bit quantization result. It is applicable to the applications of second-order and higher-order Delta-Sigma data converter circuits with a feedforward structure.

[0034] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and supplements can be made, and these improvements and supplements should also be regarded as the protection scope of the present invention.

Claims

1. A six-input 4-bit successive approximation quantizer with embedded feedforward coefficients, characterized in that The successive approximation quantizer includes a capacitive digital-to-analog converter, a comparator, and an asynchronous successive approximation digital logic circuit; the upper and lower plates of the capacitor in the capacitive digital-to-analog converter are disconnected from the input signal after sampling is completed, so that the capacitive digital-to-analog converter performs charge redistribution, and the difference between the voltages of the upper and lower plates is the input signal after proportional summation.

2. The six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient according to claim 1, wherein After charge redistribution in the capacitive digital-to-analog converter, the comparator is triggered to perform a comparison, thereby completing the first comparison. The asynchronous successive approximation digital logic circuit is used to latch the result after the comparison. The capacitive digital-to-analog converter is used to connect the lower plate of the MSB capacitor on the higher-level side to GND according to the logical value of the first comparison, and connect the lower plate of the MSB capacitor on the lower-level side to V REF REF, so as to raise the level of the originally lower-level end and lower the level of the originally higher-level end. After the capacitive digital-to-analog converter is re-established, the asynchronous successive approximation digital logic circuit is used to trigger the comparator to enter the second comparison. The result after the second comparison and the result after the first comparison are jointly latched in the asynchronous successive approximation digital logic circuit. The capacitive digital-to-analog converter is used to execute the step of connecting the lower plate of the MSB capacitor on the higher-level side to GND according to the logical value of the first comparison and connecting the lower plate of the MSB capacitor on the lower-level side to VREF according to the result after the second comparison, so as to raise the level of the originally lower-level end and lower the level of the originally higher-level end. After the comparator triggers four comparisons, the asynchronous successive approximation digital logic circuit is used to merge the results after each comparison and output them to obtain the 4-bit quantized result.

3. The six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient according to claim 1, wherein During the sampling completion and entry into the charge redistribution process of the successive approximation quantizer, the upper and lower plates of half of the capacitors in the capacitive digital-to-analog converter are successively connected to V REF or GND according to the result after comparison by the comparator, and the lower plates of the other half of the capacitors in the capacitive digital-to-analog converter are always connected to the common-mode voltage V CM , so as to be equivalent to multiplying by a coefficient of 0.5 on V REF , thereby reducing the voltage change amount of each successive approximation by half.

4. A six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient according to claim 1, characterized in that The digital code obtained by each comparison of the comparator is stored by a dynamic logic chain; the dynamic logic chain is used to store the digital code obtained by the current comparison, reset the comparator, and trigger the next comparison clock until all comparisons are completed.

5. A six-input 4-bit successive approximation quantizer with an embedded feedforward coefficient, characterized in that, The successive approximation quantizer is implemented by a fully differential circuit.

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