Printed circuit board, preparation method and electronic equipment

Abstract

The invention discloses a printed circuit board, a preparation method and electronic equipment. The printed circuit board includes: a via hole; a bonding pad structure is arranged on the inner wall of the via hole; an electrical component; and the bonding pad structure is arranged in the via hole, and a pin of the electrical component is electrically connected with the bonding pad structure through solder. Electric components mounted on the surface layer traditionally are embedded into the via holes, the surface layer space of the circuit board is released, and more chips or signal lines can be arranged on the surface layer.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and particularly to a printed circuit board, a preparation method, and an electronic device. Background Art

[0002] With the continuous development of electronic technology, the signal rate has been continuously increasing, the functions of server boards have become more and more complex, the number of components on the board has been growing, and the layout and wiring design of printed circuit boards has been developing in the direction of high density. The rate of high-speed signals has been doubling continuously, and the requirements for signal integrity have become more stringent. As the power supply voltage of chips becomes lower and lower, the requirements for decoupling and filtering of power supply signals have become higher and higher. Therefore, the number of components such as filter capacitors and resistors provided on printed circuit boards has been increasing.

[0003] Currently, for some signal transmission links, electrical components need to be provided in the link for filtering or impedance matching, etc. In some cases, the chips provided on the printed circuit board also need to be connected to the electrical components. And the electrical components are generally provided on the surface layer of the printed circuit board, which occupies a large amount of layout and wiring space of the printed circuit board and is not conducive to the development direction of high density and miniaturization of the printed circuit board. Summary of the Invention

[0004] The present application provides a printed circuit board, a preparation method, and an electronic device to solve the problem that in the traditional solution, electrical components occupy a large amount of layout and wiring space of the printed circuit board and are not conducive to the high-density and miniaturization development of the printed circuit board.

[0005] In a first aspect, the present application provides a printed circuit board, including: Via holes; a pad structure is provided on the inner wall of the via holes; Electrical components; arranged in the via holes, and the pins of the electrical components are electrically connected to the pad structure through solder.

[0006] In a second aspect, the present application further provides a preparation method for a printed circuit board, including: Forming via holes on the printed circuit board; Forming a pad structure on the inner wall of the via holes; Forming solder on the pad structure, arranging electrical components in the via holes, and electrically connecting the pins of the electrical components to the pad structure through the solder.

[0007] In a third aspect, the present application further provides an electronic device, including the printed circuit board in the first aspect.

[0008] The printed circuit board provided by this application includes vias, and pad structures are arranged on the inner walls of the vias. Electrical components are vertically embedded into the vias, and the pins of the electrical components are soldered to the inner wall pads through solder. By embedding the electrical components with traditional surface mounting into the vias, the surface space of the circuit board is released, enabling more chips or signal lines to be laid out on the surface. Description of the Drawings

[0009] In order to more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 Structural schematic diagram of a printed circuit board provided by an embodiment of this application; Figure 2 Structural schematic diagram of another printed circuit board provided by an embodiment of this application; Figure 3 Structural schematic diagram of the pad etching on the inner wall of the via of a printed circuit board provided by an embodiment of this application; Figure 4 Structural schematic diagram of the pad etching on the inner wall of the via of a printed circuit board provided by an embodiment of this application; Figure 5 Structural schematic diagram of the pad etching on the inner wall of the via of another printed circuit board provided by an embodiment of this application; Figure 6 Flow schematic diagram of a preparation method of a printed circuit board provided by an embodiment of this application; Figure 7 Optical path diagram of exposing a photosensitive layer provided by an embodiment of this application; Figure 8 Specific example flow chart of a preparation method of a printed circuit board provided by an embodiment of this application; Figure 9 Specific example flow chart of another preparation method of a printed circuit board provided by an embodiment of this application; Figure 10 Structural schematic diagram of the structure after soldering a capacitor in the via provided by an embodiment of this application. Detailed Description of the Embodiments

[0011] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0012] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0013] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further elaborates on this application in conjunction with the accompanying drawings and specific implementation manners.

[0014] With the continuous development of electronic technology, the signal rate has been continuously increasing, the functions of server boards have become more complex, the number of components on the board has been growing, and the layout and routing design of printed circuit boards has been developing in the direction of high density. The rate of high-speed signals has been doubling continuously, and the requirements for signal integrity have become more stringent. As the power supply voltage of the chip becomes lower and lower, the requirements for decoupling and filtering of power supply signals are also getting higher and higher. Therefore, the number of components such as filter capacitors and resistors arranged on the printed circuit board has been increasing.

[0015] Currently, for example, a decoupling capacitor needs to be configured in the transmission link of high-speed signals to achieve signal filtering and power supply stability. The decoupling capacitor is usually arranged near the connector or the fan-out area of the gold finger. The specific connection relationship is as follows: The printed circuit board line starts from the connector pin, passes through the decoupling capacitor and is connected to the signal layer-changing via to form a complete signal transmission path. In the high-speed signal transmission link, the decoupling capacitor and the signal layer-changing via, as key impedance discontinuity nodes, are prone to cause signal loss and reflection effects, which have an adverse impact on the integrity of high-speed signals. In addition, in traditional designs, the decoupling capacitor is arranged on the surface layer of the printed circuit board, occupying a large amount of layout space near the connector or the fan-out area of the gold finger, which restricts the high-density integrated design of the printed circuit board.

[0016] In some cases, the chips arranged on the printed circuit board also need to be connected to electrical components. For example, chips are usually arranged on the front side of the printed circuit board, capacitors are arranged on the back side of the printed circuit board corresponding to the chips, and the chip pins are directly electrically connected to the capacitor pads through vias. In this layout method, the capacitors occupy a large amount of layout space on the back side of the printed circuit board, resulting in difficulty in arranging other resistor-capacitor components in the area on the back side of the chips, and it is impossible to closely install a heat dissipation module on the printed circuit board, which restricts the high-density integration and miniaturization design of the printed circuit board.

[0017] In view of the above problems, the embodiment of this application provides a printed circuit board. Figure 1A schematic structural diagram of a printed circuit board provided by an embodiment of the present application is as follows Figure 1 As shown, the printed circuit board provided by the present application includes a via 10 and an electrical component 20.

[0018] A pad structure 11 is provided on the inner wall of the via, and the electrical component 20 is disposed in the via 10. The pins of the electrical component 20 are soldered to the pad structure 11 on the inner wall of the via through solder 12.

[0019] In the embodiment of the present application, the diameter of the via can be designed according to the external dimension of the component. The pad structure can, for example, adopt an electroplating process to form a continuous conductive layer on the hole wall. After the pins are inserted, the solder is melted by reflow soldering to fill the gap between the pins and the pad structure.

[0020] In the embodiment of the present application, the electrical components of the traditional surface mounting are embedded in the via, releasing the surface space of the printed circuit board, so that more chips or signal lines can be arranged on the surface of the printed circuit board. The pins of the electrical components are directly connected to the pad structure on the inner wall of the via, which can also shorten the signal transmission distance, reduce the parasitic inductance, and improve the signal integrity. The embodiment of the present application can adopt the existing via processing and soldering processes without adding new equipment. The pad structure can be realized by conventional electroplating, and the production cost is low.

[0021] For the design of a printed circuit board for high-speed signals in the prior art, the embodiment of the present application provides a printed circuit board with vias, and electrical components are arranged in the vias. By integrating the signal-changing vias and the electrical components, the impedance discontinuity nodes in the high-speed signal link are effectively reduced, and the layout and wiring space of the printed circuit board is significantly reduced.

[0022] For the structure in the prior art where the chips and electrical components are respectively arranged on both sides of the printed circuit board, in the embodiment of the present application, the electrical components are arranged in the vias, so that the electrical components are closer to the chip pins, which can better play a buffering role when the chip voltage fluctuates, thereby maintaining the stability of the chip voltage. It can more effectively filter out the high-frequency noise on the power line, reduce the interference of the power noise on the signal transmission, thereby maintaining the purity of the signal, reducing the distortion of the signal, and ensuring the integrity and accuracy of the power signal.

[0023] In some alternative embodiments, an annular insulating layer is provided on the side wall of the via. Figure 2 A schematic structural diagram of another printed circuit board provided by an embodiment of the present application is as follows Figure 2As shown, a ring-shaped insulating layer 13 is provided on the inner wall of the via 10. The pad structure 11 includes a first electroplated pad 111 and a second electroplated pad 112. The first electroplated pad 111 covers the inner wall of the via above the ring-shaped insulating layer 13. The second electroplated pad 112 covers the inner wall of the via below the ring-shaped insulating layer 13. A ring-shaped insulating layer (the thickness can be set according to actual situations, such as 0.2 mm, formed by epoxy resin dispensing) is provided in the middle of the inner wall of the via, dividing the hole wall into upper and lower regions. After the ring-shaped insulating layer is provided, when forming the pad structure by subsequent electroplating, the electroplated layers above and below the ring-shaped insulating layer can be disconnected. The first electroplated pad 111 is formed above the ring-shaped insulating layer, and the upper first electroplated pad 111 is connected to the top layer signal line. The second electroplated pad 112 is formed above the ring-shaped insulating layer, and the lower second electroplated pad 112 is connected to the bottom layer or inner layer trace.

[0024] The ring-shaped insulating layer electrically isolates the first electroplated pad and the second electroplated pad, avoiding longitudinal coupling of high-frequency signals on the hole wall and preventing signal short circuits caused by the upper and lower ends of the via being connected. The first electroplated pad and the second electroplated pad can be connected to different layer circuits to achieve three-dimensional signal routing. For example, the output signal of the top layer chip is connected to the input end of the capacitor through the upper first electroplated pad, and the output end of the capacitor is directly connected to the inner layer trace through the lower second electroplated pad, shortening the cross-layer interconnection path.

[0025] In some alternative embodiments, the inner wall of the ring-shaped insulating layer can be in interference fit with the electrical component.

[0026] The inner wall of the ring-shaped insulating layer is in interference fit with the outer diameter of the electrical component, and can also form a mechanical support for the electrical component. The interference fit structure pre-positions the electrical component before soldering, prevents displacement during reflow soldering, improves the soldering yield, and at the same time reduces the dependence on additional fixing glue and simplifies the process flow.

[0027] The inner wall of the annular insulating layer forms an interference fit structure with the outer contour of the electrical component. For example, the inner diameter of the annular insulating layer is 0.005 - 0.01 mm smaller than the outer diameter of the electrical component, and the tight fit is achieved by the radial pressure generated by the elastic deformation of the material. This design breaks through the traditional planar layout thinking of surface mounting, and innovatively introduces the interference fit principle in mechanical engineering into the three-dimensional integrated structure of the printed circuit board. Through precise dimension control of the insulating layer, a composite support structure with both electrical isolation and mechanical fixation functions is constructed inside the via. The interference fit structure forms a pre-positioning lock for the electrical component before soldering, and can achieve double fixation of the component in the axial and radial directions without additional auxiliary positioning structures (such as positioning glue or fixtures), solving the problem of component offset caused by gravity or soldering thermal stress in traditional via mounting. Verified by the reflow soldering process, this structure significantly improves the soldering yield and reduces defects such as solder joint voids and short circuits caused by component displacement. At the same time, eliminating the dependence on fixing glue not only simplifies the process flow such as glue application and curing, but also avoids the dielectric loss impact of the adhesive on high-frequency signal transmission, ensuring signal integrity while improving production efficiency.

[0028] This design realizes composite value through the deep integration of mechanical structure and electrical function: the annular insulating layer serves both as an electrical isolation medium between the upper and lower pads and as a mechanical support carrier for the components, constructing a multi-functional composite structure in the narrow space of the thickness.

[0029] In some alternative embodiments, the pad structure includes an etched pad and an etched signal line. The etched pad is connected to the etched signal line. In the embodiments of the present application, the pad structure can be formed by etching, that is, the pad structure is formed on the conductive layer inside the via through the etching process. The pad structure includes an etched pad and an etched signal line. The etched pad is connected to the etched signal line. The etched pad and the etched signal line adopt the same exposure and development process as the outer layer circuit, providing finer line width accuracy, etched pad size, etched pad pitch, and signal line pitch.

[0030] The pad structure is formed by the etching process, breaking through the functional limitation that the traditional via only serves as a conductive channel, and creatively extending the precise etching technology of the outer layer circuit of the printed circuit board to the three-dimensional space of the inner wall of the via. Specifically, by directly implementing the exposure, development, and etching processes on the conductive layer of the inner wall of the via (completely collinear with the outer layer circuit process), an integrated structure of the etched pad and the etched signal line is formed synchronously, realizing circuit feature processing with micron-level accuracy.

[0031] The core innovation of this design is to break the functional positioning of traditional vias as conductive through-holes, and use mature PCB etching technology to build a fine circuit structure on the inner wall of the via: the etched pads are used as welding carriers for electrical components, directly connected to the etched signal lines, forming a low-impedance transmission path from the inner wall of the via to the surface of the circuit board. Compared with the traditional electroplating pad process, this solution improves the circuit feature accuracy of the inner wall of the via to the same level as the outer layer through a standardized exposure and development process.

[0032] In some optional embodiments, the etched pad includes a positive differential signal pad and a negative differential signal pad. The electrical component includes a first electrical component and a second electrical component. The pin of the first electrical component is electrically connected to the positive differential signal pad through solder. The pin of the second electrical component is electrically connected to the negative differential signal pad through solder.

[0033] The inner wall of the via hole of the printed circuit board of this embodiment is formed into a positive differential signal pad and a negative differential signal pad through an etching process. The etching process can strictly control the distance between the two to meet the characteristic impedance requirements of high-speed differential signal transmission. The pins of the first electrical component (such as a filter capacitor) are connected to the positive differential signal pad by solder through a reflow process; the pins of the second electrical component (which can also be a filter capacitor) are connected to the negative differential signal pad in the same welding method. At the same time, the positive differential signal pad is connected to the positive differential signal line of the outer layer, and the negative differential signal pad is connected to the negative differential signal line, forming a complete differential signal transmission link.

[0034] Differential signal transmission relies on the potential difference between two signal lines to transmit information. By strictly controlling the distance between the two through the etching process, the differential signal can maintain good symmetry during transmission and effectively suppress the interference of common-mode noise. Due to the precise connection between the positive differential signal pad and the negative differential signal pad and the corresponding electrical components, the two differential signal lines are subject to approximately the same external interference. When processed by the differential amplifier at the receiving end, the common-mode interference signal is offset, leaving only the effective differential signal.

[0035] Integrating the positive differential signal pads, negative differential signal pads and corresponding electrical components in the vias greatly saves layout space compared to the traditional way of distributing them on the surface of the printed circuit board. Under the same area, the structure of this embodiment enables the printed circuit board to carry more high-speed signal transmission links, which is particularly suitable for complex electronic devices such as server boards that have extremely high requirements for signal transmission density, and has effectively promoted the development of printed circuit boards towards high-density integration.

[0036] The formation of the etched pad adopts the same exposure, development, and etching processes as the outer layer circuit of the printed circuit board. Only by adding exposure technology in the inner wall processing link of the via can uniform imaging be achieved, and the line width accuracy can be controlled within the required size. This enables this structure to be well integrated into the existing printed circuit board production and manufacturing system without the need for additional complex process equipment and processes, reduces the production technology threshold and manufacturing cost, and has good process compatibility and generalizability.

[0037] In some alternative embodiments, Figure 3 FIG. is a schematic structural diagram of an etched pad on the inner wall of a via of a printed circuit board provided by an embodiment of the present application. As Figure 3 shown, the distance between the positive differential signal pads (including D and F) and the negative differential signal pads (including E and G) is a preset distance S. Among them, the positive differential signal pads include a positive differential signal input pad D and a positive differential signal output pad F, and the negative differential signal pads include a positive differential signal input pad E and a negative differential signal output pad G. The etched signal lines include positive differential signal lines (including L1 and L2) and negative differential signal lines (including L3 and L4). The positive differential signal lines are electrically connected to the positive differential signal pads. The negative differential signal lines are electrically connected to the negative differential signal pads. The line widths of the positive differential signal lines and the negative differential signal lines are preset line widths W.

[0038] Figure 3 Exemplarily, the preset distance S is set to 8 mil, and the preset line width W is set to 8 mil. In the printed circuit board of this embodiment, the distance between the pads D and F for positive differential signal transmission is set to 0.2 mm; the distance between the pads E and G for negative differential signal lines is also 0.2 mm. The distance S between the positive differential signal pads (including D and F) and the negative differential signal pads (including E and G) is 8 mil, and this distance meets the minimum distance requirement for welding the electrical components arranged in the via. The line widths W of the positive differential signal lines and the negative differential signal lines can be accurately calculated and determined through impedance calculation software according to the target impedance value in combination with the 8 mil differential line distance condition. The cooperation between this line width value and the distance parameter can effectively ensure the characteristic impedance matching during the differential signal transmission process and meet the high-speed signal transmission requirements.

[0039] During the high-speed differential signal transmission process, the consistency of the characteristic impedance is crucial. Precise pad distance and line width design can control the transmission impedance of the differential signal, effectively avoid signal reflection and loss caused by impedance discontinuity, and ensure the accuracy and stability of data transmission.

[0040] In the printed circuit board according to the embodiment of the present application, a positive differential signal pad and a negative differential signal pad are formed on the inner wall of the via by an etching process, and the distance between the two is strictly set to a preset distance. The etched signal lines include a positive differential signal line and a negative differential signal line, wherein the positive differential signal line is electrically connected to the positive differential signal pad, and the negative differential signal line is connected to the negative differential signal pad. The line widths of the positive differential signal line and the negative differential signal line can also be precisely controlled. The line width values are precisely calculated and verified by simulation to ensure that the characteristic impedance is stable within the required range. The strictly controlled pad distance and line width make the external interference received by the positive and negative differential signal lines approximately the same during transmission. When the signal is transmitted to the receiving end, the signals of the two signal lines are processed by a differential amplifier, and the common-mode noise will be effectively canceled, and only the differential-mode signal carrying the valid information is retained.

[0041] In some alternative embodiments, multiple sets of electrical components can also be arranged in the via. The pad structure includes multiple sets of etched pads. Each set of etched pads is electrically connected to each set of electrical components in one-to-one correspondence.

[0042] Figure 4 It is a schematic structural diagram of an etched pad on the inner wall of a via of a printed circuit board provided by an embodiment of the present application. As Figure 4 shown, the embodiment of the present application can set multiple signal line transmission links in one via. For example, two pairs of differential signals are set in one via. Figure 4 It is a top view. Refer to Figure 4 , and two sets of electrical components are exemplarily arranged in the via 10, namely the first set of electrical components 21 and the second set of electrical components 22. The pad structure includes two sets of etched pads, namely the first set of etched pads 113 and the second set of etched pads 114. Each set of electrical components includes two electrical components. The first set of electrical components 21 includes electrical components 211 and 212. The second set of electrical components 22 includes electrical components 221 and 222. Each set of etched pads includes, for example, a positive differential signal pad and a negative differential signal pad. The first set of etched pads 113 includes a positive differential signal pad DP1 and a negative differential signal pad DN1, and the second set of etched pads 114 includes a positive differential signal pad DP2 and a negative differential signal pad DN2. Each set of etched pads is electrically connected to each set of electrical components in one-to-one correspondence. The positive differential signal pad DP1 is electrically connected to the electrical component 211, the negative differential signal pad DN1 is electrically connected to the electrical component 212, the positive differential signal pad DP2 is electrically connected to the electrical component 221, and the negative differential signal pad DN2 is electrically connected to the electrical component 222.

[0043] In this embodiment, by arranging multiple groups of etched pads on the inner wall of the via and correspondingly connecting multiple groups of electrical components, a three-dimensional integrated architecture of "one via with multiple components" is constructed, breaking through the limitation of the single function of traditional vias. Taking two groups of differential signals as an example, compared with arranging the etched pads and electrical components corresponding to one group of differential signals in each of the 2 independent vias, only 1 via is required in the embodiment of the present application, significantly improving the space utilization rate.

[0044] Furthermore, multiple groups of etched pads can also support the hybrid integration of different types of components (such as capacitors, resistors, inductors), and a "filtering - matching - coupling" functional unit is constructed within a single via.

[0045] Multiple groups of etched pads can be realized by adjusting the mask pattern (such as expanding the mask of a single group of etched pads into an annular array), which is completely collinear with the exposure, development, and etching processes of the outer layer circuit, without the need to add new equipment or materials.

[0046] In some alternative embodiments, the etched pads arranged oppositely on the inner wall of the via are staggered.

[0047] As Figure 4 shown, two groups of etched pads are circumferentially distributed on the inner wall of the via, and the etched pads arranged oppositely are staggered. The positive differential signal pad DP2 corresponds to the middle position between the positive differential signal pad DP1 and the negative differential signal pad DN1, which can minimize the mutual interference between the two pairs of differential signals to the greatest extent and enhance the stability and integrity of the signals.

[0048] In some alternative embodiments, a ground signal line is also arranged on the inner wall of the via.

[0049] Figure 5 As shown in the structural schematic diagram of the etched pads on the inner wall of the via of another printed circuit board provided by the embodiment of the present application, as Figure 5 shown, a ground signal line GND is arranged on the inner wall of the via 10, and for example, it can be connected to the ground plane of the inner layer of the printed circuit board through a blind via. The ground signal line GND can be arranged around the pad structure, for example, wrapping the pad structure corresponding to the differential signal, providing good shielding to prevent the differential signal from being interfered by other signals, which is beneficial to improving the signal integrity, reducing problems such as signal jitter, noise, and crosstalk, and improving the signal quality.

[0050] In the preferred embodiment, the ground signal line structure is innovatively integrated on the inner wall of the via, breaking through the functional limitation of the traditional via only as a signal transmission channel, and constructing a three-dimensional electromagnetic shielding system. A continuously surrounding ground signal line is arranged on the inner wall of the via to form a shielding ring that wraps the pad structure, providing electromagnetic isolation protection for the differential signal pads in space.

[0051] In the embodiments of the present application, the shielding function of the ground plane is extended to the inner wall of the via. By etching a circumferential ground signal line on the hole wall, a "three-dimensional ground network" is formed with the inner-layer ground plane, solving the industry problem of the lack of effective shielding when traditional vias are used as signal layer-changing nodes. The annular layout of the ground signal line forms a Faraday cage-like effect, physically cutting off the electromagnetic coupling path between the external interference source and the internal signal pad. Furthermore, the etching process of the ground signal line is formed synchronously with the pad structure. Without adding extra manufacturing steps, only by adding an annular ground pattern in the mask design can the integration of the shielding function be achieved.

[0052] In some alternative embodiments, as Figure 4 shown, if multiple groups of etched pads are included in the via, the ground signal line GND can be arranged between adjacent etched pads to avoid mutual interference between adjacent differential signals.

[0053] In the embodiments of the present application, according to the layout requirements of multiple groups of etched pads in the via, the ground signal line GND is arranged in the circumferential gap between adjacent etched pads to form a three-dimensional isolation structure of "pad-ground-pad". This design breaks through the traditional planar layout concept that the ground signal line only exists on the surface layer or the inner layer of the printed circuit board. By constructing a distributed ground barrier in the three-dimensional space of the inner wall of the via, physical isolation and electromagnetic shielding of adjacent differential signal pairs are achieved.

[0054] The ground signal line utilizes the inherent gap between adjacent pads without occupying extra planar layout space, keeping the pad integration density in the via unchanged. At the same time, the annular layout of the ground signal line forms a coplanar waveguide-like structure, providing a low-loss return path for high-frequency signals and significantly reducing the impedance compared with the traditional surface-layer ground trace.

[0055] In some alternative embodiments, the electrical components include filter capacitors and / or impedance matching resistors.

[0056] When the electrical component is a filter capacitor, the embodiments of the present application provide a printed circuit board with vias, and the filter capacitor is arranged in the vias. By integrating the signal layer-changing vias with the electrical components, for the printed circuit board design of high-speed signals in the prior art, the impedance discontinuous nodes in the high-speed signal link can be effectively reduced, and the layout and wiring space of the printed circuit board can be significantly reduced.

[0057] Compared with the prior art in which the chip is disposed on the front side of the printed circuit board and the filter capacitor is disposed on the back side of the printed circuit board, the present application forms a "near-source filtering" architecture by embedding the filter capacitor into the pad structure on the inner wall of the via: the filter capacitor is directly connected to the chip power pin through the pad structure on the inner wall of the via. The filter capacitor is disposed closer to the chip pin, and can better buffer when the chip voltage fluctuates, thereby maintaining the stability of the chip voltage. It can more effectively filter out high-frequency noise on the power line, reduce the interference of power noise on signal transmission, thereby maintaining the purity of the signal, reducing signal distortion, and ensuring the integrity and accuracy of the power signal.

[0058] When the electrical component is an impedance matching resistor, the impedance matching resistor is integrated in the via, and the area of the printed circuit board can be saved compared with the traditional surface mount solution. After the impedance matching resistor is buried in the via, the surface mount process is reduced, the investment in the chip mounter is saved, and at the same time the cost of the resistor itself is reduced (the buried resistor can adopt a smaller package). The impedance matching resistor is close to the signal source or the load end, and the length of the signal line can also be shortened.

[0059] In some alternative embodiments, an insulating filling material is further disposed in the via.

[0060] After the component soldering is completed, the remaining space of the via can be filled with an insulating filling material (such as resin), for example, the air bubbles are removed by a vacuum potting process, and the surface is ground flat to be flush with the surface of the printed circuit board after curing, so as to ensure the stability and reliability of the structure and prevent the influence of subsequent processing processes on the electrical components in the via.

[0061] Based on the same inventive concept, the present application further provides a method for manufacturing a printed circuit board. Figure 6 As shown in Figure 6 is a schematic flow chart of a method for manufacturing a printed circuit board provided by an embodiment of the present application. The method for manufacturing a printed circuit board includes: S101, forming a via on the printed circuit board.

[0062] For example, a laser drilling technology can be used to process a via at a specified position on the printed circuit board, and the aperture is designed according to the outer dimension of the electrical component (for example, a 0201 package capacitor corresponds to a via with a diameter of 0.4 mm). After drilling, the hole wall can be roughened, and the residual impurities on the hole wall can be removed by chemical cleaning to ensure the bonding force between the subsequent conductive layer and the hole wall.

[0063] S102, forming a pad structure on the inner wall of the via.

[0064] The embodiment of the present application does not limit the specific process for forming the pad structure on the inner wall of the via, such as electroplating, exposure and etching processes.

[0065] S103. Form solder on the pad structure, place the electrical component in the via, and electrically connect the pins of the electrical component to the pad structure through the solder.

[0066] Print or spray solder paste or other solder on the surface of the pad structure. The thickness of the solder paste can be controlled according to requirements such as the via diameter and the size of the electrical component. The solder covers the effective welding area of the pad structure.

[0067] Vertically insert the electrical component (such as a filter capacitor) into the via (which can be assembled by a manipulator) to accurately align the pins with the pads. Place the printed circuit board in a reflow soldering furnace and go through the preheating, holding, reflow, and cooling stages. After the solder paste melts, it fills the gap between the pins and the pad structure to form a metallurgical bonded solder joint. Solder paste or other solder serves as a medium to achieve electrical connection and mechanical fixation between the pins and the pads. The reflow soldering process uses heat conduction to uniformly melt the solder to form reliable solder joints.

[0068] In the embodiment of the present application, by embedding the electrical component inside the via, compared with the traditional surface mounting method, it can significantly save planar space, release the surface space for high-density circuit boards, and can layout more chips or signal lines. It is especially suitable for space-sensitive scenarios such as server boards and high-speed interface modules. The pins of the electrical component are directly connected to the pad structure on the inner wall of the via, which can shorten the signal transmission path and significantly reduce parasitic inductance and capacitance.

[0069] For the printed circuit board design of high-speed signals in the prior art, the embodiment of the present application provides a printed circuit board with vias, and electrical components are arranged in the vias. By integrating the signal-changing vias and the electrical components, the impedance discontinuity nodes in the high-speed signal link are effectively reduced, and the layout and wiring space of the printed circuit board are significantly reduced.

[0070] For the structure in the prior art where the chip and the electrical component are respectively arranged on both sides of the printed circuit board, in the embodiment of the present application, the electrical component is arranged in the via, making the electrical component closer to the chip pins. It can better play a buffering role when the chip voltage fluctuates, thereby maintaining the stability of the chip voltage. It can more effectively filter out high-frequency noise on the power line, reduce the interference of power noise on signal transmission, thereby maintaining the purity of the signal, reducing signal distortion, and ensuring the integrity and accuracy of the power signal.

[0071] In some alternative embodiments, the pad structure includes a first electroplated pad and a second electroplated pad. Forming the pad structure on the inner wall of the via includes: Form a ring-shaped insulating layer in the middle area of the inner wall of the via; Electroplate a first electroplated pad on the inner wall of the via above the ring-shaped insulating layer, and form a first electroplated pad on the inner wall of the via below the ring-shaped insulating layer.

[0072] ForFigure 2 For example, a ring-shaped insulating layer 13 is formed in the middle region of the inner wall of the via 10, and then electroplating is performed. Due to the isolation of the ring-shaped insulating layer 13, the first electroplated pad 111 covers the inner wall of the via above the ring-shaped insulating layer 13. The second electroplated pad 112 covers the inner wall of the via below the ring-shaped insulating layer 13.

[0073] In the embodiment of the present application, after drilling a via in the printed circuit board after lamination is completed, resin glue can be dropped at the middle position of the inner wall of the via to form a ring-shaped insulating layer. Then electroplating is performed. Due to the presence of the ring-shaped insulating layer at the middle position of the inner wall of the via, the conductive layer formed by electroplating electroplates on the inner wall of the via above the ring-shaped insulating layer to form the first electroplated pad, and forms the first electroplated pad on the inner wall of the via below the ring-shaped insulating layer. In this way, it is possible to prevent the upper and lower ends of the via from being connected to cause signal short-circuiting. The width of the glue-dropping area can be set to 0.2 mm, for example.

[0074] The ring-shaped insulating layer electrically isolates the first electroplated pad and the second electroplated pad, avoids high-frequency signal longitudinal coupling on the hole wall, and prevents the upper and lower ends of the via from being connected to cause signal short-circuiting. The first electroplated pad and the second electroplated pad can be connected to different layer circuits to achieve three-dimensional signal routing. For example, the signal output by the top-layer chip is connected to the input end of the capacitor through the upper-layer first electroplated pad, and the output end of the capacitor is directly connected to the inner-layer trace through the lower-layer second electroplated pad, shortening the cross-layer interconnection path.

[0075] In some alternative embodiments, forming a ring-shaped insulating layer in the middle region of the inner wall of the via includes: Placing a preset mold in the via, and using the preset mold to drop glue at the middle region of the inner wall of the via to form a ring-shaped insulating layer; the outer contour of the preset mold contacts the inner wall of the ring-shaped insulating layer formed by dropping glue; the outer contour of the preset mold is the same as the outer contour of the electrical component.

[0076] For example, according to the outer contour of the target electrical component, a preset mold can be fabricated by high-precision numerical control machining. The robotic arm is controlled by a vision alignment system to vertically insert the preset mold into the via hole, with the mold axis coinciding with the via hole axis, ensuring a uniform gap is reserved between the outer contour of the mold and the inner wall of the via hole, facilitating subsequent dispensing operations. Immediately after dispensing, ultraviolet exposure curing is performed to rapidly cure the resin glue to form a ring-shaped insulating layer. The preset mold is vertically pulled out upward by the robotic arm. Then electroplating is carried out. Due to the presence of the ring-shaped insulating layer at the middle position of the inner wall of the via hole, the electroplated conductive layer is electroplated on the inner wall of the via hole above the ring-shaped insulating layer to form a first electroplated pad, and a first electroplated pad is formed on the inner wall of the via hole below the ring-shaped insulating layer. The electrical component is vertically inserted into the via hole. The interference fit between the outer diameter of the electrical component and the inner diameter of the ring-shaped insulating layer can achieve gapless pre-positioning, eliminating the need for additional positioning fixtures. The outer contour of the preset mold is consistent with the outer contour of the electrical component, ensuring that the inner diameter of the ring-shaped insulating layer is strictly matched with the outer diameter of the electrical component, forming an interference fit. This design enables the electrical component to be inserted into the via hole without additional adjustment and achieves precise positioning through physical contact, solving the problem of welding displacement caused by dimensional deviations of components in traditional processes.

[0077] In some alternative embodiments, forming a pad structure on the inner wall of the via hole includes: Forming a conductive layer on the inner wall of the via hole; Forming a photosensitive layer on the conductive layer; Exposing and developing the photosensitive layer to form a pad structure pattern; Etching the conductive layer exposed by the pad structure pattern to form a pad structure; Wherein, the pad structure includes an etched pad and an etched signal line; the etched pad is connected to the etched signal line.

[0078] In the embodiment of the present application, through the process scheme of "conductive layer - photosensitive layer - exposure and development - etching", high-precision forming of the pad structure on the inner wall of the via hole is achieved. For example, first, a conductive layer is formed on the inner wall of the via hole, and then a photosensitive layer is formed on the inner wall of the via hole using a vacuum laminator. After exposure, development, and etching, the required pad structure pattern is exposed. Exposure is to align the mask plate with the pad structure pattern with the side wall of the via hole covered with the photosensitive film and then irradiate it with ultraviolet light or other light with a specific wavelength. During the exposure process, the transparent part of the mask plate allows light to pass through and irradiate the photosensitive film, and the irradiated areas will undergo a photochemical reaction, thereby changing the properties of the photosensitive film. Development is to use a developer to remove the photosensitive film in the exposed area after exposure, thereby revealing the pad structure pattern. After development, the copper skin of the non-pad structure pattern is etched, leaving the required pad structure pattern.

[0079] In the embodiments of the present application, a pad structure is formed by means of exposure, development, and etching. The dimensional accuracy of the pads and the accuracy of the line width can be more accurate, and the strict requirements of high-speed differential signals for pad symmetry can be met. Compared with traditional electroplated pads, the edge roughness of etched pads is significantly reduced, which can reduce edge scattering during signal transmission.

[0080] This preparation method can reuse the etching process of the outer layer circuit of the printed circuit board without adding special equipment. At the same time, the etching process has a high degree of automation, good pad structure consistency, and high batch production yield, reducing manual intervention and detection costs. By adjusting the etching parameters (such as line width, pad pitch, conductive layer thickness), different electrical components in different packages can be flexibly adapted to form a standardized and replicable high-density circuit board preparation solution, promoting the integrated innovation of high-speed and miniaturized electronic devices.

[0081] In some alternative embodiments, forming a pad structure pattern by exposing and developing a photosensitive layer includes: Providing exposure light from above the via, and reflecting it to the photosensitive layer on the inner wall of the via by a mirror below the via.

[0082] Figure 7 This is a light path diagram of the exposure of the photosensitive layer provided by the embodiments of the present application. A mirror 30 can be fixed on the bottom surface of the printed circuit board directly below the via. The focus of the mirror coincides with the axis of the via, and the radius of curvature of the mirror surface is optimized according to the depth and diameter of the via. For example, a parallel light source can be used to vertically incident from directly above the via, and the light is reflected by the mirror and converges to the inner wall of the via to form an exposure area. The exposure energy is monitored in real time by a light intensity sensor to ensure that the photosensitive layer is fully exposed. By adjusting the angle of the mirror, uniform illumination of the inner wall of the via can be achieved.

[0083] In the embodiments of the present application, for example, an optical reflection focusing principle is adopted to construct a three-dimensional exposure system. A mirror is set directly below the via. The ultraviolet parallel light source is incident from above the via, and the light is converted into an annular light beam along the tangential direction of the hole wall by the mirror, realizing uniform exposure of the circumferential area of the inner wall of the via. The embodiments of the present application break through the angle limitation of traditional side illumination exposure, utilize the optical focusing characteristics of the mirror, convert the point light source into an annular uniform light field covering the entire hole wall, solve the exposure defect of the inner wall of the deep hole, and can achieve consistent imaging accuracy of the pad structure pattern in the entire area of the inner wall of the via.

[0084] In some alternative embodiments, etching the conductive layer exposed by the formed pad structure pattern to form a pad structure includes: Etching the conductive layer exposed by the formed pad structure pattern to form multiple groups of etched pads of the pad structure; Among them, the etched pads arranged oppositely on the inner wall of the via are staggered.

[0085] In the embodiments of the present application, multiple groups of etched pads can be formed on the inner wall conductive layer of the via, and each group of etched pads is electrically connected to a group of electrical components one by one, so that multiple signal transmission links can be arranged in one via. In addition, in the embodiments of the present application, the etched pads arranged oppositely on the inner wall of the via are staggered, for example Figure 4 There are two groups of etched pads circumferentially distributed on the inner wall of the via, and the etched pads arranged oppositely are staggered. The positive differential signal pad DP2 corresponds to the middle position between the positive differential signal pad DP1 and the negative differential signal pad DN1, which can minimize the mutual interference between the two pairs of differential signals and enhance the stability and integrity of the signals.

[0086] In some alternative embodiments, when exposing and developing the photosensitive layer to form the pad structure pattern, it further includes: exposing and developing the photosensitive layer to form a ground signal line pattern; When etching the conductive layer exposed to form the pad structure pattern to form the pad structure, it further includes: etching the conductive layer exposed by the ground signal line pattern to form a ground signal line.

[0087] In the embodiments of the present application, when exposing and developing the photosensitive layer to form the pad structure pattern, the photosensitive layer is simultaneously exposed and developed to form a ground signal line pattern. Correspondingly, when etching the conductive layer exposed to form the pad structure pattern, the conductive layer exposed by the ground signal line pattern is simultaneously etched to form a ground signal line.

[0088] For example Figure 4 Regarding the setting of the ground signal line. A ground signal line GND is arranged on the inner wall of the via, and for example, it can be connected to the inner layer ground plane of the printed circuit board through a blind via. The ground signal line GND can be arranged around the pad structure, for example, wrapping the pad structure corresponding to the differential signal, providing good shielding, preventing the differential signal from being interfered by other signals, being beneficial to improving the integrity of the signal, reducing problems such as signal jitter, noise, and crosstalk, and improving the signal quality.

[0089] If the via includes multiple groups of etched pads, as Figure 5 shown, the ground signal line GND can be arranged between adjacent etched pads to avoid mutual interference between adjacent differential signals.

[0090] In some alternative embodiments, after forming solder on the pad structure, arranging the electrical components in the via, and electrically connecting the pins of the electrical components to the pad structure through the solder, it further includes: Filling the via with an insulating filling material.

[0091] After the components are soldered, the remaining space of the vias can be filled with an insulating filling material (such as resin). For example, air bubbles can be removed through a vacuum potting process, and the surface is ground flat after curing to be flush with the surface of the printed circuit board, ensuring the stability and reliability of the structure and preventing the subsequent processing flow from affecting the electrical components inside the vias.

[0092] Figure 8 As shown in the specific example flowchart of a method for preparing a printed circuit board provided by an embodiment of the present application, Figure 8 the method for preparing a printed circuit board provided by an embodiment of the present application includes: S201. Form vias on the printed circuit board.

[0093] S202. Form a ring-shaped insulating layer in the middle area of the inner wall of the via.

[0094] S203. Electroplate a first electroplated pad on the inner wall of the via above the ring-shaped insulating layer, and form a first electroplated pad on the inner wall of the via below the ring-shaped insulating layer.

[0095] S204. Form solder on the pad structure, place electrical components in the via, and electrically connect the pins of the electrical components to the pad structure through reflow soldering.

[0096] S205. Fill the via with an insulating filling material.

[0097] First, drill vias with a diameter of, for example, 0.4 mm on the printed circuit board after lamination. Apply a circle of resin glue in the middle area of the inner wall of the via to prevent signal short circuit caused by the upper and lower ends of the via being connected. The width of the glue application area can be, for example, 0.2 mm. After applying the glue, electroplate copper on the inner wall of the via with a thickness of, for example, 0.8 mil, and form a first electroplated pad and a second electroplated pad in the upper and lower areas of the resin glue respectively.

[0098] After electroplating, print solder paste on the first electroplated pad and the second electroplated pad on the inner wall of the via, and the thickness of the printed solder paste can be, for example, 2 mil. Use a manipulator to place electrical components (such as 0201 package capacitors) inside the via after printing the solder paste. After high-temperature reflow soldering, the 0201 package capacitors are completely combined with the via. To ensure the stability and reliability of the structure and prevent the subsequent processing flow from affecting the electrical components inside the via, resin plugging is performed on the via.

[0099] Taking the size of the 0201 package capacitor as 0.6 mm * 0.3 mm * 0.23 mm as an example. Refer to Figure 1Among them, OB = 0.115 mm, AB = 0.15 mm, OA = 0.191 mm, the via hole diameter is 0.4 mm, and the thickness of the electroplated copper is 0.8 mil. In terms of the application scenario, when transmitting a power signal, one pin of the 0201 package capacitor transmits the power signal, and the other pin of the 0201 package capacitor transmits the GND signal. When transmitting a high-speed signal, one pin of the 0201 package capacitor transmits the DP / DN signal, and the other pin C2 of the 0201 package capacitor is the DP_C / DN_C signal.

[0100] In some other embodiments, the 0201 package capacitor can also be replaced with a 0201 package resistor. In this way, when transmitting a low-speed signal, the pin R1 of the 0201 package resistor transmits the LS signal, and the pin R2 of the 0201 package resistor is the LS_R signal.

[0101] Through the collaborative design of "via hole segmented isolation - three-dimensional pad integration - fully enclosed packaging" in this embodiment, the single conductive function of the traditional printed circuit board via hole is broken through, and a three-dimensional interconnected structure integrating electrical isolation, mechanical support, and signal optimization is constructed. A ring-shaped insulating layer with a width of 0.2 mm is formed in the middle area of the inner wall of the via hole, and the via hole axis is divided into upper and lower independent conductive regions, isolating the first electroplated pad from the second electroplated pad to avoid direct coupling of signals between the upper and lower layers. The processes such as forming the ring-shaped insulating layer, electroplating, and insulating filling are all compatible with the existing printed circuit board production line. By adjusting the structural dimensions of the ring-shaped insulating layer and the pads, it can be flexibly adapted to various scenarios such as power filtering, high-speed differential, and radio frequency signals.

[0102] Figure 9 It is a specific example flowchart of another method for manufacturing a printed circuit board provided by the embodiment of the present application. As Figure 9 shown, the method for manufacturing a printed circuit board provided by the embodiment of the present application includes: S301. Form a via hole on the printed circuit board.

[0103] S302. Electroplate copper on the inner walls of the via holes to form a conductive layer.

[0104] S303. Form a photosensitive layer on the conductive layer on the inner wall of the via hole. After exposure and development, etch out the pad structure. The pad structure includes an etched pad and an etched signal line, and the etched pad is connected to the etched signal line.

[0105] S304. Form solder on the pad structure, place an electrical component in the via hole, and electrically connect the pins of the electrical component to the pad structure through reflow soldering.

[0106] S305. Fill the via hole with an insulating filling material.

[0107] In the embodiment of the present application, a conductive layer is formed by electroplating copper on the entire inner wall to establish a complete conductive foundation for the via. Subsequently, the exposure, development, and etching process in S303 can accurately form a pad structure on the conductive layer to achieve a high-precision circuit layout. The structure size, shape, and signal line routing can also be flexibly defined according to design requirements to adapt to high-frequency and high-speed signal transmission scenarios. Integrating the pad and the signal line directly on the inner wall of the via upgrades the via from a single "conductive channel" to a "signal transmission node", reducing surface wiring crossovers and improving the wiring density of the printed circuit board, especially suitable for high-density interconnect boards or system-in-package scenarios.

[0108] In the embodiment of the present application, the pattern is transferred to the photosensitive layer on the inner wall of the via through optical imaging by the exposure and development process. Compared with the traditional silk screen or electroplating filling hole process, it can achieve micron-level line width and line pitch, solve the problem of fine pattern formation on the inner walls of deep holes and small-diameter holes, and provide a process basis for the embedded installation of miniature components.

[0109] In the embodiment of the present application, the via is filled with an insulating material (such as epoxy resin) through step S305 to achieve mechanical reinforcement, eliminate the internal cavity of the via, and prevent the component pins from being displaced or broken due to vibration. The insulating material can also isolate pollutants such as moisture and dust, prevent oxidation and corrosion of the pads and pins, extend the service life of the printed circuit board, and the surface smoothing process makes the via flush with the surface of the printed circuit board, avoiding interference of the protruding structure on the subsequent chip mounting process and improving the processing compatibility.

[0110] The embodiment of the present application is applicable to the design where the high-speed signal is a differential line. The two signal lines DP and DN need to maintain a certain coupling distance. Therefore, when designing the capacitance in the via, a pair of differential line holes can be used as a unit. First, a layer-changing via is drilled, and the size of the via is, for example, an ellipse with a length of 60 mil and a width of 30 mil. Copper with a thickness of 1 mil is electroplated on the inner wall of the via.

[0111] In order to etch the pad structure on the inner wall of the via more precisely, a photosensitive layer is first covered on the inner wall of the via. After exposure, development, and etching, the required pad structure is exposed. Exposure is to align the mask plate with the circuit pattern with the inner wall of the via covered with the photosensitive layer and then irradiate it with ultraviolet light or other light with a specific wavelength. During the exposure process, the transparent part on the mask plate allows light to pass through and irradiate the photosensitive layer, and the irradiated areas will undergo a photochemical reaction, thus changing the properties of the photosensitive layer. During exposure, there is a mirror at the bottom of the via, and the light with a specific wavelength is irradiated on the inner wall of the via by using the reflection of the light. By adjusting the angle of the mirror, uniform irradiation of the inner wall of the via by the light can be achieved. Development is to use a developer to remove the photosensitive layer in the exposed area after exposure, thus revealing the pad structure pattern. After development, the copper in the non-pad structure pattern is etched, leaving the required pad structure.

[0112] Then, solder paste is printed on the pad structure with a thickness of 2 mil. After assembling the capacitor and performing high-temperature reflow soldering, the capacitor is connected to the circuits at both ends of the via. The structural diagram after soldering the capacitor in the via is as shown in Figure 10 Figure []. The pins of the capacitor are connected to the pads etched on the sidewall. The distance between the DP signal and the DN signal always remains S, which maximally ensures the coupling of differential signal lines and the continuity of impedance, facilitating the improvement of the integrity of high-speed signals. After the steps of assembling the capacitor are completed, the via groove is filled with resin, which can prevent signal problems caused by the deposition of impurities inside the via during the later operation of the printed circuit board and enhance the reliability of the board.

[0113] The schematic diagram of the inner wall of the etched via groove is as shown in Figure 3 Figure []. D, E, F, and G represent the pads of the TX coupling capacitor, with a size of 0.3 * 0.2 mm, that is, MP = NQ = 0.3 mm and MN = PQ = 0.2 mm. D and F are the capacitor pads for the DP signal, and the distance between D and F is 0.2 mm; E and G are the capacitor pads for the DN signal, and the distance between E and G is 0.2 mm. The distance S between the DP signal capacitor and the DN signal capacitor is 8 mil, which is the minimum distance that a 0201 device can be soldered. The width W of the DP and DN signal lines is the line width value calculated by impedance calculation software based on the target impedance value and the differential line spacing of 8 mil.

[0114] Through the improvement of the internal structure of the via in this application, the integrated setting of electrical components such as filter capacitors and signal-changing vias is realized, effectively reducing the layout and wiring space of the printed circuit board and significantly improving the circuit integration. This design not only helps to reduce the circuit board area and production cost, but also improves the circuit reliability and stability through the following advantages, promoting the development of printed circuit boards towards high density and miniaturization: The power filter capacitor is arranged close to the chip pins through the pad structure on the inner wall of the via. When the power supply voltage fluctuates, it can achieve a more efficient buffering response, effectively suppressing voltage ripples and maintaining the stability of the power supply voltage. At the same time, the shortened signal path enables the capacitor to more accurately filter out high-frequency noise on the power line, reducing the crosstalk interference of power noise on signal transmission, ensuring the integrity and accuracy of the power signal, and providing a clean power supply environment for the chip.

[0115] For high-speed differential signal links, the integrated design of decoupling capacitors and signal-changing vias can significantly reduce the impedance discontinuity nodes on the link. The fine circuit layout on the sidewall of the via (such as differential signal pads with preset spacing and etched signal lines with controlled line width) realizes precise impedance matching, effectively reducing signal reflection and loss.

[0116] The preparation process of this application is highly compatible with existing printed circuit board production lines. Through standardized processes such as conductive layer deposition, photosensitive layer exposure, development and etching on the inner wall of the via, the integration of the sidewall pad structure and electrical components can be achieved. No special equipment is required, the processing cost is controllable, and the process flow is stable. It has high reproducibility and engineering promotion value, providing a practical technical path for high-density board design and is an important innovation in printed circuit board integration technology.

[0117] The above technical solution achieves an excellent balance between space efficiency, signal integrity, reliability and manufacturing cost through the organic combination of structural innovation and process optimization, laying a key technical foundation for the design of printed circuit boards for the next generation of high-performance electronic devices.

[0118] Based on the same inventive concept, the present application also provides an electronic device, including the printed circuit board in any of the above embodiments.

[0119] Since the principle of solving the problem by the electronic device is similar to that of the aforementioned printed circuit board, the embodiment of the electronic device can refer to the embodiment of the printed circuit board, and the repeated parts will not be repeated.

[0120] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0121] Professionals may further appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0122] The storage components provided by the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A printed circuit board, characterized in that, Comprising: Via holes; a pad structure is provided on the inner wall of the via holes; Electrical components; Disposed within the via holes, and the pins of the electrical components are electrically connected to the pad structure through solder.

2. The printed circuit board according to claim 1, wherein A ring-shaped insulating layer is provided on the inner wall of the via holes; the pad structure includes a first electroplated pad and a second electroplated pad; the first electroplated pad covers the inner wall of the via holes above the ring-shaped insulating layer; the second electroplated pad covers the inner wall of the via holes below the ring-shaped insulating layer.

3. The printed circuit board according to claim 2, characterized in that, The inner wall of the ring-shaped insulating layer is in interference fit with the electrical components.

4. The printed circuit board according to claim 1, wherein The pad structure includes etched pads and etched signal lines; the etched pads are connected to the etched signal lines.

5. The printed circuit board according to claim 4, characterized in that, The etched pads include positive differential signal pads and negative differential signal pads; The electrical components include a first electrical component and a second electrical component; the pins of the first electrical component are electrically connected to the positive differential signal pads through solder; the pins of the second electrical component are electrically connected to the negative differential signal pads through solder.

6. The printed circuit board according to claim 5, wherein The distance between the positive differential signal pads and the negative differential signal pads is a preset distance; the etched signal lines include positive differential signal lines and negative differential signal lines; the positive differential signal lines are electrically connected to the positive differential signal pads; the negative differential signal lines are electrically connected to the negative differential signal pads; The line widths of the positive differential signal lines and the negative differential signal lines are preset line widths.

7. The printed circuit board according to claim 4, wherein, Multiple groups of electrical components are provided within the via holes; the pad structure includes multiple groups of the etched pads; each group of the etched pads is electrically connected to each group of the electrical components in one-to-one correspondence.

8. The printed circuit board according to claim 7, characterized in that, The etched pads disposed oppositely on the inner wall of the via holes are arranged staggeredly.

9. The printed circuit board according to claim 4, wherein, A ground signal line is further provided on the inner wall of the via holes.

10. The printed circuit board according to any one of claims 1-9, characterized in that, The electrical components include filter capacitors and / or impedance matching resistors.

11. The printed circuit board according to any one of claims 1-9, characterized in that, An insulating filling material is further provided within the via holes.

12. A method for preparing a printed circuit board, characterized in that, Comprising: Forming via holes on a printed circuit board; Forming a pad structure on the inner wall of the via holes; Forming solder on the pad structure, disposing electrical components within the via holes, and electrically connecting the pins of the electrical components to the pad structure through the solder.

13. The method for preparing a printed circuit board according to claim 12, wherein The pad structure includes a first electroplated pad and a second electroplated pad; the forming of the pad structure on the inner wall of the via holes includes: Forming a ring-shaped insulating layer in the middle region of the inner wall of the via holes; Electroplating a first electroplated pad on the inner wall of the via holes above the ring-shaped insulating layer, and forming a first electroplated pad on the inner wall of the via holes below the ring-shaped insulating layer.

14. The method for preparing a printed circuit board according to claim 13, wherein, The forming of the ring-shaped insulating layer in the middle region of the inner wall of the via holes includes: Placing a preset mold within the via holes, and dispensing glue in the middle region of the inner wall of the via holes using the preset mold to form a ring-shaped insulating layer; the outer contour of the preset mold contacts the inner wall of the ring-shaped insulating layer formed by dispensing glue; the outer contour of the preset mold is the same as the outer contour of the electrical components.

15. The method for preparing a printed circuit board according to claim 12, wherein The forming of the pad structure on the inner wall of the via holes includes: Forming a conductive layer on the inner wall of the via holes; Forming a photosensitive layer on the conductive layer; Expose and develop the photosensitive layer to form a pad structure pattern; Etch the conductive layer exposed by the pad structure pattern to form the pad structure; Wherein, the pad structure includes an etched pad and an etched signal line; the etched pad is connected to the etched signal line.

16. The method for preparing a printed circuit board according to claim 15, wherein, The exposing and developing the photosensitive layer to form a pad structure pattern includes: Providing exposure light from above the via, and reflecting it to the photosensitive layer on the inner wall of the via through a mirror below the via.

17. The method for preparing a printed circuit board according to claim 15, wherein The etching to form the pad structure by etching the conductive layer exposed by the pad structure pattern includes: Etching the conductive layer exposed by the pad structure pattern to form multiple groups of the etched pads of the pad structure; Wherein, the etched pads arranged oppositely on the inner wall of the via are staggered.

18. The method for preparing a printed circuit board according to claim 15, wherein When exposing and developing the photosensitive layer to form a pad structure pattern, it further includes: exposing and developing the photosensitive layer to form a ground signal line pattern; When etching the conductive layer exposed by the pad structure pattern to form the pad structure, it further includes: etching the conductive layer exposed by the ground signal line pattern to form a ground signal line.

19. The manufacturing method of a printed circuit board according to any one of claims 12-18, characterized in that, After forming solder on the pad structure, arranging an electrical component in the via, and electrically connecting the pins of the electrical component to the pad structure through the solder, it further includes: Filling the via with an insulating filling material.

20. An electronic device, characterized in that, Including a printed circuit board according to any one of claims 1-11.

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