High-capacity high-bandwidth non-volatile memory device

Abstract

A high capacity, high bandwidth non-volatile memory device includes a plurality of vertically stacked semiconductor dies. Each semiconductor die includes one or more non-volatile memory structures. Through silicon vias (TSVs) are arranged in a pattern on each semiconductor die and are used to route signal lines that directly and independently connect one or more non-volatile memory structures on one or more semiconductor dies to a controller die of the high capacity, high bandwidth non-volatile memory device. Because signal lines and TSVs are used to connect each non-volatile memory structure directly to the controller die, the bandwidth capacity of the high capacity, high bandwidth non-volatile memory device is improved compared to the current non-volatile memory device.

Description

Background Art

[0001] Three-dimensional (3D) NAND memory devices are commonly used in various data storage device applications, including memory cards, USB drives, and solid state drives (SSDs). 3D NAND memory devices are preferred for these data storage applications due to their non-volatile nature, large storage capacity, and low cost. However, compared to other memory device technologies such as static random access memory (SRAM) devices or dynamic random access memory (DRAM) devices, 3D NAND memory devices have lower bandwidth and higher access time. Therefore, and despite being significantly more costly and having lower storage capabilities compared to 3D NAND memory devices, SRAM memory devices and DRAM memory devices are commonly used in high-speed applications.

[0002] Therefore, it would be advantageous to increase the bandwidth capacity of 3D NAND memory devices without sacrificing the storage capacity of the 3D NAND memory devices. This would enable 3D NAND memory devices to be used in high-speed applications. Summary of the Invention

[0003] This application describes a high-capacity, high-bandwidth non-volatile memory device. The high-capacity, high-bandwidth non-volatile memory device includes a plurality of vertically stacked semiconductor dies. In one example, the vertically stacked semiconductor dies are 3D NAND memory dies.

[0004] Each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device has one or more non-volatile storage structures. In one example, the non-volatile storage structure is a 3D NAND plane, and each non-volatile storage structure includes a plurality of memory cells. Additionally, each non-volatile storage structure can be accessed independently and directly. Therefore, two or more non-volatile storage structures in the non-volatile storage structures can be accessed directly simultaneously or in parallel.

[0005] To increase the bandwidth capacity of a high-capacity, high-bandwidth non-volatile memory device, through-silicon vias (TSVs) are used to route signal lines between a controller of the high-bandwidth, high-capacity non-volatile memory device and each non-volatile memory structure on each semiconductor die. In one example, the TSVs and the signal lines are used in place of bond wires to interconnect each non-volatile memory structure and / or semiconductor die to a controller die associated with the high-capacity, high-bandwidth non-volatile memory device. For example, the TSVs provide a communication / signal path between one or more non-volatile memory structures in one or more semiconductor dies of the vertically stacked semiconductor dies and the controller die. Additionally, one or more horizontal metal layers are used to connect one or more non-volatile memory structures on each semiconductor die to each other.

[0006] In one example, the TSVs are arranged in a grid pattern (or another pattern) such that at least one TSV is adjacent to each non-volatile memory structure. Thus, routing signals between the non-volatile memory structure and the controller die of the high-capacity, high-bandwidth non-volatile memory device occurs along the shortest possible communication path.

[0007] Each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device also includes a TSV channel. In one example, the TSV channel is disposed in a middle portion or a central portion of each semiconductor die. The TSV channel includes a plurality of TSVs. Each TSV of the plurality of TSVs communicatively couples one or more non-volatile memory structures in the non-volatile memory structure of each semiconductor die to each other and / or to the controller die.

[0008] Thus, examples of the present disclosure describe a semiconductor device that includes a semiconductor die having a first non-volatile memory structure and a second non-volatile memory structure. A first set of signal lines communicatively couples the first non-volatile memory structure to a controller die of the semiconductor device. In one example, the first set of signal lines is disposed in a first set of through-silicon vias (TSVs) and enables a first set of data to be directly written to the first non-volatile memory structure. A second set of signal lines communicatively couples the second non-volatile memory structure to the controller die of the semiconductor device. In one example, the second set of signal lines is disposed in a second set of TSVs and enables a second set of data to be directly written to the second non-volatile memory structure independently of and in parallel with the first set of data.

[0009] Other examples describe a non-volatile memory device that includes a first semiconductor die having a first non-volatile memory element and a second non-volatile memory element. In one example, the first semiconductor die is stacked on a control element of the non-volatile memory device. The non-volatile memory device also includes a first set of via elements adjacent to the first non-volatile memory element and the second non-volatile memory element. In one example, the first set of via elements is associated with signal elements that directly couple the first non-volatile memory element to the control element of the non-volatile memory device and independently directly couple the second non-volatile memory element to the control element of the non-volatile memory device. The non-volatile memory device also includes a second semiconductor die stacked on the first semiconductor die. In one example, the second semiconductor die includes a third non-volatile memory element and a fourth non-volatile memory element. A second set of via elements is adjacent to the third non-volatile memory element and the fourth non-volatile memory element. In one example, the second set of via elements is associated with signal elements that directly couple the third non-volatile memory element to the control element of the non-volatile memory device and independently directly couple the fourth non-volatile memory element to the control element of the non-volatile memory device.

[0010] Further other examples describe a method of manufacturing a non-volatile memory device having multiple through-silicon vias (TSVs). In one example, the method includes fabricating a plurality of semiconductor dies. Each of the plurality of semiconductor dies includes a plurality of TSVs and a plurality of memory components. A controller die is placed on a substrate. In one example, the controller die includes a plurality of TSVs. A first semiconductor die of the plurality of semiconductor dies is coupled to a top surface of the controller die such that the plurality of TSVs of the first semiconductor die are aligned with corresponding TSVs of the controller die. Each memory component is directly coupled to the controller die using signal lines associated with the plurality of TSVs. The controller die and the first semiconductor die are encapsulated with a molding compound.

[0011] The present invention content is provided to introduce some concepts in a simplified form that will be further described in the detailed description below. The present invention content is not intended to identify key features or essential features of the subject matter protected by the claims, nor is it intended to be used to limit the scope of the subject matter protected by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following non-limiting and non-exhaustive examples are described with reference to the accompanying drawings.

[0013] Figure 1Illustrates a high-capacity, high-bandwidth non-volatile memory device according to one example.

[0014] Figure 2 Illustrates a high-capacity, high-bandwidth non-volatile memory device according to another example.

[0015] Figure 3 Illustrates a method for manufacturing a semiconductor wafer according to one example.

[0016] Figure 4 Illustrates a method for manufacturing a semiconductor wafer according to another example.

[0017] Figures 5A to 5F Illustrates different operations of a semiconductor die manufacturing process according to one example.

[0018] Figures 6A to 6C Illustrates a semiconductor die stacking process according to one example.

[0019] Figure 7 Illustrates a 3D NAND die according to the current solution.

[0020] Figure 8 Illustrates a high-capacity, high-bandwidth non-volatile memory device according to one example. Detailed Description

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments or examples. Without departing from the present disclosure, these aspects may be combined, other aspects may be utilized, and structural changes may be made. Each example may be practiced as a method, system, or device. Thus, the examples may take the form of hardware embodiments, entirely software embodiments, or embodiments combining software aspects with hardware aspects. Accordingly, the following detailed description should not be considered limiting in nature, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0022] As previously mentioned, 3D NAND memory devices are commonly used in various data storage device applications. Examples include memory cards, USB drives, and solid state drives (SSDs). 3D NAND memory devices are preferred for these data storage applications due to their non-volatile nature, large storage capacity, and low cost. However, due to bandwidth limitations, 3D NAND memory devices are often replaced by other memory device technologies for high-speed applications. This is partly because the access time of 3D NAND memory is slower compared to the access time of other memory device technologies such as static random access memory (SRAM) devices and / or dynamic random access memory (DRAM) devices.

[0023] For example, SRAM devices and DRAM devices are often used in graphics processing units (GPUs) and artificial intelligence (AI) applications because these devices have excellent bandwidth capacity compared to 3D NAND memory devices. However, SRAM devices and DRAM devices are volatile memory devices with relatively high production costs and lower storage capabilities compared to 3D NAND memory devices.

[0024] To address the above issues, this application describes a high-capacity, high-bandwidth non-volatile memory device. In one example, the high-capacity, high-bandwidth non-volatile memory device has a capacity that is a hundred times greater than that of current SRAM devices and DRAM devices, and has a bandwidth capacity that is a hundred times greater than that of current 3D NAND memory devices.

[0025] The high-capacity, high-bandwidth non-volatile memory device includes a plurality of vertically stacked semiconductor dies. In one example, the vertically stacked semiconductor dies are 3D NAND memory dies. For example, each semiconductor die has one or more non-volatile memory structures. In one example, each non-volatile memory structure is a 3D NAND plane having a plurality of different memory cells.

[0026] Interconnections between each semiconductor die and / or between various non-volatile memory structures are made using through-silicon vias (TSVs) and associated signal lines (instead of bond wires). Using TSVs instead of bond wires allows each semiconductor die and / or each non-volatile memory structure on each semiconductor die to have a separate and independent signal / communication path to the controller die of the high-capacity, high-bandwidth non-volatile memory device and / or to the process or host device.

[0027] For example, a first TSV (or a first group of TSVs) provides a direct communication / signal path between a first non-volatile memory structure on a semiconductor die and the controller die associated with the high-capacity, high-bandwidth non-volatile memory device. A second TSV (or a second group of TSVs) provides a direct and independent communication / signal path between a second non-volatile memory structure and the controller die associated with the high-capacity, high-bandwidth non-volatile memory device.

[0028] In one example, the second non-volatile memory structure is on the same semiconductor die as the first non-volatile memory structure. In another example, the second non-volatile memory structure is on a different semiconductor die. Thus, the TSVs provide a direct and independent communication path to each non-volatile memory structure on each semiconductor die. Therefore, each non-volatile memory structure can be accessed directly and independently from other memory structures. In another example, the TSVs allow independent and parallel access to each non-volatile memory structure and / or each semiconductor die.

[0029] In another example, the TSVs provide communication / signal paths between a first non-volatile memory structure on a first semiconductor die, a first non-volatile memory structure on a second semiconductor die, and a controller die. In still other examples, one or more metal layers provide communication / signal paths between one or more non-volatile memory structures on the same semiconductor die.

[0030] In one example, the TSVs are arranged in a grid pattern such that at least one TSV is adjacent to each non-volatile memory structure. Thus, routing signals between the non-volatile memory structures and the controller die of the high-capacity, high-bandwidth non-volatile memory device occurs along the shortest possible communication / signal paths. Although a grid pattern is specifically mentioned, other patterns may also be used.

[0031] In one example, the positions and / or patterns of the various TSVs adjacent to and / or between the various non-volatile memory structures depend on the desired granularity level of the high-capacity, high-bandwidth non-volatile memory device. For example, for finer granularity, more TSVs are provided near and / or between different non-volatile memory structures. Thus, one or more TSVs can be used to provide communication / signal paths between each non-volatile memory structure and the controller die of the high-capacity, high-bandwidth non-volatile memory device. If smaller granularity is desired, fewer TSVs are provided near and / or between different non-volatile memory structures.

[0032] In addition to the various TSVs disposed between and / or adjacent to the various non-volatile memory structures, each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device further includes TSV channels. In one example, the TSV channels are disposed in the middle or central portion of each semiconductor die and include a plurality of TSVs. Each TSV of the plurality of TSVs communicatively couples one or more non-volatile memory structures of each semiconductor die to each other and / or to the controller die.

[0033] Thus, the high-capacity, high-bandwidth non-volatile memory device of the present invention provides many technical benefits, including but not limited to increasing the bandwidth capacity of 3D NAND memory devices while maintaining a high capacity and low production / manufacturing cost relative to SRAM devices and / or DRAM devices.

[0034] These examples and other examples will be described in more detail with respect to Figures 1 to 8 These examples and other examples will be described in more detail.

[0035] Figure 1Illustrated is a high-capacity, high-bandwidth non-volatile memory device 100 according to an example. In one example, the high-capacity, high-bandwidth non-volatile memory device 100 has a capacity that is a hundred times (or more) the capacity of current SRAM devices and DRAM devices, and has a bandwidth capacity that is more than a hundred times (or more) the bandwidth capacity of current 3D NAND memory devices. Additionally, the high-capacity, high-bandwidth non-volatile memory device 100 can be used in a variety of different high-speed applications, including but not limited to graphics processing units (GPUs) and / or artificial intelligence (AI) implementations, etc.

[0036] In one example, the high-capacity, high-bandwidth non-volatile memory device 100 is a 3D NAND memory device. However, as previously mentioned, the high-capacity, high-bandwidth non-volatile memory device 100 has a higher bandwidth capacity compared to currently available 3D NAND memory devices. For example, the high-capacity, high-bandwidth non-volatile memory device 100 has a bandwidth capacity of at least 1.5 terabytes (TB) per second (although higher capacities are envisioned and achievable). Additionally, the high-capacity, high-bandwidth non-volatile memory device 100 has a higher capacity (compared to currently available 3D NAND memory devices) and a higher capacity (compared to DRAM memory devices and SRAM memory devices). For example, the high-capacity, high-bandwidth non-volatile memory device 100 has a capacity of at least two TB (although higher capacities are envisioned and achievable).

[0037] In one example, the high-capacity, high-bandwidth non-volatile memory device 100 includes a plurality of semiconductor dies. In one example, the size of each semiconductor die is eight millimeters (mm) by ten mm. Although specific sizes are given, these semiconductor dies can have any suitable size and can be at least partially based on the number of non-volatile storage structures included on the semiconductor die.

[0038] In one example, the high-capacity, high-bandwidth non-volatile memory device 100 includes a first semiconductor die 110, a second semiconductor die 120, and an Nth semiconductor die 130. In the example shown, the high-capacity, high-bandwidth non-volatile memory device 100 has eight semiconductor dies. Although eight semiconductor dies are shown, the high-capacity, high-bandwidth non-volatile memory device 100 can include any number of semiconductor dies. For example, the high-capacity, high-bandwidth non-volatile memory device 100 can include sixteen semiconductor dies or thirty-two (or more) semiconductor dies.

[0039] In one example, each semiconductor die includes one or more non-volatile memory structures. For example, the Nth semiconductor die 130 includes a first non-volatile memory structure 140 and a second non-volatile memory structure 150. Although the first non-volatile memory structure 140 and the second non-volatile memory structure 150 are specifically mentioned, each semiconductor die includes any number of non-volatile memory structures. For example, each semiconductor die includes at least twenty-four non-volatile memory structures. Although twenty-four non-volatile memory structures are mentioned, the high-capacity, high-bandwidth non-volatile memory device 100 may have more (or fewer) than twenty-four non-volatile memory structures.

[0040] In one example, each non-volatile memory structure is accessed independently of but in parallel with other non-volatile memory structures. For example, the first non-volatile memory structure 140 is accessed independently of but in parallel with the second non-volatile memory structure 150.

[0041] To achieve this, each non-volatile memory structure is associated with its own set of signal lines that directly couple the non-volatile memory structure to the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100. For example, the first non-volatile memory structure 140 is associated with a first set of signal lines (and associated TSVs), and the second non-volatile memory structure 150 is associated with a second set of signal lines (and associated TSVs). In one example, each set of signal lines includes or supports eight signals / eight wires. In other examples, each set of signal lines may support any number of signals from eight signals up to two hundred and fifty-six (or more) signals.

[0042] In one example, each of the first non-volatile memory structure 140 and the second non-volatile memory structure 150 is a 3D NAND device. In one example, each 3D NAND device includes one or more planes, and each plane includes one or more memory cells.

[0043] As Figure 1As shown, each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device 100 is vertically stacked on top of each other. For example, the second semiconductor die 120 is stacked on top of the first semiconductor die 110, and the Nth semiconductor die 130 is stacked on top of the (N-1)th semiconductor die. In one example, thirty-two (or more) semiconductor dies can be stacked on top of each other. Regardless of the number of semiconductor dies, the interconnection between the various semiconductor dies is formed by various through-silicon vias (TSVs). Each TSV enables direct and independent access to each non-volatile memory structure (e.g., receiving data / instructions from the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100 and / or providing data to the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100). This configuration is different from current 3D NAND memory devices.

[0044] For example and with reference Figure 7 , Figure 7 illustrates a 3D NAND die 700 according to a current solution. As Figure 7 shown, the 3D NAND die 700 includes four planes: plane-1 710, plane-2 720, plane-3 730, and plane-4 740. An eight-bit input / output (I / O) line 750 with eight signal lines enables the 3D NAND die 700 to receive data 760 (e.g., from a controller die or another component associated with the 3D NAND die 700).

[0045] When the eight-bit I / O line 750 is coupled to the 3D NAND die 700, a component 770 (e.g., a multiplexer) associated with the 3D NAND die 700 uses other signal lines to distribute the signals, which enables parallel access to plane-1 710, plane-2 720, plane-3 730, and plane-4 740.

[0046] For example, a single eight-bit I / O line 750 is communicatively coupled to the component 770. Four different sets of additional signal lines communicatively couple each plane to the component 770. However, regardless of the number of planes in the 3D NAND die 700 and regardless of whether access to the planes is parallel, a single eight-bit I / O line 750 is the only path for providing the data 760 to each of the planes in the plane. Therefore, the bandwidth capacity of the 3D NAND die 700 is limited.

[0047] Figure 8 illustrates a semiconductor die 800 for a high-capacity, high-bandwidth non-volatile memory device according to an example. In one example, the semiconductor die 800 is similar to that regarding Figure 1One or more of the first semiconductor die 110, the second semiconductor die 120, and the Nth semiconductor die 130 shown and described.

[0048] In one example, the semiconductor die 800 includes one or more non-volatile memory structures. For example, Figure 8 It is illustrated that the semiconductor die 800 includes eight non-volatile memory structures. Although eight non-volatile memory structures are shown and described, the semiconductor die 800 may include any number of non-volatile memory structures.

[0049] In one example, each of these non-volatile memory structures is a 3D NAND device (e.g., a NAND array plane). For example, the semiconductor die 800 includes Plane-1 810, Plane-2 840, Plane-3, Plane-4, Plane-5, Plane-6, Plane-7, and Plane-8. Additionally, each non-volatile memory structure includes its own set signal line or is associated with the set signal line. For example, Plane-1 810 is associated with the first set of signal lines 830, Plane-2 840 is associated with the second set of signal lines 860, etc.

[0050] In one example, each set of signal lines is an eight-bit I / O line having eight individual signal lines. Although eight signal lines are shown and described, each set of signal lines may have any number of signal lines. For example, each set of signal lines may support up to two hundred and fifty-six (or more) lines / two hundred and fifty-six (or more) signals. In one example, each signal line from each set of signal lines is disposed within a through-silicon via (TSV) or otherwise associated with the through-silicon via. Each set of signal lines enables the data associated with each set of signal lines to be directly input into each non-volatile memory structure 810.

[0051] For example, the first set of signal lines 830 associated with Plane-1 810 enables the first data 820 (or the first portion of the data) to be directly written into Plane-1 810 and / or read from the plane. Similarly, the second set of signal lines 860 associated with Plane-2 840 enables the second data 850 (or the second portion of the data), different from the first data 820, to be directly written into Plane-2 840 and / or read from the plane.

[0052] Because each non-volatile memory structure is associated with its own set of signal lines, data is independently and parallelly directly written into each non-volatile memory structure and / or directly read from each non-volatile memory structure. This is in contrast to Figure 7Shown and described in contrast to 3D NAND die 700, 3D NAND die 700 requires a multiplexer or other components to divide a single eight-bit I / O line associated with 3D NAND die 700 into different signal lines / paths within 3D NAND die 700. Thus, compared to Figure 7 the 3D NAND die 700, Figure 8 the semiconductor die 800 achieves a much higher bandwidth.

[0053] Returning to reference Figure 2 , in one example and as previously described, each signal line in each group of signal lines is associated with a TSV. In one example, the TSVs are arranged in a grid pattern including multiple rows and / or columns. The rows and / or columns of TSVs are also referred to as TSV groups. Although a grid pattern is specifically mentioned, other patterns may also be used.

[0054] In one example, each semiconductor die has the same pattern or a similar pattern. For example, the arrangement of the TSVs on the Nth semiconductor die 130 is the same as or similar to the arrangement of the TSVs on the first semiconductor die 110. Thus, when stacking these semiconductor dies, the TSVs of each semiconductor die are aligned. Additionally, the TSVs extend throughout the high-capacity, high-bandwidth non-volatile memory device 100.

[0055] In one example, the TSVs are arranged such that one or more TSVs are adjacent to one or more non-volatile memory structures of each semiconductor die. In another example, one or more TSVs are disposed between adjacent non-volatile memory structures. In such arrangements, each semiconductor die and / or each non-volatile memory structure of each semiconductor die can be accessed and / or programmed directly and independently. For example, the first TSV (or the first group of TSVs) provides a first communication / signal path between the first non-volatile memory structure on the first semiconductor die and the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100. Similarly, the second TSV (or the second group of TSVs) provides a second communication / signal path between the second non-volatile memory structure on the first semiconductor die and the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100.

[0056] In another example, a second TSV (or a second group of TSVs) provides a second communication / signal path between a second non-volatile memory structure on a second semiconductor die and a controller die 190 of a high-capacity, high-bandwidth non-volatile memory device 100. Thus, each non-volatile memory structure on the same semiconductor die (or on different semiconductor dies) is capable of being accessed independently of one another. Although the non-volatile memory structures are capable of being accessed independently of one another, the TSVs allow for parallel access to one or more of the non-volatile memory structures.

[0057] For example, the TSVs enable direct access to a first non-volatile memory structure on a first semiconductor die independently of and in parallel with a second non-volatile memory structure on the first semiconductor die. In another example, the TSVs enable direct access to a first non-volatile memory structure on a first semiconductor die independently of and in parallel with a second non-volatile memory structure on a second semiconductor die. In yet another example, a single TSV (or a group of TSVs) interconnects one or more non-volatile memory structures on a first semiconductor die to one or more non-volatile memory structures on a second semiconductor die.

[0058] In one example, two or more non-volatile memory structures are grouped together (e.g., logically grouped) to form an independent memory region. The two or more non-volatile memory structures can be on the same semiconductor die or on different semiconductor dies. When the non-volatile memory structures are grouped, one or more TSVs and associated signal lines provide a communication / signal path to each non-volatile memory structure in the group. For example, a first TSV provides a first communication / signal path to a first non-volatile memory structure in the group, and a second TSV provides a second communication / signal path to a second non-volatile memory structure in the group.

[0059] Additionally, the TSVs are positioned adjacent to, close to, and / or between one or more non-volatile memory structures to provide the shortest possible signal paths between the various non-volatile memory structures, the various semiconductor dies, and / or the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100. In one example, the shorter the communication path between the various non-volatile memory structures, the various semiconductor dies, and / or the controller die 190, the higher the bandwidth capacity of the high-capacity, high-bandwidth non-volatile memory device 100.

[0060] In one example, the Nth semiconductor die 130 includes a first row of TSVs 160. The first row of TSVs 160 is disposed between a first non-volatile memory structure 140 and a second non-volatile memory structure 150. Additionally, the Nth semiconductor die 130 includes a first column of TSVs 170. The first column of TSVs 170 is disposed between the first non-volatile memory structure 140 and a third non-volatile memory structure 155.

[0061] The first row of TSVs 160 extends at least partially across the width of the Nth semiconductor die 130. Additionally, the first column of TSVs 170 extends at least partially across the length of the Nth semiconductor die 130. Although a particular arrangement and pattern of TSVs are shown, the TSVs can be arranged in any pattern and each row or column of TSVs can include any number of TSVs.

[0062] Each semiconductor die also includes a TSV channel that includes a plurality of different TSVs. For example, the Nth semiconductor die 130 includes a TSV channel 180. In one example, the TSV channel 180 is disposed in the middle portion of the Nth semiconductor die 130. In one example, the TSV channel 180 includes one thousand and twenty-four TSVs. Although a particular number of TSVs has been given, this is for illustrative purposes only and the TSV channel 180 can include any number of TSVs.

[0063] Like other TSVs described herein, the TSVs in the TSV channel 180 are used to directly couple one or more non-volatile memory structures on the same semiconductor die to the controller die 190. The TSVs in the TSV channel 180 also communicatively couple one or more non-volatile memory structures on two or more semiconductor dies to the controller die 190.

[0064] For example, the first TSV (or TSVs) in the column of TSVs 170 (and / or one or more TSVs in the row of TSVs 160) communicatively couples the first non-volatile memory structure 140 on the Nth semiconductor die 130 and / or the second non-volatile memory structure 150 on the Nth semiconductor die to the controller die 190. In another example, the first TSV (or TSVs) in the column of TSVs 170 (and / or one or more TSVs in the column of TSVs 160) communicatively couples the first non-volatile memory structure 140 on the Nth semiconductor die 130 to the first non-volatile memory structure on the N-1th semiconductor die. In such examples, the first TSV in the column of TSVs 170 also communicatively couples the first non-volatile memory structure 140 on the Nth semiconductor die 130 and the first non-volatile memory structure on the N-1th semiconductor die to the controller die 190.

[0065] Although specific examples are given, each TSV of the high-capacity, high-bandwidth non-volatile memory device 100 is used to interconnect one or more semiconductor dies and / or one or more non-volatile memory structures on one or more semiconductor dies with each other and / or to a controller die 190.

[0066] The TSVs are also used to route input / output (I / O) signals, power signals, and / or ground signals from various non-volatile memory structures on each semiconductor die to the controller die 190 of the high-capacity, high-bandwidth non-volatile memory device 100. The controller die 190 is operable to route signals to / from various semiconductor dies, control garbage collection operations, control error correction operations, control refresh operations, and / or manage the traffic of various signals sent to various semiconductor dies via the TSVs.

[0067] The controller die 190 also includes one or more connection points 195. In one example, the connection point is a micro-bump, a solder ball, or other connection / communication mechanism that enables the high-capacity, high-bandwidth non-volatile memory device 100 to be communicatively coupled to another device (e.g., a controller, another high-capacity, high-bandwidth non-volatile memory device, a substrate, a printed circuit board (PCB)). Accordingly, the connection points 195 are disposed on the bottom surface of the controller die 190.

[0068] In one example, each connection point 195 is associated with a specific TSV. Accordingly, one or more TSVs of the high-capacity, high-bandwidth non-volatile memory device 100 extend from the connection points 195 through the controller die 190 and through one or more semiconductor dies, and / or extend to one or more non-volatile memory structures. Accordingly, there may be a direct communication path between the connection point and a specific non-volatile memory structure.

[0069] Figure 2 Illustrated is a high-capacity, high-bandwidth non-volatile memory device 200 according to another example. In one example, the high-capacity, high-bandwidth non-volatile memory device 200 is similar to the high-capacity, high-bandwidth non-volatile memory device 100 shown and described with respect to Figure 1 For example, the high-capacity, high-bandwidth non-volatile memory device 200 includes a first semiconductor die 210, a second semiconductor die 220, and an Nth conductor die 230 that are vertically stacked on top of each other.

[0070] In addition, each semiconductor die includes one or more non-volatile memory structures. For example, the Nth semiconductor die 230 includes a first non-volatile memory structure 240 and a second non-volatile memory structure 250. Although two non-volatile memory structures are specifically mentioned, each semiconductor die may include any number of non-volatile memory structures.

[0071] Each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device 200 also includes a plurality of TSVs arranged in a pattern. For example, each semiconductor die of the high-capacity, high-bandwidth non-volatile memory device 200 includes one or more rows of TSVs 260 and one or more columns of TSVs 270, such as those described with respect to Figure 1 However, in this example, each semiconductor die includes various TSVs disposed around the perimeter 280. Although additional TSVs are shown around the perimeter 280 of each semiconductor die, this is for illustrative purposes only and to show that the TSVs can be arranged in any pattern.

[0072] In addition, similar to Figure 1 the high-capacity, high-bandwidth non-volatile memory device 100, the high-capacity, high-bandwidth non-volatile memory device 200 includes a TSV channel 290. In one example, the TSV channel 290 functions in a manner similar to the TSV channel 180 shown and described with respect to Figure 1 In one example, each TSV in the high-capacity, high-bandwidth non-volatile memory device 200 from the controller extends through each semiconductor die from the controller die 295 (and / or from one or more connection points 285 associated with the controller die 295). For example, the TSV 275 extends from the connection point 285 of the controller die 295 through the first semiconductor die 210, the second semiconductor die 220 to the Nth semiconductor die 230.

[0073] In another example, the TSV may extend partially through the high-capacity, high-bandwidth non-volatile memory device 200. For example, the TSV 265 extends through only two semiconductor dies, while the TSV 255 extends from the controller die 295 and extends partially through the high-capacity, high-bandwidth non-volatile memory device 200.

[0074] Illustrated is a method 300 for manufacturing a semiconductor wafer according to one example. In one example, the semiconductor wafer manufacturing process is used to manufacture the high-capacity, high-bandwidth non-volatile memory device 100 shown and described with respect to

[0075] Figure 3 and / or the high-capacity, high-bandwidth non-volatile memory device 200 shown and described with respect to Figure 1 and / or with respect to Figure 2One or more semiconductor dies used in the high-capacity, high-bandwidth non-volatile memory device 200 shown and described. In such examples, the semiconductor wafer includes CMOS circuitry and NAND circuitry, and each layer is formed or fabricated on the same wafer.

[0076] Method 300 begins with an implantation process, where one or more transistors are implanted and connected (310) on the wafer. In one example, the wafer is a CMOS wafer. Additionally, any suitable transistor implantation and / or connection process can be used.

[0077] When the transistors have been implanted and connected, one or more through-silicon vias (TSVs) are formed (320) in the wafer. In one example, the TSVs are blind TSVs. Thus, the TSVs extend at least partially through the CMOS wafer.

[0078] In one example, some of the TSVs are arranged in a pattern or grid. For example, the TSVs are arranged such that they will be adjacent to one or more non-volatile memory structures such as those previously described. In other examples, other TSVs are arranged to form TSV channels. In one example, TSV channels are formed in the middle portion of the CMOS wafer.

[0079] When the TSVs have been formed, a metallization process is initiated. In one example, the metallization process is a process of connecting (330) the CMOS circuitry to the TSVs.

[0080] Subsequently, one or more non-volatile memory structures are added (340) to the wafer. In one example, the non-volatile memory structures are 3D NAND memory structures. Additionally, the 3D NAND memory structures are placed on the wafer such that the structures are adjacent to one or more of the TSV groups and / or TSV channels.

[0081] Once the non-volatile memory structures have been added, the top surface of the wafer is completed. As will be described in more detail with respect to Figures 5A to 5F Additional processes / operations are performed to prepare the wafer for bonding.

[0082] Figure 4 Illustrated is a method 400 for manufacturing a semiconductor wafer according to another example. In one example, the semiconductor wafer manufacturing process is used to manufacture the high-capacity, high-bandwidth non-volatile memory device 100 shown and described with respect to Figure 1 and / or with respect to Figure 2One or more semiconductor dies used in the high-capacity, high-bandwidth non-volatile memory device 200 shown and described. In this example, the semiconductor wafer includes CMOS circuitry and NAND circuitry, and each layer is formed on a separate wafer. Subsequently, the wafers are bonded together. Thus, regarding Figure 4 One or more of the operations shown and described may be performed sequentially or in parallel.

[0083] Method 400 begins with an implantation process, where one or more transistors are implanted and connected (410) on the CMOS wafer. In one example, any suitable process may be used to implant the transistors on the CMOS wafer.

[0084] When the transistors have been implanted and connected on the CMOS wafer, one or more through-silicon vias (TSVs) are formed (420) in the wafer. In one example, the TSVs are blind TSVs. Thus, the TSVs extend at least partially through the CMOS wafer.

[0085] In one example, the TSVs are arranged in a pattern or grid. For example, the TSVs are arranged such that they will be adjacent to one or more non-volatile memory structures such as those previously described. In other examples, the TSVs are arranged to form TSV channels. In one example, the TSV channels are formed in the middle portion of the CMOS wafer.

[0086] Once the TSVs have been formed in the CMOS wafer, a metallization process is initiated. During the metallization process, the CMOS circuitry is connected (430) to the TSVs. Subsequently, the CMOS wafer is prepared (440) for a subsequent bonding process.

[0087] Method 400 also includes fabricating a non-volatile memory layer or non-volatile memory wafer. In one example, the non-volatile memory wafer is a 3D NAND memory wafer. Additionally, the preparation of the non-volatile memory wafer may occur concurrently with one or more of the operations previously described. In another example, the operations for fabricating the non-volatile memory wafer occur before or after fabricating the CMOS wafer.

[0088] In one example, the non-volatile memory wafer is prepared when one or more non-volatile memory structures (e.g., 3D NAND memory structures or layers) are added (450) to the wafer. In one example, any suitable method for adding the non-volatile memory structures to the wafer may be used. Once the non-volatile memory structures have been added to the wafer, the non-volatile memory wafer is prepared (460) for bonding. In one example, the non-volatile memory wafer is prepared for bonding by adding one or more micro-bumps, adhesives, or other connection mechanisms to the top surface of the non-volatile memory wafer.

[0089] When a CMOS wafer and a NAND wafer have been prepared for bonding, the CMOS wafer and the non-volatile memory wafer are bonded (470). In one example, the CMOS wafer and the non-volatile memory wafer are bonded face-to-face (e.g., device layer to device layer). Subsequently, a silicon layer is removed (480) from one or more of the non-volatile memory wafer and / or the CMOS wafer. The surface of the resulting structure is intact. As will be described in more detail with respect to Figures 5A to 5F Additional processes / operations are performed to prepare the non-volatile memory wafer for bonding.

[0090] Figures 5A to 5F Illustrates different operations of a semiconductor die manufacturing process according to one example. The semiconductor die manufacturing process can be used to manufacture one or more semiconductor dies (e.g., first semiconductor die 110( Figure 1 )) for a high-capacity, high-bandwidth non-volatile memory device (e.g., high-capacity, high-bandwidth non-volatile memory device 100( Figure 1 ).

[0091] Figure 5A Illustrates a semiconductor wafer 500 according to one example. In one example, the semiconductor wafer 500 is the result of various operations performed as part of and / or otherwise in accordance with method 300 as shown and described with respect to Figure 3 and / or method 400 as shown and described with respect to Figure 4 .

[0092] In one example, the semiconductor wafer 500 includes a non-volatile memory layer 510 (e.g., 3D NAND layer) and a CMOS layer 520. Additionally, the semiconductor wafer includes one or more TSVs 540 extending through a silicon layer 530. In one example, the TSVs 540 are blind TSVs that partially extend through the silicon layer 530. The TSVs can be part of a TSV channel and / or arranged in a grid or pattern such as previously described.

[0093] Figure 5B Illustrates a second operation of the manufacturing process, where a first carrier layer 560 is bonded to the non-volatile memory layer 510 of the semiconductor wafer 500. In one example, the first carrier layer 560 is thermally bonded to the non-volatile memory layer 510 using an adhesive 550 or other bonding material.

[0094] When the first carrier layer 560 has been bonded to the non-volatile memory layer 510, the silicon layer 530 is thinned or reduced in thickness. In one example, the silicon layer 530 is thinned to expose at least a portion of the TSV 540. The silicon layer 530 is thinned and / or the TSV 540 is exposed by any suitable process. For example, an etching process (e.g., a plasma etching process) is used to reduce the thickness of the silicon layer 530 and / or expose the TSV 540. As Figure 5C shown, once the silicon layer 530 has been thinned, micro-bumps 570 are formed or otherwise disposed on each TSV 540.

[0095] Figure 5D illustrates another operation of a manufacturing process according to an example, in which a second carrier layer 580 is bonded to the CMOS layer 520 (or the silicon layer 530) of the semiconductor wafer 500. Similar to the first carrier layer 560, the second carrier layer 580 is bonded to the CMOS layer 520 using an adhesive 575 or another bonding material. As Figure 5D shown, once the second carrier layer 580 has been bonded to the CMOS layer 520, the first carrier layer 560 is removed from the semiconductor wafer 500.

[0096] Figure 5E illustrates another operation of a manufacturing process according to an example. As Figure 5E shown, once the first carrier layer 560 has been removed, micro-bumps 590 are formed on the various micro-bumps 585 of the non-volatile memory layer 510.

[0097] After the micro-bumps 590 have been formed, the semiconductor wafer 500 is mounted on a dicing tape, and the second carrier layer 580 is removed. For example, Figure 5F illustrates the semiconductor wafer 500 being mounted onto a dicing tape 595. Additionally, the second carrier layer 580 has been removed, which exposes the micro-bumps 570 on the CMOS layer 520. Subsequently, the semiconductor wafer 500 may undergo a singulation process in which individual semiconductor dies are separated from the semiconductor wafer 500.

[0098] Figures 6A to 6C illustrates a semiconductor die stacking process according to an example. In one example, Figures 6A to 6C the semiconductor die stacking process shown in Figures 5A to 5F uses semiconductor dies that have been separated from the semiconductor wafer 500 shown in Figure 1 to fabricate the high-capacity, high-bandwidth non-volatile memory device 100 shown and described with respect to Figure 2 and / or the high-capacity, high-bandwidth non-volatile memory device 200 shown and described with respect to

[0099] For example, as Figure 6AAs shown, the first semiconductor die 600 is placed and / or coupled to a substrate 610. In one example, the first semiconductor die 600 is a controller die. In one example, the controller die 600 includes a plurality of TSVs. The TSVs are arranged in a pattern or grid. The TSVs may also be arranged to form TSV channels.

[0100] The first semiconductor die 600 is bonded to the substrate 610 using solder balls 620 or other connection mechanisms. Once the semiconductor die 600 is placed on the substrate, a reflow process is initiated that melts the solder balls 620. In another example, the semiconductor die 600 is placed on the substrate 610 and the reflow process is not initiated until all semiconductor dies have been stacked (e.g., a batch reflow process).

[0101] Once the first semiconductor die 600 has been placed on and / or bonded to the substrate 610, a second semiconductor die 630 ( Figure 6B ) is placed on top of and / or bonded to the top surface of the first semiconductor die 600. This process continues until the desired number of semiconductor dies have been stacked on top of each other. In one example, during the stacking process, the TSVs of each semiconductor die are aligned with the other TSVs, creating a communication path between the topmost semiconductor die and the controller die.

[0102] Once the desired number of semiconductor dies have been stacked, signal lines are routed through the TSVs such that each memory component on each semiconductor die can be directly coupled to the substrate. A molding compound 640 is used to encapsulate the structure, and a high-capacity, high-bandwidth non-volatile memory device 650 has been created.

[0103] An example of the present application describes a semiconductor device that includes: a semiconductor die having a first non-volatile memory structure and a second non-volatile memory structure; a first set of signal lines that communicatively couple the first non-volatile memory structure to a controller die of the semiconductor device, the first set of signal lines being disposed in a first set of through-silicon vias (TSVs) and enabling a first set of data to be directly written to the first non-volatile memory structure; and a second set of signal lines that communicatively couple the second non-volatile memory structure to the controller die of the semiconductor device, the second set of signal lines being disposed in a second set of TSVs and enabling a second set of data to be directly written to the second non-volatile memory structure independently of and in parallel with the first set of data. In one example, the semiconductor further includes a TSV channel that includes at least one of a first signal line from the first set of signal lines and a first signal line from the second set of signal lines. In one example, the TSV channel is disposed in a middle portion of the semiconductor die. In one example, at least a portion of the first set of TSVs is positioned between the first non-volatile memory structure and the second non-volatile memory structure. In one example, the semiconductor die is a first semiconductor die, and the semiconductor device further includes: a second semiconductor die stacked on the first semiconductor die and having a third non-volatile memory structure and a fourth non-volatile memory structure; a third set of signal lines that communicatively couple the third non-volatile memory structure to the controller die of the semiconductor device, the third set of signal lines being disposed in a third set of TSVs and enabling a third set of data to be directly written to the third non-volatile memory structure independently of and in parallel with the first set of data and the second set of data; and a fourth set of signal lines that communicatively couple the fourth non-volatile memory structure to the controller die of the semiconductor device, the fourth set of signal lines being disposed in a fourth set of TSVs and enabling a fourth set of data to be directly written to the fourth non-volatile memory structure independently of and in parallel with the first set of data, the second set of data, and the third set of data. In one example, at least one TSV of the first set of TSVs and at least one TSV are the third set of TSVs that communicatively couple the first non-volatile memory structure and the third non-volatile memory structure. In one example, at least one TSV from the third set of TSVs and at least one TSV from the fourth set of TSVs are positioned between the third non-volatile memory structure and the fourth non-volatile memory structure. In one example, the first non-volatile memory structure and the second non-volatile memory structure are three-dimensional (3D) NAND planes.In one example, the semiconductor device further includes a plurality of connection points disposed on a bottom surface of the controller die, wherein each connection point of the plurality of connection points is associated with a TSV in the first set of TSVs and the second set of TSVs.

[0104] The example also describes a non-volatile memory device including: a first semiconductor die having a first non-volatile memory component and a second non-volatile memory component, the first semiconductor die stacked on a control component of the non-volatile memory device; a first set of via components adjacent to the first non-volatile memory component and the second non-volatile memory component, the first set of via components associated with a signal component that directly couples the first non-volatile memory component to the control component of the non-volatile memory device and independently directly couples the second non-volatile memory component to the control component of the non-volatile memory device; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a third non-volatile memory component and a fourth non-volatile memory component; and a second set of via components adjacent to the third non-volatile memory component and the fourth non-volatile memory component, the second set of via components associated with a signal component that directly couples the third non-volatile memory component to the control component of the non-volatile memory device and independently directly couples the fourth non-volatile memory component to the control component of the non-volatile memory device. In one example, the non-volatile memory device further includes: a plurality of via components disposed on the first semiconductor die, the first plurality of via components associated with a signal component that directly couples one or more of the first non-volatile memory component and the second non-volatile memory component to the control component of the non-volatile memory device. In one example, the plurality of via components are disposed in a middle portion of the first semiconductor die. In one example, at least one via component of the first set of via components and at least one via component of the third set of via components communicatively couple the first non-volatile memory component and the third non-volatile memory component. In one example, the first non-volatile memory component is a three-dimensional (3D) NAND plane. In one example, the non-volatile memory device further includes a plurality of connection components disposed on a bottom surface of the control component, wherein each connection component of the plurality of connection components is associated with a TSV in the first set of via components and the second set of via components.

[0105] The example also describes a method of manufacturing a non-volatile memory device having a plurality of through-silicon vias (TSVs), the method comprising: manufacturing a plurality of semiconductor dies, each of the plurality of semiconductor dies having a plurality of TSVs and a plurality of memory components; placing a controller die on a substrate, the controller die including a plurality of TSVs; coupling a first semiconductor die of the plurality of semiconductor dies to a top surface of the controller die such that the plurality of TSVs of the first semiconductor die are aligned with corresponding TSVs of the controller die; directly coupling each memory component to the controller die using signal lines associated with the plurality of TSVs; and encapsulating the controller die and the first semiconductor die with a molding compound. In one example, the first semiconductor die is coupled to the top surface of the controller die using a plurality of solder balls. In one example, the method further comprises initiating a reflow process to melt the plurality of solder balls. In one example, the reflow process is initiated after the first semiconductor die is coupled to the top surface of the controller die. In one example, the reflow process is a batch reflow process initiated after a second semiconductor die is placed on a top surface of the first semiconductor die and after the first semiconductor die is placed on the controller die.

[0106] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The various aspects, examples, and details provided in this disclosure are regarded as sufficient to convey ownership and the best way for others to make and use the disclosure protected by the claims.

[0107] The disclosure protected by the claims should not be understood as being limited to any aspect, example, or detail provided in this disclosure. Whether shown and described combinatorially or individually, the various features (both structural and method features) are intended to be selectively rearranged, included, or omitted to produce embodiments having a particular set of features. Having provided the description and illustration of this application, those skilled in the art can envision variations, modifications, and alternative aspects that fall within the spirit of the broader aspects of the general inventive concept specifically embodied in this application and do not depart from the broader scope of the disclosure protected by the claims.

[0108] The use of names such as "first", "second", etc. to refer to elements herein generally does not limit the number or order of those elements. Instead, these names can be used as a way to distinguish two or more elements or instances of elements. Thus, referring to a first element and a second element does not mean that only two elements can be used, nor does it mean that the first element must precede the second element. Additionally, unless otherwise specified, a group of elements can include one or more elements.

[0109] The term in the form of "at least one of A, B, or C" or "any combination of A, B, C, or them" used in the specification or claims means "A or B or C or any combination of these elements". For example, this term may include A, or B, or C, or A and B, or A and C, or A, B, and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiples of the same members. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, as well as multiples of the same members.

[0110] Similarly, as used herein, a phrase referring to a list of items linked by "and / or" means any combination of the items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor die having a first non-volatile memory structure and a second non-volatile memory structure; A first set of signal lines that communicatively couple the first non-volatile memory structure to a controller die of the semiconductor device, the first set of signal lines being disposed in a first set of through-silicon vias (TSVs) and enabling a first set of data to be directly written to the first non-volatile memory structure; And A second set of signal lines that communicatively couple the second non-volatile memory structure to the controller die of the semiconductor device, the second set of signal lines being disposed in a second set of TSVs and enabling a second set of data to be directly written to the second non-volatile memory structure independently of and in parallel with the first set of data.

2. The semiconductor device according to claim 1, the semiconductor device further comprising a TSV channel that includes at least one of a first signal line from the first set of signal lines and a first signal line from the second set of signal lines.

3. The semiconductor device according to claim 1, wherein the TSV channel is disposed in a middle portion of the semiconductor die.

4. The semiconductor device according to claim 1, wherein at least a portion of the first set of TSVs is positioned between the first non-volatile memory structure and the second non-volatile memory structure.

5. The semiconductor device according to claim 1, wherein the semiconductor die is a first semiconductor die, the semiconductor device further comprising: A second semiconductor die stacked on the first semiconductor die and having a third non-volatile memory structure and a fourth non-volatile memory structure; A third set of signal lines that communicatively couple the third non-volatile memory structure to the controller die of the semiconductor device, the third set of signal lines being disposed in a third set of TSVs and enabling a third set of data to be directly written to the third non-volatile memory structure independently of and in parallel with the first set of data and the second set of data; And A fourth set of signal lines that communicatively couple the fourth non-volatile memory structure to the controller die of the semiconductor device, the fourth set of signal lines being disposed in a fourth set of TSVs and enabling a fourth set of data to be directly written to the fourth non-volatile memory structure independently of and in parallel with the first set of data, the second set of data, and the third set of data.

6. The semiconductor device according to claim 5, wherein at least one TSV of the first set of TSVs and at least one TSV are the third set of TSVs that communicatively couple the first non-volatile memory structure and the third non-volatile memory structure.

7. The semiconductor device according to claim 5, wherein at least one TSV from the third group of TSVs and at least one TSV from the fourth group of TSVs are positioned between the third non-volatile memory structure and the fourth non-volatile memory structure.

8. The semiconductor device according to claim 1, wherein the first non-volatile memory structure and the second non-volatile memory structure are three-dimensional (3D) NAND planes.

9. The semiconductor device according to claim 1, the semiconductor device further comprising a plurality of connection points disposed on a bottom surface of the controller die, wherein each connection point of the plurality of connection points is associated with a TSV in the first group of TSVs and the second group of TSVs.

10. A non-volatile memory device, the non-volatile memory device comprising: a first semiconductor die having a first non-volatile memory component and a second non-volatile memory component, the first semiconductor die being stacked on a control component of the non-volatile memory device; a first group of via components adjacent to the first non-volatile memory component and the second non-volatile memory component, the first group of via components being associated with signal components that directly couple the first non-volatile memory component to the control component of the non-volatile memory device and independently directly couple the second non-volatile memory component to the control component of the non-volatile memory device; a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a third non-volatile memory component and a fourth non-volatile memory component; and a second group of via components adjacent to the third non-volatile memory component and the fourth non-volatile memory component, the second group of via components being associated with signal components that directly couple the third non-volatile memory component to the control component of the non-volatile memory device and independently directly couple the fourth non-volatile memory component to the control component of the non-volatile memory device.

11. The non-volatile memory device according to claim 10, the non-volatile memory device further comprising a plurality of via components disposed on the first semiconductor die, the first plurality of via components being associated with signal components that directly couple one or more of the first non-volatile memory component and the second non-volatile memory component to the control component of the non-volatile memory device.

12. The non-volatile memory device according to claim 11, wherein the plurality of via components are disposed in a middle portion of the first semiconductor die.

13. The non - volatile memory device according to claim 10, wherein at least one via member in the first group of via members and at least one via member in the third group of via members communicatively couple the first non - volatile storage member and the third non - volatile storage member.

14. The non - volatile memory device according to claim 10, wherein the first non - volatile storage member is a three - dimensional (3D) NAND plane.

15. The non - volatile memory device according to claim 10, the non - volatile memory device further comprising a plurality of connection members disposed on a bottom surface of the control member, wherein each of the plurality of connection members is associated with a TSV in the first group of via members and the second group of via members.

16. A method of manufacturing a non - volatile memory device having a plurality of through - silicon vias (TSVs), the method comprising: fabricating a plurality of semiconductor dies, each of the plurality of semiconductor dies having a plurality of TSVs and a plurality of memory components; placing a controller die on a substrate, the controller die including a plurality of TSVs; coupling a first semiconductor die of the plurality of semiconductor dies to a top surface of the controller die such that the plurality of TSVs of the first semiconductor die are aligned with corresponding TSVs of the controller die; directly coupling each memory component to the controller die using signal lines associated with the plurality of TSVs; and encapsulating the controller die and the first semiconductor die with a molding compound.

17. The method according to claim 16, wherein the first semiconductor die is coupled to the top surface of the controller die using a plurality of solder balls.

18. The method according to claim 17, the method further comprising initiating a reflow process to melt the plurality of solder balls.

19. The method according to claim 18, wherein the reflow process is initiated after the first semiconductor die is coupled to the top surface of the controller die.

20. The method according to claim 18, wherein the reflow process is a batch reflow process initiated after placing a second semiconductor die on a top surface of the first semiconductor die and after placing the first semiconductor die on the controller die.

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