Bipolar transistor and manufacturing method thereof

Abstract

The invention provides a bipolar transistor and a manufacturing method thereof.The bipolar transistor comprises an emitter region, a base region, a collector region, a first target groove, a second target groove, an emitter, a base and a collector, the emitter region, the base region and the collector region are sequentially arranged longitudinally, the base region is located on the collector region, the emitter region is located on the base region, and the collector region is located on the first target groove. Oxide is arranged on the side wall of the first target groove, polycrystalline silicon is deposited in the groove, the polycrystalline silicon at the bottom of the first target groove is in contact with the base region, the second target groove is arranged on one side of the first target groove, oxide is arranged on the side wall of the second target groove, and polycrystalline silicon is deposited in the groove. The polycrystalline silicon at the bottom of the second target groove is in contact with the collector region, the base electrode is arranged on the polycrystalline silicon on the surface of the first target groove, the collector electrode is arranged on the polycrystalline silicon on the surface of the second target groove, and the emitter electrode is arranged on the surface of the emitter region on the other side of the first target groove.

Description

Technical Field

[0001] The present application relates to the technical field of transistor manufacturing, and in particular to a bipolar transistor and a manufacturing method thereof. Background Art

[0002] Bipolar transistors (full name: bipolar junction transistor, BJT) are current control devices, and two carriers (electrons and holes) work at the same time. They are usually used in current amplification circuits, power amplification circuits and high-speed circuits. In the prior art, the plane size of conventional bipolar transistors etched on the plane of the wafer is large, resulting in low integration of bipolar transistors, and thus high cost of bipolar transistors. Summary of the invention

[0003] In view of this, the purpose of the present application is to at least provide a bipolar transistor and a manufacturing method thereof, by arranging the emitter region, the base region and the collector region in sequence in the longitudinal direction, and arranging the first target groove and the second target groove therein, the inner walls of the first target groove and the second target groove are provided with oxide and polysilicon is deposited in the grooves, and the bottom polysilicon of the first target groove directly contacts the base region, and the bottom polysilicon of the second target groove directly contacts the collector region, a base is arranged on the surface polysilicon of the first target groove, a collector is arranged on the surface polysilicon of the second target groove, a collector is arranged on the surface of the emitter region, and the base is arranged between the emitter and the collector, so as to increase the electron isolation capability by arranging the regions longitudinally and adding oxide in the first target groove and the second target groove, thereby solving the technical problem in the prior art that the electrodes of the bipolar transistor need to be separated by a certain distance in order to maintain the electron isolation capability, resulting in a large planar size and a low integration, thereby achieving the technical effect of reducing the planar size and increasing the integration.

[0004] This application mainly includes the following aspects: In a first aspect, an embodiment of the present application provides a bipolar transistor. The bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base, and a collector. Among them, the emitter region, the base region, and the collector region are arranged longitudinally in sequence, the base region is located above the collector region, the emitter region is located above the base region, the side wall of the first target trench is provided with an oxide and polysilicon is deposited in the trench, the polysilicon at the bottom of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the side wall of the second target trench is provided with an oxide and polysilicon is deposited in the trench, the polysilicon at the bottom of the second target trench is in contact with the collector region, the base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench.

[0005] Optionally, the bipolar transistor further includes a gate and a third target trench. The gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages. Among them, the third target trench is provided on the other side of the first target trench, the side wall and the bottom of the third target trench are both provided with an oxide and polysilicon is deposited in the trench, the gate is provided on the polysilicon on the surface of the third target trench, and the emitter is provided between the gate and the base.

[0006] Second aspect, an embodiment of the present application further provides a method for manufacturing a bipolar transistor, which is used to manufacture the bipolar transistor as described in the first aspect or any possible implementation manner of the first aspect above. Wherein, the method includes: etching a first initial trench on an initial substrate, and depositing an oxide in the first initial trench, the initial substrate includes a collector region and a base region located above the collector region, and the bottom of the first initial trench is located in the base region; after etching and removing the oxide at the bottom of the first initial trench, filling the trench with polysilicon deposition to obtain a first target trench corresponding to the first initial trench; etching a second initial trench on one side of the first target trench, and depositing an oxide in the second initial trench, the bottom of the second initial trench is in the collector region, and one side of the first target trench is located in a transistor arrangement direction perpendicular to the etching direction; after etching and removing the oxide at the bottom of the second initial trench, filling the trench with polysilicon deposition to obtain a second target trench corresponding to the second initial trench; forming an emitter region on the surface of the base region after generating the target trenches, and the emitter region does not cover each target trench; forming a base electrode on the polysilicon on the surface of the first target trench, forming a collector electrode on the polysilicon on the surface of the second target trench, and forming an emitter electrode on the emitter region on the other side of the first target trench, so as to realize the preparation of the bipolar transistor.

[0007] Optionally, the method further includes: etching the second initial trench and a third initial trench on both sides of the first target trench simultaneously, and depositing an oxide in the third initial trench, the bottom of the third initial trench is in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench; filling the trench with polysilicon deposition to obtain a third target trench corresponding to the third initial trench; forming a gate electrode on the polysilicon on the surface of the third target trench, and the gate electrode is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

[0008] Optionally, the initial substrate is formed in the following manner: forming a collector region on a P-type silicon substrate; after forming a P-type silicon epitaxial layer on the collector region by epitaxial growth, forming a base region on the P-type silicon epitaxial layer to obtain the initial substrate.

[0009] Optionally, after filling the trench with polysilicon deposition to obtain a first target trench corresponding to the first initial trench, the method further includes: removing the oxide and polysilicon outside the first target trench, so that the part of the surface of the initial substrate except the first target trench is the surface of the base region.

[0010] Optionally, before forming the emitter region on the surface of the base region after generating the target trench, the method further includes: removing the oxide and polysilicon outside the second target trench and the third target trench, so that the portion of the surface of the initial substrate other than each target trench is the surface of the base region.

[0011] Optionally, the emitter region, the collector region, and the base region are respectively obtained by performing photolithography and ion implantation corresponding to the type of the bipolar transistor.

[0012] Optionally, for each initial trench, the top width of the initial trench is greater than or equal to the bottom width, and the angle between the side of the trench and the top plane of the trench is limited within a preset angle range. The thickness of the oxide deposited in the initial trench is limited to a thickness that does not fill the trench. The side of the trench is used to indicate the side formed by connecting the top and the bottom on the same side; and / or, the depths of the second initial trench and the third initial trench are the same.

[0013] Optionally, the method further includes: forming an interlayer dielectric layer on the emitter region after forming the base electrode, the collector electrode, the emitter electrode, and the gate electrode, and performing polishing.

[0014] A bipolar transistor and a manufacturing method thereof provided by an embodiment of the present application. The bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base, and a collector. Among them, the emitter region, the base region, and the collector region are arranged longitudinally in sequence. The base region is located above the collector region, the emitter region is located above the base region. The side wall of the first target trench is provided with an oxide and polysilicon is deposited in the trench. The polysilicon at the bottom of the first target trench contacts the base region. The second target trench is arranged on one side of the first target trench. The side wall of the second target trench is provided with an oxide and polysilicon is deposited in the trench. The polysilicon at the bottom of the second target trench contacts the collector region. The base is arranged on the polysilicon on the surface of the first target trench. The collector is arranged on the polysilicon on the surface of the second target trench. The emitter is arranged on the surface of the emitter region on the other side of the first target trench. By arranging the emitter region, the base region, and the collector region longitudinally in sequence, and providing the first target trench and the second target trench thereon. The inner walls of the first target trench and the second target trench are both provided with oxides and polysilicon is deposited in the trenches. Moreover, the polysilicon at the bottom of the first target trench directly contacts the base region, and the polysilicon at the bottom of the second target trench directly contacts the collector region. The base is arranged on the polysilicon on the surface of the first target trench, the collector is arranged on the polysilicon on the surface of the second target trench, the emitter is arranged on the surface of the emitter region, and the base is arranged between the emitter and the collector, so as to increase the electron isolation ability by arranging the regions longitudinally and increasing the oxides in both the first target trench and the second target trench, and solve the technical problem in the prior art that in order to maintain the electron isolation ability, a certain distance needs to be set between the electrodes of the bipolar transistor, resulting in a large planar size and low integration. The technical effect of reducing the planar size and increasing the integration is achieved.

[0015] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0017] Figure 1 The flowchart showing a manufacturing method of a bipolar transistor provided by an embodiment of the present application is shown.

[0018] Figure 2Shows a schematic diagram of the initial substrate provided by the embodiments of the present application.

[0019] Figure 3 Shows a schematic diagram of the first initial trench provided by the embodiments of the present application.

[0020] Figure 4 Shows a schematic diagram of the target trench provided by the embodiments of the present application.

[0021] Figure 5 Shows a schematic diagram of the emitter region provided by the embodiments of the present application.

[0022] Figure 6 Shows a schematic diagram of the bipolar transistor provided by the embodiments of the present application.

[0023] Figure 7 Shows a schematic diagram of the electric field strength of the bipolar transistor provided by the embodiments of the present application.

[0024] Figure 8 Shows a schematic diagram of the electric potential of the bipolar transistor provided by the embodiments of the present application.

[0025] Figure 9 Shows a schematic diagram of the current density of the bipolar transistor provided by the embodiments of the present application.

[0026] Figure 10 Shows a graph of the relationship between the base current and the collector current of the bipolar transistor provided by the embodiments of the present application. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the accompanying drawings in the present application are only for the purposes of illustration and description, and are not used to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to actual scale. The flowcharts used in the present application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and the steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of the present application.

[0028] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. Generally, the components of the embodiments of the present application described and illustrated in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0029] The BCD process (Bipolar-CMOS-DMOS) is a monolithic integrated circuit manufacturing process that combines bipolar transistors, CMOS (complementary metal-oxide semiconductor), and DMOS (double-diffused metal-oxide semiconductor) on a single chip. In the prior art, due to the relatively simple manufacturing process of bipolar transistor process technology, low manufacturing cost, and high yield, and in terms of circuit performance, it has advantages such as high speed, high transconductance, low noise, high analog accuracy, and strong current driving ability, and is thus favored. Bipolar transistors are current control devices, and both carriers (electrons and holes) act simultaneously. They are usually applied to current amplification circuits, power amplification circuits, and high-speed circuits. However, currently, the planar size of conventional bipolar transistors is relatively large and the integration degree is low, which affects the manufacturing cost.

[0030] Based on this, the embodiments of the present application provide a bipolar transistor and a manufacturing method thereof. By arranging the emitter region, base region, and collector region longitudinally in sequence, and setting a first target trench and a second target trench thereon, oxides are provided on the inner walls of the first target trench and the second target trench, and polysilicon is deposited in the trenches. Moreover, the polysilicon at the bottom of the first target trench directly contacts the base region, the polysilicon at the bottom of the second target trench directly contacts the collector region, a base electrode is provided on the polysilicon on the surface of the first target trench, a collector electrode is provided on the polysilicon on the surface of the second target trench, a collector electrode is provided on the surface of the emitter region, and the base electrode is arranged between the emitter electrode and the collector electrode. By longitudinally arranging each region and increasing the oxide in both the first target trench and the second target trench, the ability to isolate electrons is increased, solving the technical problem in the prior art that due to the need to keep a certain distance between the electrodes of the bipolar transistor to maintain the electron isolation ability, the planar size is relatively large and the integration degree is low, and achieving the technical effect of reducing the planar size and increasing the integration degree, specifically as follows: Please refer to Figure 1 , Figure 1 which is a flowchart of a manufacturing method of a bipolar transistor provided by an embodiment of the present application. As Figure 1 shown, the manufacturing method of the bipolar transistor provided by the embodiment of the present application includes the following steps: S101: Etch a first initial trench in the initial substrate, and deposit an oxide in the first initial trench.

[0031] Wherein, the initial substrate includes a collector region and a base region located above the collector region, and the bottom of the first initial trench is located in the base region.

[0032] Specifically, the initial substrate is formed in the following manner: form a collector region on a P-type silicon substrate; after forming a P-type silicon epitaxial layer on the collector region by epitaxial growth, form a base region on the P-type silicon epitaxial layer to obtain the initial substrate.

[0033] Wherein, the emitter region, the collector region, and the base region are respectively obtained by performing photolithography and ion implantation corresponding to the type of the bipolar transistor.

[0034] That is to say, perform photolithography and ion implantation corresponding to the type of the bipolar transistor to obtain the emitter region, the collector region, and the base region. The types of bipolar transistors include NPN-type bipolar transistors and PNP-type bipolar transistors. That is to say, perform photolithography on the emitter region, the collector region, and the base region of the NPN-type bipolar transistor respectively, and perform ion implantation according to the corresponding doping type and concentration. Perform photolithography on the emitter region, the collector region, and the base region of the PNP-type bipolar transistor respectively, and perform ion implantation according to the corresponding doping type and concentration. The ions, doping types, and concentrations of ion implantation of the NPN-type bipolar transistor and the PNP-type bipolar transistor in the same region are all different, that is, the ion implantation performed when generating the emitter region of the NPN-type bipolar transistor and the PNP-type bipolar transistor is different.

[0035] Exemplarily, please refer to Figure 2 , Figure 2 , which is a schematic diagram of the initial substrate provided by the embodiment of the present application. As Figure 2 shown, perform photolithography and ion implantation on the upper part of the P-type silicon substrate, so as to generate a collector region in the upper part of the P-type silicon substrate; form a P-type silicon epitaxial layer on the collector region through an epitaxial growth (Epitaxial Growth, EPI) process, or in other words, the P-type silicon epitaxial layer is equivalent to the part generated on the P-type silicon substrate, and the thickness h of the P-type silicon epitaxial layer is 0.5 to 20 micrometers (μm); perform photolithography and ion implantation on the upper part of the P-type silicon epitaxial layer to generate a base region on the P-type silicon epitaxial layer, and it can be selected to turn the entire P-type silicon epitaxial layer into a base region, so as to constitute the initial substrate.

[0036] Among them, the photolithography for generating the collector region can be middle ultraviolet lithography (MUV), deep ultraviolet lithography (DUV), etc., and the photolithography for generating the base region can also be middle ultraviolet lithography (MUV), deep ultraviolet lithography (DUV), etc. This application does not limit the specific method of photolithography, nor does it limit the specific method of ion implantation.

[0037] Exemplarily, if the bipolar transistor to be fabricated is an NPN bipolar transistor, a high-concentration doped donor impurity needs to be implanted to form an N-type semiconductor to obtain the emitter region, a low-concentration doped acceptor impurity needs to be implanted to form a P-type semiconductor to obtain the base region, and a medium-concentration doped (between the concentrations of the emitter region and the base region) donor impurity needs to be implanted to form an N-type semiconductor to obtain the collector region. If the bipolar transistor to be fabricated is a PNP bipolar transistor, a high-concentration doped acceptor impurity needs to be implanted to form a P-type semiconductor to obtain the emitter region, a low-concentration doped donor impurity needs to be implanted to form an N-type semiconductor to obtain the base region, and a medium-concentration doped (between the concentrations of the emitter region and the base region) acceptor impurity needs to be implanted to form a P-type semiconductor to obtain the collector region. This application does not limit the types of donor impurities and acceptor impurities corresponding to the actual ion implantation.

[0038] Furthermore, the upper part of the P-type silicon epitaxial layer includes the base region and the emitter region, and the emitter region is located above the base region, or in other words, both the base region and the emitter region are in the P-type silicon epitaxial layer. The upper part on the P-type silicon substrate is the collector region, or in other words, the collector region is in the P-type silicon substrate.

[0039] Furthermore, after generating the initial substrate, a first initial trench is obtained by etching on the initial substrate, and the bottom of the first initial trench is located in the base region. That is to say, since the base region in the initial substrate is above the collector region, when the bottom of the first initial trench is in the base region, it means that the first initial trench is only etched to the base region and not to the collector region, and the whole of the first initial trench is in the base region.

[0040] Exemplarily, please refer to Figure 3 , Figure 3 which is a schematic diagram of the first initial trench provided by the embodiment of this application. As Figure 3As shown, the side view of the first initial trench is trapezoidal. The side view refers to the cross-section obtained by cutting the initial substrate along the etching direction on the surface of the initial substrate. The top width a1 of the first initial trench is greater than or equal to the bottom width a2, and the angle α between the trench side B and the trench top plane A is limited within a preset angle range. The trench side is used to indicate the side formed by connecting the top and the bottom on the same side. And the depth b1 of the first initial trench is less than or equal to the depth of the base region, so that the complete first initial trench is located within the base region.

[0041] Exemplarily, the angle α between the trench side and the trench top plane should be non-obtuse, that is, the preset angle range is greater than or equal to 70° and less than or equal to 90°. When the angle α between the trench side and the trench top plane is 90°, the top width a1 of the first initial trench is equal to the bottom width a2, and the side view of the first initial trench should be rectangular. And dry etching (Dry Etch) is used to etch out the first initial trench. Since the etching is achieved from top to bottom, the top width a1 of the trench must be greater than or equal to the bottom width a2. The depth of the first initial trench should be less than the depth of the P-type silicon epitaxial layer and greater than the depth of the emitter region, and the depth of the first initial trench does not reach the collector region. Exemplarily, the critical dimension (CD) of the first initial trench is 0.3 to 3 micrometers (μm), or the top width a1 of the first initial trench is 0.3 to 3 micrometers (μm), and the depth b1 of the first initial trench is greater than 0.5 micrometers (μm).

[0042] Furthermore, after etching out the first initial trench, an oxide is deposited in the first initial trench. Among them, the oxide can be deposited in the first initial trench by chemical vapor deposition (Chemical Vapor Deposition, CVD) or furnace tube process. The thickness of the oxide should be limited to not fill the thickness of the first initial trench, generally 0.01 to 1 micrometer (μm), and the oxide can be selected as silicon dioxide SiO2.

[0043] Return Figure 1 , S102: After etching and removing the bottom oxide of the first initial trench, the trench is filled with polysilicon deposition to obtain the first target trench corresponding to the first initial trench.

[0044] That is to say, after depositing the oxide in the first initial trench, the bottom oxide of the first initial trench is removed by etching, and after removing the bottom oxide, polysilicon deposition is used to fill the trench to obtain the first target trench.

[0045] Exemplarily, dry etch is used to remove the bottom oxide of the first initial trench, and then polysilicon (poly) is deposited in the trench through a furnace tube process to fill the trench, thereby obtaining the first target trench.

[0046] After filling the trench with polysilicon deposition to obtain the first target trench corresponding to the first initial trench, the method further includes: removing the oxide and polysilicon outside the first target trench, so that the portion of the surface of the initial substrate other than the first target trench is the surface of the base region.

[0047] That is to say, after generating the first target trench, it is necessary to perform oxide etch back or chemical mechanical polishing (CMP), or a combination of both processes, to remove the excess oxide and polysilicon outside the trench to planarize the surface of the initial substrate, so that the top surface of the first target trench and the remaining base region are shown on the surface of the initial substrate.

[0048] S103: Etch a second initial trench on one side of the first target trench, and deposit an oxide in the second initial trench.

[0049] Wherein, the bottom of the second initial trench is located in the collector region, and one side of the first target trench is located in a transistor arrangement direction perpendicular to the etching direction.

[0050] That is to say, the bipolar transistors on the wafer are arranged in a matrix arrangement. The first target trench should be located in the row arrangement direction or the column arrangement direction of the matrix arrangement of the second initial trench. And since the bottom of the second initial trench is located in the collector region, the depth of the second initial trench is greater than the depth of the first initial trench, so that the side surface of the second initial trench covers the base region, the P-type silicon epitaxial layer and the collector region, and the bottom of the second initial trench is located in the collector region without etching into the P-type silicon substrate.

[0051] Exemplarily, dry etch is used to etch the second initial trench. The side view of the second initial trench can also be trapezoidal. The top width of the second initial trench is greater than or equal to the bottom width, and the angle between the trench side and the trench top plane is limited within a preset angle range. The angle between the trench side and the trench top plane of the second initial trench should be non-obtuse, that is, the preset angle range is greater than or equal to 70° and less than or equal to 90°. When the angle between the trench side and the trench top plane of the second initial trench is 90°, the top width of the second initial trench is equal to the bottom width, and the side view of the second initial trench should be rectangular.

[0052] Furthermore, an oxide is deposited in the trench after the second initial trench etching. Among them, the oxide can be deposited in the first initial trench by means of Chemical Vapor Deposition (CVD) or a furnace tube process. The thickness of the oxide should be limited to a thickness that does not fill the first initial trench, generally 0.01 to 1 micrometer (μm). The oxide can be selected as silicon dioxide SiO2.

[0053] S104: After etching and removing the bottom oxide of the second initial trench, the trench is filled with polysilicon deposition to obtain the second target trench corresponding to the second initial trench.

[0054] Furthermore, in the second initial trench after the oxide deposition, dry etch is used to remove the bottom oxide of the second initial trench, and then polysilicon poly is deposited in the trench by a furnace tube process to fill the trench to obtain the second target trench.

[0055] Specifically, the method further includes: etching the second initial trench and the third initial trench on both sides of the first target trench simultaneously, and depositing an oxide in the third initial trench. The bottom of the third initial trench is in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench; filling the trench with polysilicon deposition to obtain the third target trench corresponding to the third initial trench; forming a gate on the polysilicon on the surface of the third target trench, and the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

[0056] That is to say, after obtaining the first target trench, the second initial trench and the third initial trench can be etched on both sides of the first target trench respectively, and both the second initial trench and the third initial trench are in the row arrangement direction or the column arrangement direction of the matrix arrangement. That is, the second initial trench is located on one side of the first target trench in the row arrangement direction, the third initial trench is located on the other side of the first target trench in the row arrangement direction, or the second initial trench is located on one side of the first target trench in the column arrangement direction, and the third initial trench is located on the other side of the first target trench in the column arrangement direction.

[0057] That is to say, since dry etch is used to etch the second initial trench and the third initial channel simultaneously, and the bottoms of both the second initial trench and the third initial trench are in the collector region, furthermore, the depths of the third initial trench and the second initial trench can be the same.

[0058] Among them, the top width of the third initial trench is greater than or equal to the bottom width, and the angle between the trench sidewall and the trench top plane is limited within a preset angle range. The angle between the trench sidewall and the trench top plane of the third initial trench should be non-obtuse, that is, the preset angle range is greater than or equal to 70° and less than or equal to 90°. When the angle between the trench sidewall and the trench top plane of the third initial trench is 90°, the top width of the third initial trench is equal to the bottom width, and the side view of the third initial trench should be rectangular.

[0059] Exemplarily, the critical dimension of the third initial trench is smaller than that of the second initial trench, or rather, the top width of the third initial trench is smaller than the top width of the second initial trench. Further, after etching the second initial trench and the third initial trench, oxides are deposited in the second initial trench and the third initial trench simultaneously by means of chemical vapor deposition or furnace tube process. And because the critical dimension of the third initial trench is smaller than that of the second initial trench, further, it is necessary to prevent the oxides from filling the third initial trench during the deposition process. Therefore, the thickness of the oxides deposited in the second initial trench and the third initial trench respectively should be limited to a thickness that does not fill the trenches.

[0060] Exemplarily, after depositing oxides in the second initial trench and the third initial trench simultaneously by means of chemical vapor deposition or furnace tube process, dry etching can be performed on the oxides deposited in the second initial trench and the third initial trench to remove the bottom oxides of the second initial trench. Since the top width of the third initial trench is smaller than the top width of the second initial trench, the bottom oxides of the third initial trench will not be completely removed. Or rather, after removing the oxides, the bottom of the second initial trench is exposed as the collector region, and the bottom of the third initial trench is the deposited oxides.

[0061] That is to say, the second initial trench and the third initial trench are etched simultaneously, and the top width of the second initial trench is maintained to be greater than that of the third initial trench. Then, oxides are deposited in the second initial trench and the third initial trench simultaneously, and it should be ensured that the second initial trench and the third initial trench are not filled with oxides. Then, after depositing the oxides, the second initial trench and the third initial trench are etched to remove the bottom oxides of the second initial trench and expose the collector region at the bottom of the second initial trench. The bottom oxides of the third initial trench are not completely removed. Then, polysilicon is deposited to fill the trenches to obtain the second target trench corresponding to the second initial trench and the third target trench corresponding to the third initial trench.

[0062] Furthermore, by simultaneously forming the second initial trench and the third initial trench at the same time, and by simultaneously depositing oxides on the second initial trench and the third initial trench, the process cost can be reduced. Moreover, since oxides are deposited on the sidewalls of both the first target trench and the second target trench to increase the ability to isolate electrons, the distance between the first target trench and the second target trench can be reduced, and the distances between the base and the emitter and between the base and the collector in the subsequent structure can also be reduced, thereby increasing the integration density of bipolar transistors.

[0063] Specifically, before forming the emitter region on the surface of the base region after generating the target trenches, the method further includes: removing the oxides and polysilicon outside the second target trench and the third target trench, so that the portion of the surface of the initial substrate other than each target trench is the surface of the base region.

[0064] That is to say, after generating the second target trench and the third target trench, through oxide etchback or chemical mechanical polishing (CMP), or a combination of both processes, the excess oxides and polysilicon outside the second target trench and the third target trench are removed to planarize the surface of the initial substrate, so that the top surfaces of the first target trench, the second target trench, the third target trench, and the remaining base region are exposed on the surface of the initial substrate.

[0065] Exemplarily, please refer to Figure 4 , Figure 4 which is a schematic diagram of the target trenches provided by the embodiments of the present application. As Figure 4 shown, the first target trench is connected to the base region through polysilicon, the second target trench is connected to the collector region through polysilicon, the structure of the first target trench along the setting direction of the target trenches on both sides is oxide, polysilicon, and oxide, that is, the lateral structure of the first target trench is oxide, polysilicon, and oxide, and the lateral structure of the second target trench is also oxide, polysilicon, and oxide. The third target trench is connected to the collector region through an oxide, and the lateral structure of the third target trench is also oxide, polysilicon, and oxide. Since electrodes of bipolar transistors need to be provided in the first target trench and the second target trench subsequently, and since oxides are non-conductive, the structure of oxide, polysilicon, and oxide is used to increase the ability to isolate electrons. Therefore, there is no need to set a relatively large lateral distance m between the first target trench and the second target trench to maintain a certain electron isolation ability, and the lateral distance m between the first target trench and the second target trench can be reduced, thereby reducing the planar size of the bipolar transistor and increasing the number of bipolar transistors etched on the same wafer, and increasing the integration density.

[0066] S105: Form an emitter region on the surface of the base region after generating the target trenches, and the emitter region does not cover each target trench.

[0067] Exemplarily, refer to Figure 5 , Figure 5 which is a schematic diagram of the emitter region provided by the embodiments of the present application. As Figure 5 shown, the upper part of the base region is lithographed according to lithography methods such as Middle Ultraviolet Lithography (MUV) and Deep Ultraviolet Lithography (DUV), and ion implantation is performed to generate the emitter region. Furthermore, the bipolar transistor prepared in the present application is a vertical bipolar transistor, and the emitter region, the base region, and the collector region are arranged longitudinally.

[0068] S106: Form a base on the polysilicon on the surface of the first target trench, form a collector on the polysilicon on the surface of the second target trench, and form an emitter on the emitter region on the other side of the first target trench to implement the preparation of the bipolar transistor.

[0069] Furthermore, by generating each electrode of the bipolar transistor on the polysilicon on the surface of the target trench, namely the base, the collector, and the emitter, the bipolar transistor is prepared. In addition, a gate is formed on the polysilicon on the surface of the third target trench to increase the electrodes of the bipolar transistor. By connecting the gate to different external voltages, the current amplification factor of the bipolar transistor is changed, thereby realizing the function of regulating the current amplification factor of the bipolar transistor.

[0070] Furthermore, when the bipolar transistor is in forward amplification, the emitter junction is forward-biased and the collector junction is reverse-biased. When the bipolar transistor is an NPN-type bipolar transistor, due to the forward bias of the emitter junction, electrons in the emitter region are injected into the base region, forming an accumulation of non-equilibrium minority carriers in the P-type base region and forming a certain electron concentration gradient. Due to the existence of the electron concentration gradient, electrons diffuse towards the collector junction. Due to the reverse bias of the collector junction, the electrons diffusing to the boundary of the space charge region of the collector junction are accelerated by the electric field and drift towards the collector region, becoming the main part of the collector current. Due to the existence of the gate, the base region semiconductor can be strongly inverted, and the electron concentration in the inversion layer is high enough to form an N-type conductive channel on one side of the gate. This conductive channel can connect the two N-type semiconductors of the emitter region and the collector region, and electrons will flow from the emitter region to the collector region under the action of the electric field, enhancing the collector current, so that the current amplification factor of the bipolar transistor can be greatly enhanced. At the same time, the current amplification factor of the bipolar transistor can be regulated in real time through the gate voltage, achieving controllable current amplification.

[0071] Exemplarily, the effects on the bipolar transistor when different voltages are applied to the gate can be reflected by determining the current amplification factor, the peak collector current, and the peak base current. Table 1 is a schematic table of the various parameters of the bipolar transistor when different voltages are applied to the gate.

[0072] Table 1:

[0073] Exemplarily, please refer to Figure 6 , Figure 6 which is a schematic diagram of the bipolar transistor provided by the embodiment of the present application. As Figure 6 shown, a base, a collector, an emitter, and a gate are formed above the emitter region, and the emitter is located between the gate and the base in the lateral direction. After forming the base, the collector, the emitter, and the gate, a dielectric layer needs to be deposited on the emitter region. The dielectric layer may include at least one of the following: silicon nitride, silicon oxynitride, or phosphorus-doped silicon glass. Then, chemical mechanical polishing (CMP) is performed on the deposited dielectric layer to form an interlayer dielectric layer. Then, contact holes are formed on the base, the collector, the emitter, and the gate of the interlayer dielectric layer through photolithography and etching processes to fabricate a bipolar transistor with an additional gate. The contact holes can be filled with titanium (Ti), titanium nitride (TiN), and tungsten (W) to facilitate the connection of the metal in the subsequent process.

[0074] Based on the same inventive concept, the embodiment of the present application also provides a bipolar transistor corresponding to the manufacturing method of the bipolar transistor provided in the above embodiment. Since the principle of solving problems of the bipolar transistor in the embodiment of the present application is similar to that of the manufacturing method in the above embodiment of the present application, the implementation of the bipolar transistor can refer to the implementation of the method, and the repeated parts will not be described again.

[0075] Exemplarily, an embodiment of the present application further provides a bipolar transistor, which includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base, and a collector. Among them, the emitter region, the base region, and the collector region are arranged longitudinally in sequence, the base region is located above the collector region, the emitter region is located above the base region, the side wall of the first target trench is provided with an oxide and polysilicon is deposited in the trench, the polysilicon at the bottom of the first target trench is in contact with the base region, the second target trench is arranged on one side of the first target trench, the side wall of the second target trench is provided with an oxide and polysilicon is deposited in the trench, the polysilicon at the bottom of the second target trench is in contact with the collector region, the base is arranged on the polysilicon on the surface of the first target trench, the collector is arranged on the polysilicon on the surface of the second target trench, and the emitter is arranged on the surface of the emitter region on the other side of the first target trench.

[0076] Among them, the bipolar transistor further includes a gate and a third target trench. The gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages. Among them, the third target trench is arranged on the other side of the first target trench, the side wall and the bottom of the third target trench are both provided with an oxide and polysilicon is deposited in the trench, the gate is arranged on the polysilicon on the surface of the third target trench, and the emitter is arranged between the gate and the base.

[0077] That is to say, the polysilicon at the bottom of the first target trench is in contact with the P-type silicon epitaxial layer, the polysilicon at the bottom of the second target trench is in contact with the P-type silicon substrate, the longitudinal structure of the third target trench is polysilicon and an oxide layer, and the oxide layer at the bottom of the third target trench is in contact with the collector region, that is, the oxide layer at the bottom of the third target trench is in contact with the P-type silicon substrate. Exemplarily, the depth of the second target trench is the same as the depth of the third target trench.

[0078] Exemplarily, the bipolar transistor includes an NPN bipolar transistor and a PNP bipolar transistor. Moreover, the bipolar transistor provided in the present application is generally integrated in a power management chip.

[0079] Exemplarily, please refer to Figure 7 , Figure 7 , which is a schematic diagram of the electric field strength of the bipolar transistor provided by the embodiment of the present application. Figure 7 It reflects the electric field strength at each position in the cross-section in the lateral direction of the bipolar transistor. Please refer to Figure 8 , Figure 8 , which is a schematic diagram of the electric potential of the bipolar transistor provided by the embodiment of the present application. Figure 8 It reflects the electric potential at each position in the cross-section in the lateral direction of the bipolar transistor. Please refer toFigure 9 , Figure 9 is a schematic diagram of the current density of the bipolar transistor provided by the embodiment of the present application. Figure 9 It reflects the current density at each position in the cross-section in the lateral direction of the bipolar transistor. Please refer to Figure 10 , Figure 10 is a relationship curve graph of the base current and the collector current of the bipolar transistor provided by the embodiment of the present application. Figure 10 It reflects the collector current corresponding to different base currents of the bipolar transistor, and the unit is ampere (A). Through Figures 7 to 10 it reflects the electrical characteristics of the bipolar transistor prepared by the present application.

[0080] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems and devices described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated here. In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0082] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0083] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A bipolar transistor, characterized in that, The bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base, and a collector. Among them, the emitter region, the base region, and the collector region are arranged longitudinally in sequence. The base region is located above the collector region, and the emitter region is located above the base region. The sidewalls of the first target trench are provided with an oxide and polysilicon is deposited in the trench. The polysilicon at the bottom of the first target trench contacts the base region. The second target trench is provided on one side of the first target trench. The sidewalls of the second target trench are provided with an oxide and polysilicon is deposited in the trench. The polysilicon at the bottom of the second target trench contacts the collector region. The base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench.

2. The bipolar transistor according to claim 1, characterized in that, The bipolar transistor further includes a gate and a third target trench. The gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages. Among them, the third target trench is provided on the other side of the first target trench. The sidewalls and the bottom of the third target trench are both provided with an oxide and polysilicon is deposited in the trench. The gate is provided on the polysilicon on the surface of the third target trench, and the emitter is provided between the gate and the base.

3. A method for manufacturing a bipolar transistor, characterized in that, The method is used to manufacture the bipolar transistor as described in claim 1 or 2. Among them, the method includes: Etch a first initial trench on an initial substrate and deposit an oxide in the first initial trench. The initial substrate includes a collector region and a base region located above the collector region. The bottom of the first initial trench is located in the base region. After etching and removing the oxide at the bottom of the first initial trench, fill the trench with polysilicon deposition to obtain a first target trench corresponding to the first initial trench. Etch a second initial trench on one side of the first target trench and deposit an oxide in the second initial trench. The bottom of the second initial trench is in the collector region. One side of the first target trench is in a transistor arrangement direction perpendicular to the etching direction. After etching and removing the oxide at the bottom of the second initial trench, fill the trench with polysilicon deposition to obtain a second target trench corresponding to the second initial trench. Form an emitter region on the surface of the base region after generating the target trenches, and the emitter region does not cover each target trench. Form a base on the polysilicon on the surface of the first target trench, form a collector on the polysilicon on the surface of the second target trench, and form an emitter on the emitter region on the other side of the first target trench to achieve the preparation of the bipolar transistor.

4. The method according to claim 3, wherein The method further includes: Etch the second initial trench and the third initial trench on both sides of the first target trench simultaneously, and deposit an oxide in the third initial trench. The bottom of the third initial trench is in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench. The third target trench corresponding to the third initial trench is obtained by filling the trench with polysilicon deposition; A gate is formed on the polysilicon on the surface of the third target trench, and the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

5. The method according to claim 3, wherein The initial substrate is formed by the following method: A collector region is formed on a P-type silicon substrate; After a P-type silicon epitaxial layer is formed by epitaxial growth on the collector region, a base region is formed on the P-type silicon epitaxial layer to obtain the initial substrate.

6. The method according to claim 3, characterized in that, After the first target trench corresponding to the first initial trench is obtained by filling the trench with polysilicon deposition, the method further includes: Removing the oxide and polysilicon outside the first target trench, so that the portion of the surface of the initial substrate other than the first target trench is the surface of the base region.

7. The method according to claim 4, characterized in that, Before forming the emitter region on the surface of the base region after generating the target trench, the method further includes: Removing the oxide and polysilicon outside the second target trench and the third target trench, so that the portion of the surface of the initial substrate other than each target trench is the surface of the base region.

8. The method according to claim 3 or 4, characterized in that The emitter region, the collector region, and the base region are respectively obtained by corresponding photolithography and ion implantation according to the type of the bipolar transistor.

9. The method according to claim 4, wherein For each initial trench, the top width of the initial trench is greater than or equal to the bottom width, and the angle between the side of the trench and the top plane of the trench is limited within a preset angle range. The thickness of the oxide deposited in the initial trench is limited to a thickness that does not fill the trench. The side of the trench is used to indicate the side formed by connecting the top and the bottom on the same side; And / or, the second initial trench and the third initial trench have the same depth.

10. The method according to claim 4, wherein The method further includes: Forming an interlayer dielectric layer on the emitter region after forming the base, the collector, the emitter, and the gate, and performing polishing.

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