Power semiconductor device with auxiliary gate structure

Abstract

The invention relates to a power semiconductor device in GaN technology. The present disclosure proposes an integrated auxiliary (dual) gate terminal and pull-down network to achieve a normally-off (E-mode) GaN transistor with a threshold voltage above 2V, low gate leakage current, and enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device and a low voltage auxiliary GaN device, the high voltage GaN device having a gate (10) transistor connected to a source (12) of the integrated auxiliary low voltage GaN and a drain as an external high voltage drain terminal (9) and a source as an external source terminal (8), the low-voltage auxiliary GaN transistor has a gate (first auxiliary electrode 15) serving as an external gate terminal connected to the drain (second auxiliary electrode 16). In an embodiment, a pull-down network for turning off a high threshold voltage GaN transistor is formed from an additional auxiliary low voltage GaN transistor (34) and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.

Description

[0001] This application is a divisional application of the PCT international application PCT / EP2020 / 062710 with the invention title "Power semiconductor device with auxiliary gate structure" filed on May 7, 2020, entering the Chinese national phase patent application 202080034026.1. Technical Field

[0002] The present invention relates to a power semiconductor device, for example, to a heterostructure aluminum gallium nitride / gallium nitride (AlGaN / GaN) high electron mobility transistor (HEMT) or rectifier. Background Art

[0003] Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic devices (for example, DC-to-AC inverters for motor control, or DC-to-DC converters for switched-mode power supplies). Power semiconductor devices are typically used in a "commutation mode" (i.e., it is either on or off), and thus have a design optimized for such use.

[0004] Typically, the rated voltage of a power device (i.e., the potential difference that the device must withstand between its main terminals in the off state) exceeds 20V and conducts more than 100mA during the on state. More commonly, the ratings of power devices exceed 60V and more than 1A. These values make power devices very different from low-power devices, which operate at voltages below 5V and typical currents below 1mA, and more commonly in the µAs or sub-µAs range. Another difference between power devices and other types of devices such as low-power or RF is that they mainly operate with large signals and their behavior is similar to that of switches. Exceptions are found in high-voltage or power amplifiers using dedicated power transistors.

[0005] Silicon bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs) are common types of power semiconductor switching devices. Their application fields range from portable consumer electronics, household appliances, hybrid and electric vehicles, motor control and power supplies to radio frequency and microwave circuits and telecommunication systems.

[0006] Gallium nitride (GaN) is increasingly regarded as a very promising material for the field of power devices with the potential to increase power density, reduce on-resistance, and improve high-frequency response. The wide bandgap of this material (E g = 3.39 eV) results in a high critical electric field (E c= 3.3 MV / cm), if compared with a silicon-based device having the same breakdown voltage, this high critical electric field can lead to the design of a device with a shorter drift region and thus a lower on-state resistance [1]. The use of an AlGaN / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface, where the carriers can reach very high mobility (μ = 2000 cm 2 / (Vs)) values [1]. In addition, the piezoelectric polarization charges present at the AlGaN / GaN heterostructure result in a high electron density in the 2DEG layer (e.g., 1x10 13 cm -2 ). These characteristics allow the development of high electron mobility transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters [2], [3]. A large amount of research has focused on the development of power devices using AlGaN / GaN heterostructures.

[0007] However, when attempting to design normally-off devices rather than normally-on devices, the 2DEG inherently present at the AlGaN / GaN heterointerface poses challenges. Nevertheless, since normally-off transistors are preferred in most power electronics applications, several methods that can lead to enhancement-mode devices have been proposed, including the use of a metal-insulator-semiconductor structure [4], the use of fluorine treatment [5], a recessed gate structure [6], and the use of a p-type cap layer [7][8]. Due to the relative maturity and controllability of the pGaN layer epitaxial growth (compared to other technologies), the pGaN / AlGaN / GaN HEMT is considered the leading structure for commercialization.

[0008] Figure 1 The cross-section of the active region of a prior art pGaN HEMT is schematically shown. The device shown is a lateral three-terminal device having an AlGaN / GaN heterostructure epitaxially grown on a standard silicon wafer 4. Although there is a significant lattice mismatch between GaN and Si, the transition layer 3 is used to allow the growth of a high-quality GaN layer 2. Carbon p-type doping is typically added to the GaN layer [9]. Finally, a thin capping GaN layer 11 is usually added to form a gate with a magnesium (Mg) p-type doping density greater than 1x10 19 cm- 3 .

[0009] Typical pGaN gate devices have a threshold voltage of about 1.5 to 2V and a gate-open bias of about 8V. The threshold voltage and the gate-open voltage in enhancement-mode GaN devices are of great concern because if the threshold voltage is low, some problems may occur during operation, such as the device accidentally turning on when it should be off. Secondly, due to the non-insulated gate structure, gate turn-on can be a problem. Therefore, it is obvious that pGaN gate devices operate at gate voltages in the range of 2V to 8V, and preferably at gate voltages between 5V and 7V, to minimize the on-state resistance of the device while ensuring a low leakage voltage (below the open-circuit voltage) through the gate.

[0010] In prior art devices, there is a trade-off between the threshold voltage of the device, the carrier density in the 2DEG of the device, and the device on-state resistance. Previous studies have shown that for pGaN doping greater than 1x10 19 cm -3 , the threshold voltage does not change significantly due to the use of different gate metals or the thickness of the pGaN layer

[10] . Therefore, unlike their silicon counterparts

[12] , a narrow operating window (with a gate voltage in the range of 4V to 7V relative to the source) is specified for these devices

[11] . The lower boundary is defined by the gate bias required to fully form a channel (2DEG) under the gate (this is called the threshold voltage Vth), and the upper boundary is limited by the point at which the gate turns on and a significant current starts to flow through it.

[0011] Another area of interest for AlGaN / GaN HEMTs is their fast switching ability. Due to the higher critical electric field, for a given breakdown, the high mobility of carriers in the 2DEG and the shorter drift region result in a very low drift region charge Qgd. In addition, the device gate charge Qg is about an order of magnitude lower than that of corresponding prior art silicon devices

[11] ,

[12] . Therefore, GaN HEMTs can switch at much higher speeds than silicon MOSFETs. Although this is beneficial in many applications, due to the presence of parasitic components at both the device and circuit levels, it may lead to unexpected oscillations

[13] . To avoid oscillatory behavior, one possible solution proposed is to add an external gate resistance to the device to reduce the observed dV / dt and dI / dt rates

[13] .

[0012] In

[14] , an attempt was made to expand the operating window defined by the threshold voltage and the open-circuit of the pGaN / AlGaN junction by changing the composition of the gate metal. As discussed in

[10] , this attempt was unsuccessful, and

[10] showed that for pGaN doping greater than 1x10 19 cm -3 , the threshold voltage cannot be significantly changed by using different gate metals or by changing the thickness of the pGaN layer.

[0013] In

[16] , a technique for obtaining a higher Vth on the P-gate was achieved via the "Through-Recessed Regrown Gate (TRRG)" technique. This process technology is based on the complete removal of the AlGaN barrier layer and its subsequent regrowth by epitaxial regrowth. This shows that the threshold voltage is more stable at elevated temperatures, and it is possible to achieve a Vth of up to 2.3 V by controlling the thickness of the AlGaN layer. Although this is an interesting process technology for obtaining a stable threshold voltage, it does affect Ron when Vth > 2 V. In addition, the high-Vth solution proposed in

[16] does not address the oscillation problem related to Rg during the fast switching of high-voltage transistors, nor does it address the high gate leakage problem of the pGaN gate technology.

[0014] In

[17] , an integrated double-gate technology for achieving a high Vth (>2.8 V) was demonstrated. The double-gate technology proposed in

[17] is based on the integration of high-voltage normally-on (D-mode) and low-voltage normally-off (E-mode) GaN transistors. However, in this configuration, the two transistors are in series, so the total on-state resistance will be affected by the series contribution of the on-state resistance of the low-voltage device.

[0015] Other proposed double-gate technologies exist in the literature, and they are so named because they have a second gate electrode located above the gate passivation layer

[18] or buried in the heterostructure stack

[19] . These devices are mainly aimed at improving the dynamic performance of the transistor by alleviating the current collapse phenomenon. The current collapse phenomenon is actually a reduction in the current in the on-state when the device is repeatedly subjected to high voltage in the off-state.

[0016] In

[20] , a circuit configuration with a diode and a second gate electrode was attempted to increase the Vth of a normally-off (enhancement-mode - E-mode) GaN transistor. In this document, the diode is used as a voltage switch and is connected in series with the gate of the high-voltage GaN device. Devices implementing the voltage switch with transistors are also described. However, in this particular case, the drain terminal of the voltage-switching transistor is connected to the high-voltage drain terminal of the GaN device. The implication of this connection is that the driving device will have to maintain a high voltage in the blocking mode and is thus designed as a high-voltage transistor with a drift region longer than that of the low-voltage device. This device will therefore have an increased area consumption, and the reliability of this additional transistor must be considered. In addition, no upper boundary limit is mentioned in

[20] .

[0017] Resistive loads connected between the gate and source of a GaN HEMT or a power MOSFET are also generally known, and their objectives can be to reduce oscillations during high-voltage switching, protect the device from electrostatic discharge, and generally ensure robust operation. For example, in the datasheet of GaN system components

[21] , it is recommended to add a 3 kΩ resistor between the gate terminal (gate bus) and the source (or ground).

[0018] In US9882553B2 and US10411681B2, devices for expanding the operating window of III-V semiconductor devices are described.

[0019] In US10374591B2, a gate drive circuit for controlling the operation of a wide-bandgap semiconductor switch is described.

[0020] In US2020007119A1, a voltage regulation circuit implemented using GaN HEMT technology to provide a stable output voltage suitable for applications (such as a GaN power transistor gate driver and a low-voltage auxiliary power supply for GaN integrated circuits) is described. Summary of the Invention

[0021] The object of the present invention is to propose a solution for a p-gate GaN E-mode transistor that simultaneously results in the following characteristics: (i) a reduction in gate leakage current, (ii) an increase in threshold voltage, and (iii) an increase in the gate voltage operating window. The result of these three characteristics is (i) to avoid turn-on re-triggering during turn-off and limit oscillations under certain turn-off conditions where there is a high dV / dt rate, and (ii) to improve the switching performance of the overall configuration through the integrated pull-down network.

[0022] According to the present invention, we propose a GaN power device having a high threshold voltage, a very large gate voltage operating range with less or no risk of p-GaN junction open circuit, and the ability to have a switching behavior with no or reduced oscillations. The details of the present invention will be discussed considering but not limited to pGaN gate E-mode technology.

[0023] The GaN transistors utilizing the present disclosure are intended but not limited to applications in the medium and low voltage ranges. Devices with low voltage capabilities (<200V but above 20V) will be suitable for point-of-load applications, i.e., low voltage DC-DC converters for IT or consumer electronics applications. Such devices can also be used in linear electronics to improve efficiency. However, for applications such as power factor correction (PFC), uninterruptible power supplies (UPS), motor drives, and photovoltaic (PV) system inverters, there is a huge market potential in the 600V range. 600V GaN devices can also be used as chargers for hybrid electric vehicles (HEV) and / or electric vehicles (EV), which is a rapidly growing market. GaN transistors with a breakdown capability of up to 1.2kV and a rated power of up to 7.2kW can lead to the use of GaN transistors in EV and HEV converters and inverters, where high-frequency operation will allow for a reduction in system size, an important parameter when considering mobile systems. Ultimately, if the rated power is large enough, GaN transistors can find applications in wind turbines (1.7kV). Applications that recently require reliable operation in the MHz range (e.g., wireless charging in the fields of IT (mobile phones, laptops) and automotive (EV, HEV)) may be very suitable for the present disclosure. In addition, applications other than power conversion are also envisioned, such as class-D audio amplifiers.

[0024] Broadly speaking, the present disclosure relates to power semiconductor devices using GaN technology. The present disclosure proposes an integrated auxiliary gate terminal and a pull-down network to achieve normally-off (E-mode) GaN transistors with a threshold voltage higher than 2V, low gate leakage current, and potentially enhanced switching performance. The high-threshold voltage GaN transistor has a high-voltage active GaN device and an auxiliary GaN device (preferably a low-voltage device), where the high-voltage GaN device has a gate transistor with a gate connected to the source of the integrated auxiliary GaN, a drain as an external high-voltage drain terminal, and a source as an external source terminal, while the auxiliary GaN transistor has a gate (the first auxiliary electrode) serving as an external gate terminal connected to the drain (the second auxiliary electrode). In other embodiments, the pull-down network for turning off the high-threshold voltage GaN transistor is formed by a diode, a resistor, or a parallel connection of both in parallel with the auxiliary GaN transistor.

[0025] In other embodiments, the pull-down network for turning off the active (high-voltage) GaN transistor is formed by an additional auxiliary low-voltage GaN transistor and a resistive element connected in parallel or in series with the low-voltage auxiliary GaN transistor.

[0026] In other embodiments, the pull-down network for turning off the active (high-voltage) GaN transistor is formed by an active Miller clamp.

[0027] In other embodiments, the overvoltage protection circuit is formed by a resistor or resistive element and a low-voltage enhancement-mode (or depletion-mode) transistor to limit the maximum potential at the gate of the active (high-voltage) transistor.

[0028] In other embodiments, the overcurrent protection circuit is formed by a current-sensing resistor or resistive element and a low-voltage enhancement-mode (or active depletion-mode) transistor to act as protection against overcurrent events.

[0029] According to a second aspect of the present invention, there is provided a heterojunction (gallium nitride) chip having at least three terminals (a high-voltage terminal, a low-voltage terminal, and a control terminal) (also called or referred to as a GaN chip or a GaN power integrated circuit or a GaN smart device or a GaN high-voltage integrated circuit),

[0030] and comprising at least one high-voltage active GaN device (also referred to as a main power heterojunction transistor) having an internal gate (whose source and drain are respectively connected to the low-voltage and high-voltage terminals of the GaN chip), a pull-down circuit, an auxiliary gate circuit comprising at least one low-voltage heterojunction transistor, and a current control circuit, wherein:

[0031] The auxiliary gate circuit has a first connection to the internal gate of the at least one main power heterojunction transistor, a second connection to the control terminal, and at least one additional connection connecting the gate of the at least one low-voltage heterojunction transistor to the pull-down circuit;

[0032] The pull-down circuit has at least one connection to the current control circuit and at least one connection to the source terminal of the at least one main power heterojunction transistor;

[0033] The current control circuit has a connection to the control terminal

[0034] And wherein, the auxiliary gate partially controls the voltage and current levels entering the internal gate of the at least one main power heterojunction transistor, the current control circuit controls the current level entering the pull-down circuit, and in combination with the pull-down circuit design, determines the voltage level applied to the control terminal at which the pull-down circuit actively pulls down the gate voltage of the at least one low-voltage heterojunction transistor to clamp the voltage of the internal gate of the at least one main power heterojunction transistor.

[0035] The auxiliary gate block (circuit) integrated in the GaN chip is composed of auxiliary GaN transistors (preferably low-voltage devices), wherein the gate of the high-voltage active GaN device (main power heterojunction transistor) is connected to the source of the integrated auxiliary gallium nitride transistor, and the drain of the auxiliary GaN transistor is connected to the control terminal of the GaN chip.

[0036] The integrated current control block (circuit) is connected between the drain and gate terminals of the auxiliary GaN transistor.

[0037] An integrated pull-down circuit block (circuit) is connected between the gate terminal of the auxiliary GaN transistor and the source terminal of the high-voltage active GaN device.

[0038] The threshold voltage of the GaN chip (the potential applied to the control terminal of the GaN chip relative to the low-voltage terminal where the main power heterojunction transistor starts to conduct current) may be higher than the inherent threshold voltage of a single main power heterojunction transistor. When a voltage signal is applied to the control terminal of the GaN chip (also known as the external gate terminal), this can be achieved by an additional voltage drop across the integrated auxiliary gate block. Thus, the potential at the internal gate (also known as the active gate terminal) is lower than the potential applied to the control terminal of the GaN chip.

[0039] When the voltage signal at the external gate terminal (control terminal) increases linearly, the voltage drop across the auxiliary gate block (circuit) is non-linear.

[0040] The low gate leakage current of the high-voltage active GaN device (main power heterojunction transistor) is achieved by limiting the potential at the internal gate (active gate) terminal. This is achieved by allowing a voltage drop across the integrated auxiliary gate block. The limitation of the potential of the active gate terminal is defined by appropriately designing the current control block and the pull-down circuit block such that when the gate signal of the external gate terminal (control terminal of the GaN chip) increases beyond a certain level, the gate of the auxiliary gate transistor is pulled down. Thus, the gate voltage operation window of the GaN chip (i.e., the voltage operation window applied to the control terminal) is increased compared to that of a conventional GaN HEMT.

[0041] The maximum voltage signal that can be applied to the external gate of the device (control terminal of the GaN chip) can be designed to be above 10V (e.g., 20V), such that conventional silicon gate drivers and controllers can be used to drive the GaN chip.

[0042] In addition, the current control block (and other circuits) needs to be appropriately designed to balance fast turn-on, avoid overshoot at the active gate terminal (internal gate terminal) during turn-on, and low gate driver power consumption during the on-state operation of the device.

[0043] The integrated current control circuit (current control block) can be a resistive element or incorporate a resistive element. Alternatively, the current control circuit can be or include a current source. The current source can be composed of a low-voltage depletion-mode HEMT and a resistive element. The resistive element can be connected between the gate and source terminals of the low-voltage depletion-mode HEMT. The drain terminal of the depletion-mode HEMT is connected to the drain terminal of the auxiliary gate HEMT, and the gate terminal of the depletion-mode HEMT is connected to the gate terminal of the auxiliary gate HEMT.

[0044] In a similar embodiment, an RCL network may be included in parallel with a resistive element or a current source to improve the dynamic characteristics during device turn-on or turn-off transients.

[0045] The current control block may also include a circuit that generates an additional voltage drop. The current control block may also include a circuit that adapts the current in the current control block according to operating conditions (e.g., switch, on, or off conditions). Such a current adaptation circuit may include a depletion-mode HEMT or an enhancement-mode HEMT in series or in parallel with a resistive element in the current source.

[0046] In some embodiments, the integrated pull-down circuit (block) may be or include one or more HEMTs in parallel or in series. The gate potential of the pull-down HEMT is controlled to set the voltage drop across the pull-down HEMT, thereby setting the gate voltage of the auxiliary gate block and the voltage drop across the auxiliary gate block.

[0047] The pull-down circuit block may also include an element for compensating or reducing the effect of temperature on the voltage drop across the pull-down circuit block.

[0048] In another embodiment, the auxiliary gate may include a low-voltage depletion-mode transistor instead of a low-voltage enhancement-mode transistor. This embodiment may not be as effective in achieving an increased threshold voltage for the GaN chip, but may achieve an increased operating range by allowing an increase in the maximum allowable control signal (external gate signal) level. Since there is a channel in the depletion-mode transistor when the potential on the active gate is high and the potential on the external gate terminal is low, the GaN transistor can be used as part of the device turn-off network.

[0049] In other embodiments, some or all of the described functional blocks may be used together to add enhanced functionality.

[0050] Although the auxiliary GaN transistors are preferably low-voltage devices, since they are typically made in a symmetric (or similar) manner, the source and drain terminals may be interchanged. A low-voltage device refers to a device with a rated breakdown voltage typically below 20V and limited current capability (below 100mA). However, it should be understood that although this increases cost and complexity, the auxiliary gate may also be a high-power or high-voltage device.

[0051] Most embodiments according to the present disclosure described herein relate to an integrated auxiliary transistor, whereby the auxiliary transistor and the active transistor are fabricated on the same substrate (in the same chip). Although the integration of both may have several advantages (e.g., fewer pads, low area consumption, compact size, lower cost, and lower complexity), the auxiliary transistor may also be fabricated on a separate substrate and connected to the active transistor in a discrete or hybrid manner. The auxiliary transistor and the active transistor may be located side by side in the same package or module, or discretely connected on a board, and are not necessarily integrated in the same GaN chip.

[0052] This also applies to the other functional blocks described.

[0053] According to one aspect of the present invention, there is provided a heterojunction power device based on group-III nitride semiconductors, the heterojunction power device comprising:

[0054] An active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:

[0055] A first group-III nitride semiconductor region including a first heterojunction, the first heterojunction including an active two-dimensional carrier of a second conductivity type;

[0056] A first terminal operatively connected to the group-III nitride semiconductor region;

[0057] A second terminal laterally spaced from the first terminal and operatively connected to the group-III nitride semiconductor region;

[0058] An active gate region formed over the group-III nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal;

[0059] An auxiliary heterojunction transistor formed on the substrate or an additional substrate, the auxiliary heterojunction transistor comprising:

[0060] A second group-III nitride semiconductor region including a second heterojunction, the second heterojunction including an auxiliary two-dimensional carrier of a second conductivity type;

[0061] A first additional terminal operatively connected to the second group-III nitride semiconductor region;

[0062] A second additional terminal laterally spaced from the first additional terminal and operatively connected to the second group-III nitride semiconductor region;

[0063] An auxiliary gate region formed over the second group-III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;

[0064] Wherein, a first additional terminal is operatively connected to the auxiliary gate region, and wherein, a second additional terminal is operatively connected to the active gate region,

[0065] Wherein, the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein, the heterojunction power device further includes a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and wherein a first additional terminal of the first auxiliary heterojunction transistor is operatively connected to the source terminal of the second auxiliary heterojunction transistor, and the second additional terminal of the first auxiliary heterojunction transistor is operatively connected to the drain terminal of the second auxiliary heterojunction transistor,

[0066] Wherein, the auxiliary heterojunction transistor is configured to (or adding an auxiliary heterojunction transistor) cause an increase in the threshold voltage of the heterojunction power device and / or an increase in the operating voltage range of the first additional terminal.

[0067] Here, the term "operatively connected" means that the terminals are electrically connected. In other words, the first additional terminal is electrically connected to the auxiliary gate, and the second additional terminal is electrically connected to the active gate region. In addition, in one embodiment, the first terminal is the source terminal of the active transistor, and the second terminal is the drain terminal of the active transistor. On the other hand, the first additional terminal is the drain terminal of the auxiliary transistor, and the second additional terminal is the source terminal of the auxiliary transistor. In an embodiment, the connected first additional terminal and the auxiliary gate region form a high-voltage terminal (or form an external gate terminal), where a relatively higher voltage is applied compared to the second additional terminal. Therefore, the second additional terminal can be referred to as the low-voltage terminal of the auxiliary transistor. Here, the term "Group-III nitride semiconductor region" generally refers to the entire region including the GaN layer and the AlGaN layer formed on the GaN layer. Two-dimensional carrier gas is usually formed at the interface between the GaN layer and the AlGaN layer within the Group-III nitride semiconductor region. In an embodiment, the two-dimensional carrier gas refers to two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG).

[0068] When integrated on the same substrate (monolithic integration), the heterojunction power device may further include an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor. The isolation region separates the active two-dimensional carrier gas and the auxiliary two-dimensional carrier gas. The isolation region may separate the first and second Group-III nitride semiconductor regions.

[0069] In use, when the first additional terminal and the auxiliary gate region can be biased at a potential (or voltage), the carrier density in a portion of the auxiliary two-dimensional carrier gas below the auxiliary gate region is controlled such that an auxiliary two-dimensional carrier gas connection is established between the first and second additional terminals. Generally, a two-dimensional electron gas (2DEG) is formed below the first and second additional terminals. When a voltage is applied to the auxiliary gate region (or high-voltage terminal), it controls the carrier density in the 2DEG below the auxiliary gate, and thus a 2DEG connection is formed between the 2DEGs below the first and second additional terminals.

[0070] The active gate region can be configured to conduct through an auxiliary two-dimensional carrier gas (e.g., 2DEG) connection between the first and second additional terminals. A change in the resistance of the 2DEG connection below the auxiliary gate region can also turn on the active gate. The auxiliary 2DEG connection can be used as the internal resistance of the active gate region. This internal gate resistance can be used to slow down the rapid dV / dt during switching or prevent high oscillations caused by the di / dt effect.

[0071] The first additional terminal and the auxiliary gate region can be configured such that a portion of the potential is used to form the auxiliary 2DEG connection and another portion of the potential is used to conduct the active gate region.

[0072] The first group-III nitride semiconductor region can include an active aluminum gallium nitride (AlGaN) layer that is in direct contact with the first terminal, the active gate region, and the second terminal.

[0073] The second group-III nitride semiconductor region can include an auxiliary aluminum gallium nitride (AlGaN) layer that is in direct contact with the first additional terminal, the auxiliary gate region, and the second additional terminal.

[0074] The thicknesses of the active AlGaN layer and the auxiliary AlGaN layer can be the same or different.

[0075] The doping concentrations of the active AlGaN layer and the auxiliary AlGaN layer can be the same or different.

[0076] The aluminum mole fractions of the active AlGaN layer and the auxiliary AlGaN layer can be the same or different.

[0077] The active gate region can include p-type gallium nitride (pGaN) material. The metal contact on the active pGaN gate can be Schottky or ohmic. Alternatively, the active gate region can include a recessed Schottky contact.

[0078] Each of the first terminal, the second terminal, the first additional terminal, and the second additional terminal can include a surface ohmic contact. Alternatively, each of the first terminal, the second terminal, the first additional terminal, and the second additional terminal can include a recessed ohmic contact.

[0079] The auxiliary gate region may include a field plate extending towards the first additional terminal, and wherein the field plate extends over the field oxide region.

[0080] The power device may have an interleaved layout, wherein the gate metal pad is directly connected to the auxiliary gate region and the first additional terminal, and the active gate region includes gate fingers connected to the second additional terminal. Alternatively, the device may have an interleaved layout, wherein the auxiliary gate region, the first additional terminal, and the second additional terminal are located under the source metal pad. Advantageously, compared to prior art designs, no additional chip area is required to include the auxiliary gate structure.

[0081] In an embodiment, the second additional terminal and the active gate region may be connected in a third dimension of the device.

[0082] Compared with the active heterojunction transistor, the active heterojunction transistor may be a high-voltage transistor, while the auxiliary heterojunction transistor may be a low-voltage transistor.

[0083] The heterojunction power device may further include a diode connected in parallel between the first and second additional terminals of the auxiliary heterojunction transistor. During the turn-off of the entire configuration where the gate terminal of the active GaN transistor is connected to ground, the parallel diode acts as a pull-down network. When a positive bias (conducting state) is applied to the auxiliary gate, the diode will be reverse-biased, and zero current will flow through it, which will not affect the electrical behavior of the entire high-voltage configuration. When a zero bias (turn-off state) is applied to the auxiliary gate, the diode will be forward-biased, and the turn-off current flowing through it will discharge the gate capacitance of the active transistor, enabling the entire configuration to turn off. In the turn-off state, the gate of the active transistor will remain biased to a minimum voltage (equal to the turn-on voltage of the diode). Therefore, the diode is designed to have as low a turn-on voltage as possible, ideally a few millivolts. The diode may be formed monolithically with the device. The diode may be a simple Schottky diode. The diode typically pulls down the active gate to the diode V th , so the diode needs to be designed to have as low a threshold voltage as possible. One feature that can achieve this is to use a recessed anode to directly contact the 2DEG.

[0084] Alternatively, normally-on (depletion-mode) GaN power devices not available in the prior art can be used. Such normally-on devices can include a gate structure based on a discontinuous p-GaN layer (or a discontinuous region of the first conductivity type) that includes islands within a stripe or a closed shape surrounding a cell that, when a gate voltage is provided, is used to modulate a conduction path given by a two-dimensional electron gas (or a two-dimensional carrier gas of the second conductivity type) between a high-voltage terminal and a low-voltage terminal. All such islands can be connected to the same gate electrode. It should be understood that a discontinuous island means that there is no p-GaN layer between adjacent islands, and thus there is a direct and unobstructed conduction path provided by the two-dimensional electron gas between the source terminal and the drain terminal. However, adjacent islands are positioned together in a direction intersecting (orthogonal to) the current path such that the potential applied to the p-GaN gate islands modulates the conductive region between the islands, thereby modulating the direct path between the source and the drain. The p-GaN layers in the continuous and discontinuous gate structures are completed in the same process step, and the difference between continuous and discontinuous is achieved by a layout change of the same mask.

[0085] The operation of this normally-on (depletion-mode) device is characterized by the presence of two threshold voltages. The first threshold voltage can be negative and equivalent to the threshold voltage of a classical normally-on transistor, indicating a transition from an off state to an on state. The second threshold voltage is preferably positive and is characterized by a sharp increase in current. The second threshold voltage can be the same as that of an integrated normally-off device having a continuous p-GaN gate.

[0086] The two threshold voltages are discussed and identified more clearly and in more detail below.

[0087] In addition to epitaxial / process modifications, the first threshold voltage, which is referred to here as the device threshold voltage, can also be adjusted by layout modifications. Furthermore, the depletion-mode (normally-on) device proposed here can allow an increased positive gate bias (>7V) to be applied before the channel in the dominant on state changes from drain-source to gate-source. Such a device can be implemented in a manufacturing process that does not provide a Schottky contact on the surface of the AlGaN layer.

[0088] Alternatively, normally-on depletion devices using discontinuous pGaN islands can be used in diode mode by connecting the gate and source together (or becoming the anode terminal due to symmetry from connecting the drain and gate together). The distance (pitch) between pGaN islands can be used to adjust the voltage level at which the diode conducts current in the forward mode. This is particularly advantageous over the prior art using a continuous pGaN layer, which results in a large forward voltage. For example, the pitch between pGaN islands (or multiple strips of pGaN islands) can be used to adjust this open-circuit forward voltage to 0.3 to 0.5 V, which is characteristic of Schottky diodes in silicon. To avoid an undesired negative open-circuit voltage for the diode, the pitch between pGaN islands should be very small (on the order of tens or hundreds of nanometers), or the source of the HEMT in the diode configuration can have a Schottky contact.

[0089] When a 2DEG is formed under the pGaN layer, a second increase in current occurs at a higher voltage level (above the open-circuit voltage level) during forward conduction. In forward conduction, it is desirable for the diode to operate above this second voltage level to minimize the on-state resistance.

[0090] In all embodiments, the contact to the pGaN islands can be made of ohmic or Schottky metallization.

[0091] The first additional terminal (or drain (gate) terminal) and the second additional terminal (or source terminal) of the (first) auxiliary heterojunction transistor can each be used as an external gate terminal.

[0092] In the present invention, the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and the heterojunction device further includes a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor can be connected to the source terminal of the second auxiliary heterojunction transistor, while the second additional terminal (or source terminal) of the first auxiliary heterojunction transistor can be operatively connected to the drain (gate) terminal of the second auxiliary heterojunction transistor.

[0093] The pull-down network through the second auxiliary heterojunction transistor may further include a resistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The resistor is between the gate and drain terminals of the second auxiliary transistor. Thus, the resistor does not form a common node between the gates of the first auxiliary transistor and the active transistor. The function of the resistor is to reduce the active gate capacitance discharge time through the pull-down network during the off period of the heterojunction power device. The additional resistive element performs this function by generating a potential at the gate terminal of the second auxiliary transistor that is increased compared to the drain terminal of the second auxiliary transistor during the off period. The additional resistor may be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active power transistor. During the off period of the active device, the additional resistor acts as a parallel pull-down network. Thus, it can be understood that the additional resistor is not connected through the common node connecting the source of the first auxiliary transistor and the gate of the active transistor. During the on and conducting states of the active device, the additional resistor may act as a voltage limiting component to protect the gate terminal of the active device.

[0094] The pull-down network through the second auxiliary heterojunction transistor may further include a third auxiliary transistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The function of the third auxiliary transistor is to reduce the active gate capacitance discharge time through the pull-down network during the off period of the heterojunction power device. The third auxiliary transistor performs this function by generating a potential at the gate terminal of the second auxiliary transistor that is increased compared to the drain terminal of the second auxiliary transistor during the off period. The third auxiliary transistor may be a depletion-mode low-voltage transistor. The depletion-mode device may be made of a p-GaN island as Figure 18 shown, or may be a diode as Figure 19 shown. The gate terminal of the third auxiliary transistor may be connected to the source or drain terminal of the third auxiliary transistor. The additional resistor may be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active (high-voltage) transistor. In other words, it can be understood that the additional resistor is not connected through the common node connecting the source of the first auxiliary transistor and the gate of the active transistor. During the off period of the active device, the additional resistor acts as a parallel pull-down network. During the on and conducting states of the active device, the additional resistor may act as a voltage limiting component to protect the gate terminal of the active device.

[0095] The heterojunction power device further includes a voltage limiting circuit, which includes two resistors forming a voltage divider and a low-voltage enhancement-mode transistor for actively switching. The drain-source path of the actively switched low-voltage enhancement-mode transistor is connected between the gate and the source of the active power transistor. The voltage divider is connected between the first additional terminal (or the drain (gate) terminal) of the first auxiliary heterojunction transistor and the source terminal of the active (high-voltage) transistor. The midpoint of the voltage divider is connected to the gate terminal of the low-voltage enhancement-mode transistor. When the voltage at the first additional terminal (or the drain (gate) terminal) rises above a certain value (which can be controlled by the selection of the resistors in the described voltage divider), the enhancement-mode transistor can be turned on, thereby adjusting the resistance between the gate terminal of the active device and the source terminal of the active (high-voltage) device. This function can protect the active gate terminal from overvoltage events.

[0096] The heterojunction power device may further include a voltage limiting circuit as described above, where the low-voltage enhancement-mode transistor is replaced by a low-voltage depletion-mode transistor. In this embodiment, when the potential at the first additional terminal (or the drain (gate) terminal) of the first auxiliary heterojunction transistor increases, the resistance of the depletion-mode transistor can be reduced, thereby adjusting the resistance between the gate terminal of the active (high-voltage) device and the source terminal of the active device. The voltage divider formed by the resistors determines the potential on the gate terminal of the depletion-mode transistor. The described circuit can protect the active gate terminal from overvoltage events.

[0097] The heterojunction power device may further include an overcurrent protection circuit composed of a current sensing resistor and an actively switched low-voltage enhancement-mode transistor. The active region of the active (high-voltage) transistor is divided into two regions, which form two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low-resistance (main power) transistor and a high-resistance (current sensing) transistor respectively. The first terminal of the current sensing resistor is connected to the source terminal of the high-resistance transistor. The actively switched enhancement-mode transistor is connected between the gate terminal of the active (high-voltage) transistor and the second terminal of the current sensing resistor. The gate terminal of the low-voltage enhancement-mode transistor is connected to the first terminal of the current sensing resistor. As the current passing through the high-resistance transistor increases, the potential drop across the current detection resistor increases, raising the potential on the gate of the low-voltage enhancement-mode resistor, thereby adjusting its resistance. The critical current through the low-voltage transistor can turn on the low-voltage enhancement-mode transistor, thereby limiting the potential on the gate of the active power transistor. The described circuit can protect the circuit from overcurrent events. The described components can be monolithically included in the design.

[0098] The heterojunction power device may further include an overcurrent protection circuit as described above, where the low-voltage enhancement-mode transistor is replaced by a low-voltage depletion-mode transistor. Similarly, the potential at the gate terminal of the depletion-mode transistor increases as the current through the current sensing resistor increases. As the current through the current sensing resistor increases, the resistance of the depletion-mode transistor decreases, reducing the resistance of the path between the gate and source of the active (high-voltage) device, thereby limiting the potential on the active gate terminal. The described circuit can protect the circuit from overcurrent events.

[0099] The heterojunction power device may further include an active Miller clamp to provide an additional pull-down network for the active (high-voltage) device gate terminal during the device turn-off transient. The active Miller clamp consists of a logic inverter and a transistor acting as an active ground switch for the pull-down network. The logic inverter can consist of a resistor or resistive element (i.e., a load transistor) and an enhancement-mode transistor.

[0100] The transistor acting as the active ground switch can be an enhancement-mode or depletion-mode transistor. In operation, the active Miller clamp uses the voltage bias of an external gate terminal (i.e., the terminal connected to the gate driver) to adjust the resistance of the transistor acting as the active ground switch, thereby providing a low-resistance pull-down path when the main power device is turning off or is in the off state. When the gate driver signal is high, the bias on the gate of the transistor acting as the active ground switch in the Miller clamp is low (so its resistance is high), and vice versa.

[0101] The resistor (in any of the embodiments shown here) can be made of a metal layer in the process, an AlGaN layer, or preferably made of 2DEG. For high packaging density, the resistor can be made in a meandering shape. The above-described functional blocks can be included in the design discreetly, monolithically, or in a hybrid package.

[0102] The depletion-mode transistor in the described functional block can be a Schottky gate HEMT as described in the prior art.

[0103] In addition, the normally-on (depletion-mode) transistor in the described functional block can be the above-described pGaN island transistor.

[0104] It should be understood that, as already mentioned, the auxiliary heterojunction transistor can have interchangeable source and drain. Different from the active (high-voltage) transistor, the source and drain in the auxiliary heterojunction can be symmetric or fabricated and arranged in a similar manner so that the source can act as the drain and vice versa.

[0105] According to a second aspect of the present disclosure, a gallium nitride (GaN) chip is provided, which includes a heterojunction power device based on a group III nitride semiconductor according to the foregoing aspect and an auxiliary low-voltage transistor according to the foregoing aspect, but wherein the auxiliary gate region terminal is operatively connected to a control circuit (block) and a pull-down circuit (block).

[0106] The current control block can be connected between a first additional terminal and the auxiliary gate region. The pull-down circuit block can be connected between the auxiliary gate terminal and the first terminal (source) of the heterojunction power device (which is the same as the low-voltage terminal of the GaN chip).

[0107] The GaN chip can further include an overcurrent protection circuit as described above, wherein the low-voltage transistor is in parallel with the pull-down circuit.

[0108] The GaN chip can further include an integrated current control circuit (block). As described above, the current control block provides current to charge and discharge the gate of the auxiliary HEMT in the auxiliary gate circuit. The current control block can be connected between the first additional terminal and the gate of the auxiliary HEMT.

[0109] In some embodiments, the integrated current control block can be a resistive element. The resistive element can be made of a metal layer or a 2DEG layer.

[0110] In other embodiments, the current control block can be or include a current source. The current source can be composed of a low-voltage depletion-mode HEMT and a resistive element. The drain of the low-voltage HEMT can be connected to the first additional terminal, the source to the first terminal of the resistive element, and the gate to the second terminal of the resistive element. The second terminal of the resistive element can also be connected to the gate terminal of the auxiliary HEMT.

[0111] In similar embodiments, an RCL network can be included in parallel or in series with the resistive element or the current source to improve the characteristics of the current control block.

[0112] The current control block can further include a circuit that generates an additional voltage drop. Such a circuit can be one or several low-voltage diodes, one or several low-voltage HEMTs with the gate connected to the source, or a low-voltage enhancement-mode HEMT with a voltage divider connected between the drain and source terminals of the HEMT (where the midpoint of the voltage divider is connected to the gate terminal of the HEMT).

[0113] The current control block can further include a circuit that adapts the current in the current control block. Such a current reduction circuit can include a depletion-mode HEMT or an enhancement-mode HEMT in series or in parallel with the resistive element in the current source. The gate of the HEMT can be connected to a voltage divider between the gate and the first terminal of the auxiliary HEMT or to a node within the integrated pull-down circuit.

[0114] The heterojunction GaN chip may further include an integrated pull-down circuit block. The pull-down circuit block may be connected between the gate of the auxiliary HEMT and the first terminal (the source terminal of the main power heterojunction transistor - the same as the low-voltage terminal of the GaN chip).

[0115] In some embodiments, the integrated pull-down circuit block may be one or more normally-open or normally-closed HEMTs in parallel or series. There may be additional capacitors or resistors in series with the HEMT. The gate potential of the pull-down HEMT is controlled to set the voltage drop across the pull-down HEMT, thereby setting the gate voltage of the auxiliary gate block and the voltage drop across the auxiliary gate block.

[0116] In one embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the gate terminal of the auxiliary HEMT and the first terminal.

[0117] In another embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the source terminal of the HEMT in the current source of the current control block and the first terminal.

[0118] In additional embodiments, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the active gate and the first terminal.

[0119] In a fourth embodiment, the gate terminal of the pull-down HEMT may be connected to the output of a voltage divider between the first additional terminal and the first terminal.

[0120] In additional embodiments, an additional current control block is connected to the first additional terminal. The additional current control block is connected to an additional pull-down circuit (connected to the first terminal). In this embodiment, the gate terminal of the first pull-down HEMT may be connected to the output of a voltage divider on the additional pull-down circuit.

[0121] In all these embodiments of the pull-down circuit, the voltage divider may be composed of resistive elements, such as resistors formed of metal or 2DEG; capacitors; current sources formed of depletion-mode HEMTs, whose source is connected to the first terminal of the resistive element and whose gate is connected to the second terminal; Schottky diodes, enhancement-mode HEMTs with their gate terminals connected to their source terminals; HEMTs, whose gate terminals are connected to the output of a voltage divider between their drain and source; or similar voltage divider circuits.

[0122] The pull-down circuit or current control or auxiliary gate circuit may also include elements that compensate for or reduce the temperature effect. This element is a specific embodiment of a voltage divider that is part of the pull-down circuit. The first part of the voltage divider may include an integrated resistor, while the second part of the voltage divider may include a current source consisting of a normally-open HEMT whose source is connected to the first terminal of an additional resistor and whose gate is connected to the second terminal of the resistor. The first part of the voltage divider may also include a similar current source in parallel with the resistor. The second part of the voltage divider may also include a resistor in parallel with the current source.

[0123] The two parts of the voltage divider will increase the voltage drop with increasing temperature at a given current. However, the current source and the resistor change the voltage drop at different rates. By designing the size of the normally-open HEMT and the resistor, the output of the voltage divider can be designed to have a smaller temperature dependence on the voltage drop across the pull-down circuit and / or the voltage drop across the auxiliary HEMT.

[0124] In another embodiment, the gate of the pull-down HEMT is controlled by an overcurrent protection circuit or an overtemperature protection circuit.

[0125] In another embodiment, the gate of the pull-down HEMT is directly or indirectly controlled by an external circuit or an additional circuit integrated on the GaN device.

[0126] The GaN chip may include more than one main power device. For example, a half-bridge configuration in which a low-side power device is connected in series with a high-side main power device is possible. A full bridge consisting of two half-bridge arms or a three-phase GaN chip configuration is also possible. According to this aspect of the present invention, at least one main power device in these configurations (half-bridge or full-bridge or three-phase) includes the auxiliary gate circuit, the pull-down circuit, and the current control circuit as described above.

[0127] According to another aspect of the present disclosure, a method for manufacturing a heterojunction power device based on a group III nitride semiconductor is provided, the method including:

[0128] Forming an active heterojunction power transistor on a substrate, the active heterojunction transistor including:

[0129] A first group III nitride semiconductor region including a first heterojunction, the first heterojunction including an active two-dimensional carrier gas;

[0130] A first terminal operatively connected to the group III nitride semiconductor region;

[0131] A second terminal laterally spaced from the first terminal and operatively connected to the group III nitride semiconductor region;

[0132] An active gate region, formed over a Group-III nitride semiconductor region, the active gate region being formed between a first terminal and a second terminal;

[0133] Forming a first auxiliary heterojunction transistor on the substrate or on an additional substrate, the auxiliary heterojunction transistor including:

[0134] A second Group-III nitride semiconductor region, including a second heterojunction, the second heterojunction including an auxiliary two-dimensional carrier gas;

[0135] A first additional terminal, operatively connected to the second Group-III nitride semiconductor region;

[0136] A second additional terminal, laterally spaced apart from the first additional terminal and operatively connected to the second Group-III nitride semiconductor region;

[0137] An auxiliary gate region, formed over the second Group-III nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;

[0138] Forming a second auxiliary heterojunction transistor on the substrate or the additional substrate,

[0139] Operatively connecting the first additional terminal to the auxiliary gate region, and

[0140] Operatively connecting the second additional terminal to the active gate region,

[0141] Operatively connecting the second auxiliary heterojunction transistor in parallel with the first auxiliary transistor,

[0142] Operatively connecting the first additional terminal of the first auxiliary heterojunction transistor to the source terminal of the second auxiliary heterojunction transistor, and

[0143] Operatively connecting the second additional terminal of the first auxiliary heterojunction transistor to the drain terminal of the second auxiliary heterojunction transistor.

[0144] The method may further include forming an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor, which separates the active two-dimensional carrier gas and the auxiliary two-dimensional carrier gas.

[0145] The method may further include forming a first Group-III nitride semiconductor region while forming the second Group-III nitride semiconductor region.

[0146] The method may further include forming the active gate region while forming the auxiliary gate region.

[0147] The method may further include forming a metallization layer for the first terminal, the second terminal, the first additional terminal, and the second additional terminal simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0148] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings. However, it should not be considered as limiting the present disclosure to the specific embodiments shown, but only for illustration and understanding purposes.

[0149] Figure 1 Schematically shows a cross-section in the active region of a prior art pGaN HEMT;

[0150] Figure 2 Schematically shows a cross-section of the active region of the proposed disclosure according to an embodiment of the present disclosure;

[0151] Figure 3 Schematically shows a circuit schematic representation of an embodiment as shown in the Figure 2 schematic cross-section;

[0152] FIG. 4A shows a circuit schematic representation of another embodiment of the proposed disclosure, wherein a low on-state voltage diode is connected in parallel between the drain and source of the auxiliary transistor;

[0153] FIG. 4B shows a 3D schematic representation of the embodiment of FIG. 4A;

[0154] FIG. 4C shows a cross-section of the low voltage diode used in the embodiment of FIG. 4A;

[0155] Figure 5 Schematically shows a circuit schematic representation of another embodiment of the proposed disclosure, wherein the drain (gate) terminal and the source terminal of the auxiliary transistor can be used as an external gate terminal;

[0156] Figure 6 Schematically shows a circuit schematic representation of another embodiment of the proposed disclosure, wherein a second auxiliary transistor is connected in parallel with the first auxiliary transistor, wherein the drain (gate) terminal of the first low auxiliary transistor is connected to the source terminal of the second auxiliary transistor, and the source terminal of the first low auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor;

[0157] Figure 7 Schematically shows a circuit schematic representation of another embodiment of the proposed disclosure, wherein a resistor is added between the drain terminal and the gate terminal of the second auxiliary transistor;

[0158] Figure 8 Schematically shows a circuit schematic representation of another embodiment of the proposed disclosure, wherein an additional resistor is added between the source terminal of the auxiliary transistor (the drain terminal of the second auxiliary transistor) and the source terminal of the active device;

[0159] Figure 9 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; the gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor;

[0160] Figure 10 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; the gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor;

[0161] Figure 11 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where a voltage limiting circuit composed of two resistors forming a voltage divider and an actively switched low-voltage enhancement-mode transistor is implemented;

[0162] Figure 12 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where a voltage limiting circuit composed of two resistors forming a voltage divider and an actively switched low-voltage depletion-mode transistor is implemented;

[0163] Figure 13 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where an overcurrent protection circuit composed of a resistor and an actively switched low-voltage enhancement-mode transistor is implemented;

[0164] Figure 14 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where an overcurrent protection circuit composed of a resistor and an actively switched low-voltage depletion-mode transistor is implemented;

[0165] Figure 15 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where an active Miller clamp circuit composed of a resistor, an actively switched low-voltage enhancement-mode transistor, and an actively switched depletion-mode transistor is implemented;

[0166] Figure 16 A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where an active Miller clamp circuit composed of a resistor, an actively switched low-voltage enhancement-mode transistor, and an actively switched depletion-mode transistor is implemented;

[0167] Figure 17 A schematic representation of a cross-section of the active region of a depletion-mode device that can be used as an actively switched transistor proposed in the prior art is presented;

[0168] Figure 18Shows a three-dimensional schematic representation of the active region of a depletion-mode device with a pGaN island (not found in the prior art) that can be used as an actively switched transistor;

[0169] Figure 19 Shows the active region of a depletion-mode device operating in diode mode with Figure 18 the pGaN island shown; and

[0170] Figure 20 Shows Figure 18 the transfer characteristics of the depletion-mode device shown.

[0171] Figure 21 Shows a schematic representation of a cross-section of an active region of the proposed disclosure according to another embodiment of the present disclosure. In this embodiment, the first additional terminal 16 is not operatively connected to the auxiliary gate terminal 15.

[0172] Figure 22 Shows a circuit schematic representation of an embodiment of the proposed disclosure as shown in Figure 21 a schematic cross-section.

[0173] Figure 23 Shows a schematic representation of a second aspect of an embodiment of the proposed disclosure, where the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block.

[0174] Figure 24 Shows the relationship between an external gate voltage bias and an active gate voltage.

[0175] Figure 25 Shows a circuit schematic representation of another embodiment of the proposed disclosure, where the current control block consists of a resistive element and the pull-down circuit includes a HEMT in a threshold multiplier configuration.

[0176] Figure 26 Shows a circuit schematic representation of another embodiment of the proposed disclosure, where the current control block includes a resistive element with a capacitive element in parallel, and where the pull-down circuit includes a HEMT in a threshold multiplier configuration, with an additional capacitive element.

[0177] Figure 27 Shows a circuit schematic representation of another embodiment of the proposed disclosure, where the current control block includes a normally-on HEMT and a series resistive element, where the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and where the pull-down circuit includes a HEMT in a threshold multiplier configuration. In this embodiment, the auxiliary gate block includes an enhancement-mode low-voltage HEMT and a Schottky diode in parallel.

[0178] Figure 28 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the current control block includes a normally - on HEMT and a resistive element in series, where the gate of the normally - on HEMT is connected to the second terminal of the resistive element; and where the pull - down circuit includes a HEMT in a threshold multiplier configuration.

[0179] Figure 29 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the auxiliary gate block includes a second auxiliary transistor connected in parallel with a first auxiliary transistor, where the gate terminal of the second auxiliary transistor is connected to the source terminal of the first auxiliary transistor;

[0180] Figure 30 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the pull - down circuit includes a HEMT in a threshold multiplier configuration. In this embodiment, the voltage divider of the pull - down circuit includes a temperature compensation circuit, which includes a current source connected in parallel with a resistive element.

[0181] Figure 31 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the voltage divider of the pull - down circuit is connected to the source terminal of the HEMT of the current control block.

[0182] Figure 32 A schematic representation of an embodiment of the proposed disclosure, where the gate terminal of the auxiliary gate block is controlled by the current control block and the pull - down circuit block; and where the Miller - clamping HEMT is controlled by a logic inverter. The logic inverter is powered by the output voltage of an integrated DC / DC voltage regulator. Further, the input of the logic inverter is the output of the VG - to - Vlogic voltage regulator, which limits the voltage from the first additional terminal to a level optimized for the integrated GaN HEMT included in the inverter circuit.

[0183] Figure 33 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the auxiliary gate block includes a normally - on HEMT.

[0184] Figure 34 A schematic representation of a circuit showing a further embodiment of the proposed disclosure, where the auxiliary gate block includes a normally - on HEMT and where the auxiliary gate block includes a second auxiliary transistor connected in parallel with a first auxiliary transistor, where the source of the second auxiliary transistor is connected to the source of the first auxiliary transistor;

[0185] Figure 35A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the auxiliary gate block includes a normally-on HEMT and where the auxiliary gate block includes a second auxiliary normally-on HEMT connected in parallel with the first auxiliary transistor, where the gate terminal of the second auxiliary transistor is connected to the first terminal;

[0186] Figure 36 A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the voltage divider of the pull-down circuit is connected to the active gate terminal.

[0187] Figure 37 A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the voltage divider of the pull-down circuit is connected to the active gate terminal, and where the voltage divider includes a series of source-gate connected E-HEMTs.

[0188] Figure 38 A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the voltage divider of the pull-down circuit is connected to the active gate terminal, and where the voltage divider includes HEMTs in a threshold multiplier configuration.

[0189] Figure 39 A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the voltage divider of the pull-down circuit is connected to a first additional terminal, and where the voltage divider includes HEMTs in a threshold multiplier configuration.

[0190] Figure 40 A schematic circuit representation of an additional embodiment of the proposed disclosure is shown, where the voltage divider of the pull-down circuit is connected to a first additional terminal, and where the voltage divider includes a current source (formed by a normally-on HEMT and a resistor) and HEMTs in a threshold multiplier configuration. In this embodiment, the output of the voltage divider is the gate terminal of the HEMTs in the threshold multiplier configuration.

[0191] Figure 41 An interleaved device layout of an additional embodiment of the present disclosure is shown, which incorporates an auxiliary gate structure having a current control block and a pull-down circuit block.

[0192] Figure 42 An interleaved device layout of an additional embodiment of the present disclosure is shown, where the auxiliary gate having a current control block, a pull-down circuit block, and a terminal region is located under the source pad metal.

[0193] Figure 43 A block diagram of an additional embodiment of the proposed disclosure is shown, where any one embodiment of the GaN chip power device according to the present disclosure is in a half-bridge configuration.

[0194] Figure 44A block diagram showing another embodiment of the proposed disclosure, in which any one embodiment of the GaN chip power device according to the present disclosure is located in a three-phase half-bridge configuration. Detailed Description

[0195] Figure 2 A schematic representation of a cross-section of an active region according to one embodiment of the present disclosure is shown. In use, current flows in the active region of the semiconductor device. In this embodiment, the device includes a semiconductor (e.g., silicon) substrate 4 that defines a main (horizontal) surface at the bottom of the device. There is a substrate terminal 5 below the substrate 4. The device includes a first region of a transition layer 3 above the semiconductor substrate 4. The transition layer 3 includes a combination of III-V semiconductor materials, which is used as an intermediate step to allow the subsequent growth of high-quality III-V semiconductor materials.

[0196] There is a second region 2 above the transition layer 3. This second region 2 is a high-quality III-V semiconductor (e.g., GaN) and includes several layers. A third region 1 of the III-V semiconductor containing an aluminum mole fraction is formed above the second region 2. The third region 1 is formed such that a heterostructure is formed at the interface between the second region 2 and the third region 1, thereby forming a two-dimensional electron gas (2DEG).

[0197] A fourth region 11 of highly p-doped III-V semiconductor is formed in contact with the third region 1. This has the effect of reducing the 2DEG carrier concentration when the device is unbiased, and in this embodiment is a pGaN material. The gate control terminal 10 is configured above the fourth region 11 to control the carrier density of the 2DEG at the interface between the second region 2 and the third region 1. The high-voltage drain terminal 9 is arranged to make physical contact with the third region 1. The high-voltage drain terminal forms an ohmic contact with the 2DEG. The low-voltage source terminal 8 is also arranged to make physical contact with the third region 1 and also forms an ohmic contact with the 2DEG.

[0198] A portion of the surface passivation dielectric 7 is formed above the fourth region 1 and between the drain terminal 9 and the source terminal 8. The SiO2 passivation layer 6 is formed above the surface passivation dielectric 7 and the source terminal 8 and the drain terminal 9.

[0199] The device is divided into two cross-sections by a vertical cut line. The two cross-sections are not necessarily in the same plane. The above features are on one side of the vertical cut line (e.g., the right hand side). This is called the active device 205. The other side of the vertical cut line (e.g., the left hand side) is called the auxiliary device 210, which also includes the semiconductor substrate 4, the transition layer 3, the second region 2, and the SiO2 passivation region 6.

[0200] The fifth region 17 of the III-V semiconductor containing the molar fraction of aluminum is located above the second region 2 in the auxiliary device, so that a heterostructure is formed at the interface between the fifth region 17 and the second region 2. This results in the formation of a second two-dimensional electron gas (2DEG) in the region that will be referred to as the auxiliary gate. The AlGaN layer 17 of the auxiliary device 210 can be the same as or different from the AlGaN layer 1 in the active device 205. The AlGaN layer thickness and the aluminum molar fraction are key parameters because they affect the carrier density of electrons in the 2DEG

[15] .

[0201] The sixth region 14 of the highly p-doped III-V semiconductor is formed on and in contact with the fifth region 17. This has the function of reducing the 2DEG carrier concentration when the auxiliary gate is unbiased. The auxiliary gate control terminal 15 is configured to be above the sixth region 14 to control the carrier density of the 2DEG at the interface between the fifth region 17 and the second region 2. The auxiliary gate pGaN layer 14 can be the same as or different from the active gate pGaN layer 11. Key parameters that may be different include but are not limited to pGaN doping and the width along the x-axis (as shown in the figure).

[0202] The isolation region 13 is formed downward along the vertical cutting line. This cuts off the electrical connection between the 2DEG formed in the active device 205 and the 2DEG formed in the auxiliary device 210.

[0203] The first additional terminal 16 is arranged above and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact with the 2DEG of the auxiliary device 210 and is also electrically connected (via the interconnecting metal) to the auxiliary gate control terminal 15 configured to be above the sixth region (pGaN) 14. The first additional terminal 16 is biased at the same potential as the auxiliary gate terminal 15 of the auxiliary device. The second additional terminal 12 is also arranged above and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact with the 2DEG of the auxiliary device 210 and is electrically connected (via the interconnecting metal) to the active gate control terminal 10 configured to be above the fourth region 11 of the active device 205. The interconnection between the second additional terminal 12 of the auxiliary device 210 and the active gate terminal 10 of the active device 205 can be made in the third dimension, and different metal layers can be used in the process. Note that this interconnection is not shown in the Figure 2 schematic representation. A similar but not necessarily identical AlGaN / GaN structure is used in the auxiliary gate.

[0204] When the device is in use, the auxiliary gates 14, 15 drive the active gates 10, 11. The auxiliary 2DEG layer formed between the first additional terminal 16 and the second additional terminal 12 and the part below the auxiliary p-GaN gate 14 are controlled by the potential applied to the auxiliary gate terminal 15.

[0205] When the auxiliary gate terminal 15 and the shorted first additional terminal 16 are at 0 V, a portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 is depleted. As the auxiliary gate bias (both terminals 15, 16) increases, 2DEG starts to form under the pGaN gate 14, which is connected to the already formed 2DEG layer that is connected to the first additional terminal 16 and the second additional terminal 12. The 2DEG connection is now located between the first additional terminal 16 and the second additional terminal 12.

[0206] When the second additional terminal 12 is connected to the active gate 10, the device can now be turned on. A positive (and desired) shift in the device threshold voltage is observed using this structure because not all of the potential applied to the auxiliary gate 15 is transferred to the active gate 10. A portion of this potential is used to form the auxiliary 2DEG under the auxiliary gate 15, and only a portion is transferred to the second additional terminal 12 that is connected to the active gate 10.

[0207] The auxiliary gate provides an additional advantage of being able to more easily control the gate resistance of the device. This can be achieved by changing the field plate design or the distance between terminals 12 and 15 or 15 and 16. This can be used to control the unexpected oscillations observed due to the fast switching of these devices.

[0208] Different embodiments of the device can include terminals 10, 15 that are Schottky or ohmic contacts or any combination of the two.

[0209] Figure 3 A schematic circuit representation of one embodiment as shown in the proposed disclosure in Figure 2 is shown in the schematic cross-section. Figure 3 The features shown in Figure 2 have the same reference numerals as the features in

[0210] FIG. 4A shows a schematic circuit representation of another embodiment of the proposed disclosure, where a low on-state voltage diode is connected in parallel between the drain and source of the auxiliary transistor, as shown schematically in 3D in FIG. 4B. Many features of this embodiment are the same as Figure 2are similar in characteristics and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, and second additional terminal 12. However, in this embodiment, a low on-state voltage diode 31 is connected in parallel between the drain 16 and source 12 of the auxiliary transistor. During the turn-off of the entire configuration in which the gate terminal 10 of the active GaN transistor is connected to ground, the parallel diode 31 acts as a pull-down network. When a positive bias (referred to as the on-state) is applied to the auxiliary gate, the diode will be reverse-biased and zero current will flow through it, which will not affect the electrical behavior of the entire high-voltage configuration. When a zero bias (off-state) is applied to the auxiliary gate 15, the diode 31 will be forward-biased and the off-state current flowing through it will discharge the gate capacitance of the active transistor, enabling the entire configuration to turn off. In the off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. Therefore, the diode 31 is designed such that its turn-on voltage is as low as possible, ideally a few millivolts. FIG. 4B shows how the diode 31 can be monolithically included. The diode can be a simple Schottky diode or can be an ordinary p-n diode. Diode 31 pulls down the active gate 10 to diode V during turn-off th , so the diode needs to be designed to have as low a threshold voltage as possible. As shown in FIG. 4C, one feature that can achieve this is to use a recessed anode to directly contact the 2DEG.

[0211] Figure 5 shows a schematic representation of the circuit of another embodiment of the proposed disclosure, in which the drain (gate) terminal 16 and source terminal 12 of the auxiliary transistor can be used as external gate terminals. Many features of this embodiment are similar to those of Figure 2 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, and second additional terminal 12. However, in this case, the external gate terminal is divided into two terminals. Since the gate driver receiver output pin can now be directly connected to the source terminal of the auxiliary transistor that provides the pull-down path, the component 31 in FIG. 4 can be (or may not be) omitted.

[0212] Figure 6A schematic circuit representation of a further embodiment of the proposed disclosure is shown, in which a second auxiliary transistor 34 (which can advantageously be a low-voltage one) is connected in parallel with the first auxiliary transistor, wherein the drain (gate) terminal 16 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor, and the source terminal 12 of the first low auxiliary transistor is connected to the drain (gate) terminal of the second auxiliary transistor. Many features of this embodiment are similar to those of Figure 2 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case, the pull-down network during the turn-off of the entire configuration is the second auxiliary transistor 34.

[0213] Figure 7 A schematic circuit representation of a further embodiment of the proposed disclosure is shown, in which a resistor 41 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor 34. Many features of this embodiment are similar to those of Figure 6 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12 and second auxiliary transistor 34. In this embodiment, the function of the resistor 41 is to reduce the active gate capacitance discharge time through the pull-down network during the turn-off of the active device. The additional resistor performs this function by generating a potential at the gate terminal 10 of the second auxiliary transistor that is increased compared to the drain terminal 12 of the second auxiliary transistor during the turn-off.

[0214] Figure 8 A schematic circuit representation of a further embodiment of the proposed disclosure is shown, in which an additional resistor 42 is added between the source terminal of the auxiliary transistor (the drain terminal 12 of the second auxiliary transistor) and the source terminal 8 of the active device. Many features of this embodiment are similar to those of Figure 7are similar in characteristics and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34, and resistance element 41. In this embodiment, additional resistance element 42 acts as an additional pull-down network during the turn-off of the active device. During the turn-on and conduction state of the active device, additional resistor 42 can act as a voltage-limiting component to protect the gate terminal of the active device.

[0215] Figure 9 A schematic circuit representation of another embodiment of the proposed disclosure is shown, in which a third auxiliary transistor 58 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are the same as those of Figure 8 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34, and additional resistance element 41. In this embodiment, the role of the third auxiliary transistor is to reduce the active gate capacitance discharge time through a pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 58 performs this function by generating an increased potential at the gate terminal 10 of the second auxiliary transistor compared to the drain terminal 12 of the second auxiliary transistor during the turn-off. The third auxiliary transistor is a depletion-mode device. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor.

[0216] Figure 10 A schematic circuit representation of another embodiment of the proposed disclosure is shown, in which a third auxiliary transistor 59 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are the same as those of Figure 8are similar in characteristics and thus have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34, and additional resistor element 41. In this embodiment, the role of the third auxiliary transistor is to reduce the active gate capacitance discharge time through a pull-down network during the turn-off of the heterojunction power device. The third auxiliary transistor 59 performs this function by generating a potential at the gate terminal of the second auxiliary transistor 10 that is increased compared to the drain terminal 12 of the second auxiliary transistor during turn-off. The third auxiliary transistor is a depletion-mode device. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor.

[0217] Figure 11 shows a schematic representation of a circuit of another embodiment of the proposed disclosure, in which a voltage-limiting circuit consisting of a resistor 44, a resistor 45 (forming a voltage divider), and an actively switched low-voltage enhancement-mode transistor 43 is implemented. Many features of this embodiment are the same as those of Figure 6 and thus have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or the drain (gate) terminal 16) rises above a certain value (which can be controlled by the selection of the resistors (44, 45) in the described voltage divider), the enhancement-mode transistor 43 can be turned on, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. This function can protect the active gate terminal from overvoltage events.

[0218] Figure 12 shows a schematic representation of a circuit of another embodiment of the proposed disclosure, in which a voltage-limiting circuit including a resistor 44, a resistor 45 (forming a voltage divider), and an actively switched low-voltage depletion-mode transistor 46 is implemented. Many features of this embodiment are the same as those of Figure 6are similar in characteristics and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or drain (gate) terminal 16) of the first auxiliary heterojunction transistor increases, the resistance of the depletion-mode transistor 46 can be reduced, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. A voltage divider formed by two resistors (44, 45) determines the potential on the gate terminal of the depletion-mode transistor 46. The described circuit can protect the active gate terminal from overvoltage events.

[0219] Figure 13 FIG. shows a schematic representation of a circuit of another embodiment of the proposed disclosure, in which an overcurrent protection circuit composed of a current sensing resistor 48 and an actively switched low-voltage enhancement-mode transistor 49 is implemented. Many features of this embodiment are the same as those Figure 6 are similar in characteristics and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, the active region of the active (high-voltage) transistor is divided into two regions, which form two parallel transistors. The drain and gate terminals of the two transistors are electrically connected. The two parallel transistors are a low-resistance (main power) transistor 55 and a high-resistance (current sensing) transistor 54, respectively. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high-resistance transistor 54. The potential at the gate terminal of the enhancement-mode transistor 49 increases as the current through the current sensing resistor 48 increases. When the current through the resistive element 48 reaches a critical value, the enhancement-mode transistor 49 turns on, providing a reduction in the resistance of the path between the gate 10 and the source 8 of the active (high-voltage) device, thereby limiting the potential on the active gate terminal 10. The described circuit can protect the circuit from overcurrent events.

[0220] Figure 14A schematic representation of a circuit showing a further embodiment of the proposed disclosure is presented, in which an overcurrent protection circuit consisting of a current sensing resistor 48 and an actively switched low-voltage depletion-mode transistor 47 is implemented. Many features of this embodiment are similar to those of Figure 6 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, the active region of the active (high-voltage) transistor is divided into two isolated regions, which form two parallel transistors. The drain and gate terminals of the two transistors are electrically connected. The two parallel transistors are a low-resistance (main power) transistor 55 and a high-resistance (current sensing) transistor 54, respectively. The first terminal of the current sensing resistor 48 is connected to the source terminal of the high-resistance transistor 54. The potential at the gate terminal of the depletion-mode transistor 47 increases as the current through the resistance element 48 increases. As the current through the resistance element 48 increases, the resistance of the depletion-mode transistor 49 decreases, providing a reduction in the resistance of the path between the gate 10 and source 8 of the active (high-voltage) device, thereby limiting the potential at the active gate terminal 10. The described circuit can protect the circuit from overcurrent events.

[0221] Figure 15 A schematic representation of a circuit showing a further embodiment of the proposed disclosure is presented, in which an active Miller clamp circuit consisting of a resistor 52, an actively switched low-voltage enhancement-mode transistor 50, and an actively switched depletion-mode transistor 51 is implemented. Many features of this embodiment are similar to those of Figure 6 and thus have the same reference numerals, namely, semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2 passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, an active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0222] Figure 16A schematic representation of a circuit showing another embodiment of the proposed disclosure is presented, where an active Miller clamp circuit composed of a resistor 52, an actively switched low-voltage enhancement-mode transistor 50, and an actively switched enhancement-mode transistor 53 is implemented. Many features of this embodiment are similar to those of Figure 6 and thus have the same reference numerals, namely, a semiconductor substrate 4, a substrate terminal 5, a transition layer 3, a GaN layer 2, an AlGaN layer 1, an active pGaN layer 11, an active gate terminal 10, a surface passivation dielectric 7, a low-voltage source terminal 8, a high-voltage drain terminal 9, an SiO2 passivation layer 6, an isolation region 13, an auxiliary AlGaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a first additional terminal 16, a second additional terminal 12, and a second auxiliary transistor 34. In this embodiment, the active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.

[0223] Figure 17 A schematic representation of a cross-section of the active region of a depletion-mode device that can be used as an actively switched transistor at positions 46, 47, 51, 58, 59, 60 as proposed in the prior art is shown.

[0224] Figure 18 A three-dimensional schematic representation of the active region of a depletion-mode device having a pGaN island (not found in the prior art) that can be used as an actively switched transistor at positions 46, 47, 51, 58, 59 is shown.

[0225] Figure 19 A three-dimensional schematic representation of the active region of a depletion-mode device having a pGaN island as shown in Figure 18 and operating in diode mode and used at positions 34, 58, 59 is shown.

[0226] Figure 20 A diagram shows Figure 18 the transfer characteristics of the depletion-mode device as shown.

[0227] Figure 21 A cross-section of an additional embodiment according to the second aspect of the proposed invention is shown. Figure 21 The features shown in Figure 2 have the same reference numerals as those shown in

[0228] Figure 22 A diagram shows Figure 21is schematically shown, and the features corresponding to that figure use the same reference numerals. In this embodiment, a series of components may be added between the auxiliary gate terminal 15 and the first additional terminal 16. By way of example only, these components may include, but are not limited to, any one or more of a resistive element, a passive element, and a current source. Additional illustrative examples of such embodiments are presented herein.

[0229] In Figure 23 a gallium nitride (GaN) chip 1000 (also referred to as an intelligent GaN power device or GaN power or high-voltage integrated circuit) according to an embodiment of the second aspect of the present invention is shown. The GaN chip may include at least three terminals. The at least three terminals may include one or more of a high-voltage terminal, a low-voltage terminal, and a control terminal. The chip 1000 may also include one or more main power heterojunction transistors 500 having an internal gate. The source terminal and the drain terminal of the transistor 500 may be connected to the low-voltage terminal and the high-voltage terminal of the GaN chip, respectively. The chip 1000 may also include a current control circuit 530, a pull-down circuit 520, and / or an auxiliary gate circuit 510. The auxiliary gate circuit 510 may include at least one low-voltage heterojunction transistor (also referred to as an auxiliary transistor) having an internal gate.

[0230] The auxiliary gate circuit 510 may be operatively connected to the internal gate of at least one main power heterojunction transistor 500 through a first connection, and may also include a second connection that operatively connects the auxiliary gate 510 to the control terminal. A third connection of the auxiliary gate circuit 510 may operatively connect the internal gate of the low-voltage heterojunction transistor of the auxiliary gate circuit 510 to the pull-down circuit 520.

[0231] In addition to at least one connection connected to the auxiliary gate circuit, the pull-down circuit 520 may also include at least one connection connected to the current control circuit and at least one connection connected to the source terminal of the main power heterojunction transistor 500.

[0232] The current control circuit 530 may include at least one connection connected to each of the control terminal, the auxiliary gate circuit 510, and the pull-down circuit 520.

[0233] The auxiliary gate 510 may partially control the voltage and current levels entering the internal gate of the main power heterojunction transistor 500. The current control circuit 530 may control the current level entering the pull-down circuit 520, and in combination with the pull-down circuit may further determine the voltage level applied to the internal gate of the low-voltage heterojunction transistor of the auxiliary gate 510. The pull-down circuit may then actively pull down the gate voltage of the low-voltage heterojunction transistor in order to clamp the voltage of the internal gate of the main power heterojunction transistor.

[0234] Referring toFigure 22 and Figure 23 , in some embodiments, the auxiliary gate terminal 15 of the auxiliary gate block 510 can be connected to the first additional terminal 16 of the auxiliary gate block 510 through or via the current control block 530. The auxiliary gate terminal 15 can also be connected to the source terminal 8 of the active device block 500 through or via the pull - down circuit block 520.

[0235] When the auxiliary gate terminal 15 is at or near 0V, the portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 can be depleted. As the bias of the first additional terminal is increased, the potentials on both the bias terminals 15, 16 may increase and 2DEG may start to form under the pGaN gate 14. The 2DEG formed under the pGaN gate 14 can be connected to the (already formed) 2DEG layer under the first additional terminal 16 and the second additional terminal 12. By connecting these 2DEG layers, a 2DEG connection can be formed between the first additional terminal 16 and the second additional terminal 12.

[0236] When the second additional terminal 12 is connected to the active gate 10, the device can now be turned on. A positive shift in the device threshold voltage is observed using this structure because not all of the potential applied to the first additional terminal 16 is transferred to the active gate (internal gate) 10. A portion of this potential drops across the auxiliary gate 510, and only a portion is transferred to the second additional terminal 12 connected to the active gate (internal gate) 10. Advantageously, as described below, this can increase the threshold voltage without degrading the on - state resistance of the device.

[0237] Figure 24 An example of the relationship between the external gate voltage bias (GaN chip control terminal bias) 2501 and the active gate voltage (internal gate voltage) 2502 according to an embodiment of the present invention is shown. When the external gate voltage signal initially rises (until the auxiliary gate transistor Vth), the auxiliary gate transistor has a high resistance. Most of the applied potential drops across the auxiliary gate transistor, and the potential of the active gate terminal remains near 0V. When the external gate voltage signal reaches the auxiliary gate transistor Vth, the resistance of the auxiliary transistor becomes small, and the potential of the active gate terminal starts to rise.

[0238] Thus, an increase in the threshold voltage is achieved in a GaN chip multi - block HEMT without affecting the on - state resistance of the device. A positive shift in the device threshold voltage (as shown in the graph 2500) is observed using this structure because not all of the potential applied to the external gate is transferred to the active gate (a portion of this potential is used to form the auxiliary 2DEG under the auxiliary gate), and only a portion is transferred to the terminal 12 connected to the active gate 10.

[0239] When the external gate 16 bias voltage reaches a pre-designed level, the pull-down circuit block 520 starts to operate and pulls the gate 15 of the auxiliary transistor towards the potential of the active transistor source terminal 8. The auxiliary transistor has a high resistance in this case, so any additional external gate potential drops across the auxiliary transistor, and the active gate terminal potential remains approximately constant as the external gate voltage signal rises, for example, constant at at least about 20V.

[0240] The designs of the current control block 530 and the pull-down circuit block 520 determine the potential at which the active gate terminal is clamped.

[0241] This document includes several illustrative examples of different embodiments having functional blocks 510, 520, 530. Note that the list of the examples is not exhaustive, and any combination of different embodiments of each block can be considered within the scope of the present invention. This includes the several examples of the auxiliary gate mentioned above. In addition, any or all of the above protection circuits and control circuits (overvoltage, overcurrent, Miller clamp) can also be combined with Figure 23 the functional blocks shown in

[0242] Figure 25 A schematic representation of an embodiment of the GaN chip 1000a of the proposed invention is shown. The auxiliary gate block 510a includes enhancement-mode low-voltage HEMTs, the current control block 530a includes resistors, and the pull-down circuit 520a includes HEMTs in a threshold multiplier configuration. The threshold multiplier configuration in this embodiment includes a voltage divider and a pull-down enhancement-mode HEMT, where the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the drain of the pull-down enhancement-mode HEMT and the gate terminal of the HEMT in the auxiliary gate block.

[0243] Figure 26 A schematic representation of another embodiment of the GaN chip 1000b of the proposed invention is shown, where the auxiliary gate block 510b includes enhancement-mode low-voltage HEMTs. The current control block 530b includes a resistor in parallel with an RC circuit. The parallel RC circuit can improve the dynamic characteristics of the device during turn-on and turn-off transients. The pull-down circuit 520b includes HEMTs in a threshold multiplier configuration with passive elements in parallel. The passive elements can improve the dynamic characteristics of the device during turn-on and turn-off transients.

[0244] Figure 27A schematic representation of an additional embodiment of the GaN chip 1000c of the proposed invention is shown. The auxiliary gate block 510c includes an enhancement-mode low-voltage HEMT and a Schottky or p-n diode in parallel. In this embodiment, a low on-state voltage diode is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. During the turn-off of the entire configuration where the gate terminal 10 of the active GaN transistor is connected to ground, the parallel diodes act as a pull-down network. When a positive bias (referred to as the on-state) is applied to the external gate terminal 16, the diodes will be reverse-biased and zero current will flow through them, thus not affecting the electrical characteristics of the entire high-voltage configuration. When a zero bias (off-state) is applied to the auxiliary gate 15, the diodes are forward-biased, and the off-state current flowing through them will discharge the gate capacitance of the active transistor, enabling the entire configuration to turn off. In the off-state, the gate of the active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. Therefore, the diodes are designed to have as low a turn-on voltage as possible, ideally a few millivolts. The current control block 530c includes a current source using a low-voltage depletion-mode HEMT and a resistor. The value of the resistor can be adjusted to set the maximum current level that can flow through the current source. The pull-down circuit 520c includes a HEMT in a threshold multiplier configuration.

[0245] Figure 28 A schematic representation of an additional embodiment of the GaN chip 1000d of the proposed invention is shown, where the auxiliary gate block 510d includes an enhancement-mode low-voltage HEMT. The current control block 530d includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 520d includes a HEMT in a threshold multiplier configuration.

[0246] Figure 29 A schematic representation of an additional embodiment of the GaN chip 1000e of the proposed invention is shown, where the auxiliary gate block 510e includes an enhancement-mode low-voltage HEMT. Additionally, in this embodiment, a second auxiliary transistor (which can advantageously be low-voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor, and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, the pull-down network during the turn-off of the entire configuration is the second auxiliary transistor. This is similar to Figure 27 the embodiment shown in, but uses a second auxiliary transistor instead of a diode. The current control block 530e includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 520e includes a HEMT in a threshold multiplier configuration.

[0247] Figure 301 shows a schematic representation of another embodiment of the proposed invention GaN chip 1000f, wherein the auxiliary gate block 510f comprises an enhancement mode low voltage HEMT. Figure 29 In the embodiment described in the embodiment of the present invention, the second auxiliary transistor is connected in parallel with the first auxiliary transistor. The current control block 530f includes a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520f includes a HEMT in a threshold multiplier configuration. In this embodiment, the threshold multiplier also includes a current source in parallel with one of the resistors in the voltage divider of the threshold multiplier circuit. The inclusion of the current source provides temperature stability in the clamping voltage value achieved on the active gate of the high voltage transistor 500 when the voltage signal on the external gate terminal is high.

[0248] Figure 31 A schematic representation of a further embodiment of the proposed invention GaN chip 1000j is shown, wherein the auxiliary gate block 510j comprises an enhancement mode low voltage HEMT. The current control block 530j comprises a current source using a low voltage depletion mode HEMT and a resistor. The pull-down circuit 520j comprises a HEMT in a threshold multiplier configuration, similar to the previous embodiment comprising a voltage divider and an enhancement mode pull-down HEMT. However, in this embodiment, the resistor on top of the voltage divider - connected to the drain terminal of the enhancement mode pull-down HEMT in the previous embodiment - is alternatively connected to the source terminal of the depletion mode HEMT used in the current source of the control block.

[0249] Figure 32 A block diagram schematically shows another embodiment of the proposed invention. In this embodiment, Figure 23 Compared with the embodiment shown in the figure, some additional functional blocks are included. In this embodiment, as in the previous embodiment, an auxiliary gate block, a current control block and a pull-down circuit block are included. An integrated active Miller clamp is also included.

[0250] An active Miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient. The active Miller clamp circuit may include a monolithically integrated Miller clamp transistor 570, a logic inverter 560, an external gate signal to logic signal converter 540, and / or a DC to DC block 550 that generates a suitable inverter VDD rail.

[0251] As shown in this embodiment, transistor 570 may include a low voltage enhancement mode HEMT. Logic inverter 560 may include a low voltage enhancement mode HEMT and a resistor (similar to Figure 16The inverter circuit shown). However, this is provided only as an example configuration, and other logic inverter designs may be used instead or in addition. The enhancement mode devices used in the inverter can be formed in the same process step as the active high voltage transistors. Therefore, the upper limit of the voltage signal that can be applied to the gate of the inverter transistor can be lower than the external gate signal. Vg to the logic block 540 can be used to reduce the external gate voltage signal to a voltage signal suitable for use with p-GaN technology enhancement mode HEMTs.

[0252] When the output of the inverter is high, the integrated Miller clamp transistor can receive a signal close to VDD at its gate terminal. Therefore, if the available VDD rail is higher than the peak gate voltage that the integrated clamp resistor can withstand, the DC / DC step 550 can be integrated into the GaN chip multi-block power device to reduce the VDD rail to the desired level.

[0253] Figure 33 A schematic representation of another embodiment of the GaN chip 3000a of the proposed invention is shown, where the auxiliary gate block 610a includes depletion mode low voltage HEMTs. The current control block 630a includes a resistive element. The pull-down circuit 620a includes HEMTs in a threshold multiplier configuration. The operation of the GaN chip multi-block power device shown in this embodiment is similar to Figure 25 the following operation of the device shown: When the external voltage signal exceeds a predetermined (by design) level, a clamped voltage signal is implemented at the active gate terminal (internal gate terminal) of the high voltage HEMT (main power heterojunction transistor) 500. Compared with the GaN chip power device 1000a, the use of depletion mode transistors in the auxiliary gate block in this embodiment may be less effective in providing an increased threshold voltage for the GaN chip power device 3000a. When the potential at the active gate is high and the potential at the external gate terminal is low, the low voltage depletion mode HEMT can be more effective in providing a turn-off path as part of the turn-off network of the device due to the presence of a channel in the depletion mode transistor.

[0254] Figure 34A schematic representation of an additional embodiment of the GaN chip 3000b of the proposed invention is shown, where the auxiliary gate block 610b includes depletion-mode low-voltage HEMTs. In this embodiment, a second auxiliary transistor (which can advantageously be a low-voltage transistor) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the second auxiliary transistor, and the source terminal 12 of the first auxiliary transistor is connected to the source (gate) terminal of the second auxiliary transistor. In this embodiment, during the turn-off of the high-voltage transistor 500, the second auxiliary transistor is included as an additional pull-down network. The current control block 630e includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 620e includes HEMTs in a threshold multiplier configuration.

[0255] Figure 35 A schematic representation of an additional embodiment of the GaN chip 3000d of the proposed invention is shown, where the auxiliary gate block 610d includes depletion-mode low-voltage HEMTs. Additionally, in this embodiment, a second depletion-mode auxiliary transistor (which can advantageously be low-voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, where the drain terminal 16 of the first auxiliary transistor is connected to the drain terminal of the auxiliary gate block, and the source terminal 12 of the first auxiliary transistor is connected to the source terminal of the second auxiliary transistor. The gate terminal of the second auxiliary transistor is connected to the source terminal of the high-voltage transistor 500. In this embodiment, during the turn-on of the high-voltage transistor 500, the second depletion-mode auxiliary transistor is included as an additional current path. When the external gate signal goes high, the second depletion-mode transistor is in the saturation mode and provides an additional conduction path for charging the gate-source capacitance of the high-voltage transistor 500. When the voltage at the active gate terminal rises above the threshold voltage of the second depletion-mode transistor, this conduction path becomes highly resistive. The current control block 630e includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 620e includes HEMTs in a threshold multiplier configuration.

[0256] Figure 36 A schematic representation of an additional embodiment of the GaN chip 5000b of the proposed invention is shown, where the auxiliary gate block 810b includes enhancement-mode low-voltage HEMTs. The current control block 830b includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 820b includes HEMTs in a threshold multiplier configuration, which includes a voltage divider and a pull-down enhancement-mode HEMT, where the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the active gate terminal instead of the drain of the pull-down enhancement-mode HEMT in the previous embodiments.

[0257] In Figure 37In this case, the top of the voltage divider is connected to the active gate terminal. The voltage divider includes a plurality of E-HEMT821c connected in series with a resistor between the source and the gate as shown in the foregoing embodiments. Although Figure 37 two series-connected HEMTs are shown, different numbers can be used. These HEMTs are a possible way to adjust the voltage level required at the active gate terminal before the pull-down enhancement-mode HEMT starts to operate.

[0258] Figure 38 Another method for adjusting the voltage level required at the active gate terminal before the pull-down enhancement-mode HEMT starts to operate is shown. Figure 38 An additional HEMT in the threshold multiplier configuration 821d is used.

[0259] Figure 39 A schematic representation of another embodiment of the GaN chip 6000a of the proposed invention is shown, in which the auxiliary gate block 910a includes enhancement-mode low-voltage HEMTs. The current control block 930a includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 920a includes HEMTs in a threshold multiplier configuration, which includes a voltage divider, where the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT (similar to the foregoing embodiments). However, in this embodiment, the voltage divider is connected to the external gate terminal instead of the gate terminal of the auxiliary transistor. Additionally, an additional HEMT in the threshold multiplier configuration can be included between the gate and source terminals of the enhancement-mode pull-down HEMT. This additional threshold multiplier is used to limit the voltage at the gate terminal of the pull-down transistor. This additional threshold multiplier can alternatively be implemented using one or more series-connected diodes.

[0260] Figure 40 A schematic representation of another embodiment of the GaN chip 6000b of the proposed invention is shown, in which the auxiliary gate block 910b includes enhancement-mode low-voltage HEMTs. The current control block 930b includes a current source using a low-voltage depletion-mode HEMT and a resistor. The pull-down circuit 920b includes a pull-down enhancement-mode HEMT whose gate is connected to the output of a voltage divider (similar to other embodiments). In this embodiment, the voltage divider is connected to the external gate terminal and consists of a current source and HEMTs in a threshold multiplier configuration. The current source is implemented using a low-voltage depletion-mode HEMT and a resistor. The output of the voltage divider (voltage divider) is the gate of an additional low-voltage HEMT.

[0261] In another embodiment, the gate of the pull-down HEMT can preferably be controlled by an additional external signal through the VG to Vlogic regulator as described above, or the gate of the pull-down HEMT can be controlled by the output of an additional circuit integrated on the GaN device, which provides functions such as overcurrent protection, undervoltage lockout, power supply overvoltage protection, logic inverter, or others.

[0262] Figure 41 An interleaved device layout including an auxiliary gate structure of another embodiment of the present disclosure is shown. Many features of this embodiment are similar to those Figure 21 shown, and thus have the same reference numerals, namely, the active gate terminal 10, the low-voltage source terminal 8, the high-voltage drain terminal 9, the first additional terminal 16, and the second additional terminal 12. The source pad metal 18, the drain pad metal 19, and the gate pad metal 20 are also shown in this figure. However, in this embodiment, different from the gate pad metal 20 that is directly in contact with the gate fingers 10 in the prior art devices, it is connected to the auxiliary gate terminal 16. The gate fingers in the interleaved structure are directly connected to the second additional terminal 12. Note that in this layout, as in the cross-section of the previous embodiment, an isolation layer exists between the auxiliary gate and the 2DEG in the active device. The additional operation blocks in the device are also shown: the auxiliary gate block 510, the pull-down circuit block 520, and the current control block 530. The different blocks can be connected using the interconnect metal layer 210.

[0263] Figure 42 An interleaved device layout of another embodiment of the present disclosure is shown, where the auxiliary gate and the terminal region are located under the source pad metal. Similarly, these circuits can be located under the gate pad or the drain pad (not shown). Many features of this embodiment are similar to those Figure 41 shown, and thus have the same reference numerals, namely, the active gate terminal 10, the low-voltage source terminal 8, the high-voltage drain terminal 9, the first additional terminal 16, the second additional terminal 12, the source pad metal 18, the drain pad metal 19, the gate pad metal 20, the auxiliary gate block 510, the pull-down circuit block 520, the current control block 530, and the interconnect metal 210. However, in this embodiment, the auxiliary gate block, the current control block, and the pull-down circuit block are located under the source pad metal 18. The via metal 220 can connect the blocks at different metal layers in the process. Compared with the prior art design, less additional die area will be required to include the additional blocks. Note that in this illustration, the additional blocks are located under the source pad metal, however, the present disclosure is intended to include designs where the additional blocks can be located under other pads existing in the integrated circuit layout.

[0264] Figure 43A block diagram showing another embodiment of the proposed disclosure, in which any one embodiment of the GaN chip power device 35 is in a half-bridge configuration, where the external gates of two power devices (high side and low side) are connected to a gate drive block, which in turn is connected to a logic block. The different components and blocks included in the figure can be discrete components or monolithically connected. This shows different examples of possible monolithic integration 36, 37, 38, while using the concept of an auxiliary gate.

[0265] Figure 44 A schematic circuit representation showing another embodiment of the proposed disclosure, in which the GaN chip power device 35 according to the present disclosure is connected in a standard three-phase half-bridge configuration.

[0266] It should be understood that the above-mentioned auxiliary transistors of all embodiments can be low-voltage transistors or high-voltage transistors.

[0267] It should also be understood that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", and "beneath" and "above", "front" and "rear", "underlying", etc. may be used conventionally in this specification and do not imply a specific physical orientation of the overall device.

[0268] Although the present disclosure has been illustrated in terms of preferred embodiments as set forth above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Given the present disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Every feature disclosed or illustrated in this specification, whether alone or in any suitable combination with any other feature disclosed or illustrated herein, can be included in the present disclosure.

[0269] References

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Claims

1. A heterojunction device based on group III nitride semiconductors, comprising: A substrate; A group III nitride semiconductor region formed above the substrate, wherein the group III nitride semiconductor region includes a heterojunction, and the heterojunction includes at least one two-dimensional carrier of a second conductivity type; A first terminal operatively connected to the group III nitride semiconductor region; A second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the group III nitride semiconductor region; At least two discontinuous highly doped semiconductor regions of a first conductivity type, directly formed above the group III nitride semiconductor region and formed between the first terminal and the second terminal; and An active gate region formed above the at least two discontinuous highly doped semiconductor regions of a first conductivity type, wherein the active gate region contacts the at least two discontinuous highly doped semiconductor regions of a first conductivity type, and the group III nitride semiconductor region between the active gate region and the at least two discontinuous highly doped semiconductor regions of a first conductivity type is not in physical contact; Wherein the at least two discontinuous highly doped semiconductor regions of a first conductivity type are spaced apart from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension; and Wherein the device is a depletion-type device.

2. The heterojunction device according to claim 1, wherein In use, the at least two discontinuous highly doped semiconductor regions of a first conductivity type are operable to modulate the current path between the first terminal and the second terminal in the first dimension.

3. The heterojunction device according to claim 1, wherein, All of the at least two discontinuous highly doped semiconductor regions of a first conductivity type are connected to the active gate region.

4. The heterojunction device according to claim 1, wherein, The device is configured as a diode, and wherein the first terminal is electrically connected to the active gate region.

5. The heterojunction device according to claim 1, wherein, The device is configured as a diode, and wherein the second terminal is electrically connected to the active gate region.

6. The heterojunction device according to claim 4 or 5, wherein the spacing between the at least two discontinuous highly doped semiconductor regions of a first conductivity type is greater than 10 nm and less than 1000 nm.

7. The heterojunction device according to claim 1, wherein the at least two discontinuous highly doped semiconductor regions of a first conductivity type include a first group of at least two highly doped semiconductor regions and a second group of at least two highly doped semiconductor regions, and wherein the first group and the second group are spaced apart in the first dimension.

8. The heterojunction device according to claim 1, wherein the device is configured to have a first threshold voltage, the first threshold voltage defining the transition of the device from an off state to an on state, and wherein the value of the first threshold voltage can be controlled by adjusting the distance between the at least two discontinuous highly doped semiconductor regions of a first conductivity type.

9. The heterojunction device according to claim 8, wherein, The device is configured to have a second threshold voltage higher than the first threshold voltage, wherein, at the second threshold voltage, the at least one two-dimensional carrier of a second conductivity type is formed below the highly doped semiconductor region, thereby increasing the current or reducing the on-resistance.

10. The heterojunction device according to claim 1, wherein, The gate terminal extends in a third dimension between adjacent semiconductor regions among the at least two discontinuous highly doped semiconductor regions of the first conductivity type, wherein the third dimension is perpendicular to the first dimension and the second dimension.

11. The heterojunction device according to claim 1, wherein, The highly doped semiconductor region includes an ohmic metallization layer.

12. The heterojunction device according to claim 1, wherein, The highly doped semiconductor region includes a Schottky metallization layer.

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