Planar gate SiC MOSFET device structure and preparation method thereof

Abstract

The invention provides a planar gate SiC MOSFET device structure and a preparation method thereof, and relates to the technical field of semiconductor devices.The planar gate SiC MOSFET device structure sequentially comprises an N + type SiC substrate, an N type SiC epitaxial layer and an N type Si epitaxial layer from bottom to top, and a P type base region, an N + source region and a P + contact region are formed in the N type Si epitaxial layer and the N type SiC epitaxial layer through injection and annealing; the trench structure is formed in the JFET region, a P + shielding layer is formed at the bottom of the trench structure through injection, a gate dielectric layer is formed through oxidation growth, and a polycrystalline silicon gate structure is formed in the trench through deposition; the source metal layer and the gate metal layer are formed on the surface of the device structure, and the drain metal layer is formed on the back face of the N + type SiC substrate. The channel mobility of the device is improved, the on-resistance is reduced, the current on-resistance of the JFET region is reduced, and the through-current capability of the JFET region is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a planar gate SiC MOSFET device structure and a preparation method thereof. Background Art

[0002] The planar gate SiC MOSFET device structure is widely used in high-power and high-frequency electronic devices. However, the existing planar gate SiC MOSFETs have the following problems: 1. Low inversion layer (channel) mobility: In traditional SiC MOSFETs, due to the properties of the SiC material, the electron mobility in the channel is low, resulting in a high on-resistance of the device and affecting its performance.

[0003] 2. High on-resistance: As the device size decreases, the channel resistance in the traditional planar gate SiC MOSFET structure is still high, which limits the efficiency of the device.

[0004] 3. Inherent JFET region and JFET resistance: The JFET region in the planar gate SiC MOSFET structure will cause an increase in resistance as the size shrinks. Especially in small-size designs, this JFET resistance becomes more and more serious, further affecting the device performance.

[0005] In order to overcome these problems, a new SiC MOSFET structure needs to be proposed to improve the channel mobility of the device, reduce the on-resistance, reduce the current on-resistance of the JFET region, and improve the current-carrying capacity of the JFET region. Summary of the Invention

[0006] In view of this, to solve the above problems. The purpose of the present invention is to provide a planar gate SiC MOSFET device structure and a preparation method thereof. By growing an N-type Si epitaxial layer on the N-type SiC epitaxial layer, the channel mobility of the MOSFET device is improved, the channel resistance of the device is reduced, the current conduction characteristics of the JFET region are improved, especially the resistance generated due to the reduction of the structure size is reduced, and the overall reliability of the device is enhanced, especially the risk of breakdown damage is reduced.

[0007] To achieve the above object, the present invention provides the following technical solutions: Based on the above object, in the first aspect, the present invention provides a planar gate SiC MOSFET device structure, including the following components: A substrate structure, which sequentially includes an N+-type SiC substrate (N-SiC SUB), an N-type SiC epitaxial layer (N-SiCEPI), and an N-type Si epitaxial layer (N-Si EPI) from bottom to top; P-base, the P-base extends downward through the N-Si epitaxial layer (N-Si EPI) and is partially embedded in the N-SiC epitaxial layer (N-SiC EPI); an N+ source region (N+) and a P+ contact region (P+) are formed on the top of the P-base, and the N+ source region (N+) and the P+ contact region (P+) simultaneously penetrate the lower surface of the N-Si epitaxial layer (N-Si EPI) and extend to the N-SiC epitaxial layer (N-SiC EPI); A trench structure formed in the JFET region, a P+ shielding layer is formed by implantation at the bottom of the trench structure, and a gate dielectric layer is formed by thermal oxidation. A polysilicon gate (gate poly) structure is formed by deposition inside the trench; A source metal layer and a gate metal layer formed on the surface of the device structure, and a drain metal layer formed on the back of the N+-type SiC substrate (N-SiCSUB).

[0008] As a further aspect of the present invention, the N-Si epitaxial layer is a layer of N-Si epitaxial layer grown on the upper surface of the N-SiC epitaxial layer before manufacturing the SiC MOSFET device.

[0009] As a further aspect of the present invention, a part of the P-base, the N+ source region (N+), and the P+ contact region (P+) is in the N-Si epitaxial layer (N-Si EPI), and another part is in the N-SiC epitaxial layer (N-SiC EPI).

[0010] As a further aspect of the present invention, the upper parts of the P-base, the N+ source region (N+), and the P+ contact region (P+) are located in the N-Si epitaxial layer (N-Si EPI), and the lower parts are located in the N-SiC epitaxial layer (N-SiC EPI).

[0011] As a further aspect of the present invention, the trench structure penetrates the N-Si epitaxial layer (N-SiEPI) through photolithography and etching and extends into the N-SiC epitaxial layer (N-SiC EPI).

[0012] As a further aspect of the present invention, the gate dielectric layer is a SiO2 layer formed by thermal oxidation, covering the surface of the channel region and extending to the sidewalls of the trench in the JFET region.

[0013] As a further aspect of the present invention, a polysilicon gate structure is formed by CVD process deposition inside the trench structure.

[0014] As a further solution of the present invention, the conductive channel of the MOSFET device structure is formed on the surface of the P-base region in the N-type Si epitaxial layer (N-SiEPI), and the gate dielectric layer is directly grown on the surface of the N-type Si epitaxial layer (N-Si EPI).

[0015] As a further solution of the present invention, the trench structure includes a U-shaped, V-shaped or stepped cross-sectional shape.

[0016] As a further solution of the present invention, the lateral extension range of the P+ shielding layer covers the projection area of the trench bottom.

[0017] In a second aspect, the present invention provides a method for manufacturing a planar gate SiC MOSFET device structure, including the following steps: a) Growing and forming an N-type Si epitaxial layer (N-Si EPI) on the upper surface of the N-type SiC epitaxial layer (N-SiC EPI); b) Forming a P-type base region (P-base), an N+ source region (N+), and a P+ contact region (P+) in the N-type Si epitaxial layer (N-Si EPI) and the N-type SiC epitaxial layer (N-SiC EPI) by implantation and annealing, with a part in the N-type Si epitaxial layer (N-Si EPI) and the other part in the N-type SiC epitaxial layer (N-SiC EPI); c) Forming a trench in the JFET region by photolithography and etching, implanting a P+ shielding layer at the bottom of the trench, oxidizing and growing a gate dielectric layer, and depositing a polysilicon gate (gate poly) structure inside the trench; d) Forming a source metal layer and a gate metal layer on the surface of the device structure, and forming a drain metal layer on the back of the N+-type SiC substrate (N-SiCSUB).

[0018] Compared with the prior art, a planar gate SiC MOSFET device structure and a manufacturing method thereof proposed by the present invention have the following beneficial effects: The planar-gate SiC MOSFET device structure and its manufacturing method provided by the present invention grow an N-type Si epitaxial layer on an N-type SiC epitaxial layer, changing the formation of the channel region and the gate dielectric layer above it from the traditional formation in the SiC epitaxial layer to the formation in the Si epitaxial layer, thereby significantly improving the channel mobility of the MOSFET device, enhancing the current-carrying capacity of the channel, and reducing the channel resistance of the device. At the same time, trenches are introduced in the JFET region. The bottom and side walls of the trenches have gate dielectric layers, and the trenches are filled with polysilicon and connected to the polysilicon above the channel region of the planar-gate SiC MOSFET. In this way, when the MOSFET is turned on, the voltage applied to the polysilicon gate makes the N-type SiC epitaxial layer and the N-type Si epitaxial layer adjacent to the side walls of the trenches become N-type accumulation regions, thereby reducing the current conduction resistance in the JFET region and improving the current-carrying capacity. In addition, by introducing a P+ shielding layer at the bottom of the trenches, the breakdown damage of the strong electric field to the region above the JFET and the trench gate dielectric layer is further improved, and the breakdown voltage and reliability of the device are enhanced.

[0019] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the description of the exemplary embodiments or related technologies. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. In the drawings: Figure 1 It is a schematic structural diagram of growing N_Si EPI on N_SiC EPI in the manufacturing method of the planar-gate SiC MOSFET device structure according to the embodiment of the present invention.

[0021] Figure 2 It is a schematic structural diagram of forming a P-base region, a P+ region, and an N+ source region in the manufacturing method of the planar-gate SiC MOSFET device structure according to the embodiment of the present invention.

[0022] Figure 3 It is a schematic structural diagram of etching to form trenches, implanting to form a P+ shielding layer, forming a gate dielectric layer through an oxidation process, and forming a gate poly deposition through a CVD process in the manufacturing method of the planar-gate SiC MOSFET device structure according to the embodiment of the present invention.

[0023] Figure 4The structural schematic diagram of the planar-gate SiC MOSFET device structure prepared by the preparation method of the planar-gate SiC MOSFET device structure according to the embodiment of the present invention is made.

[0024] Figure 5 The schematic diagram of the evolution of the trench shape in the preparation method of the planar-gate SiC MOSFET device structure according to the embodiment of the present invention.

[0025] Reference numerals: 1. N+-type SiC substrate; 2. N-type SiC epitaxial layer; 3. N-type Si epitaxial layer; 4. P-type base region; 5. N+ source region; 6. P+ contact region; 7. Trench structure; 8. P+ shielding layer; 9. Gate dielectric layer; 10. Polysilicon gate; 11. Source metal layer; 12. Drain metal layer. Detailed implementation manners

[0026] Next, in combination with the accompanying drawings and specific implementation manners, the present application will be further described. It should be noted that, on the premise of non-conflict, the following-described embodiments or technical features can be arbitrarily combined to form new embodiments.

[0027] To make the purpose, technical solution and advantages of the present invention clearer and more understandable, the following will further describe the embodiments of the present invention in detail in combination with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units inherently includes other steps or units.

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in combination with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0030] The flowchart shown in the accompanying drawings is only an example illustration, and does not necessarily include all the contents and operations / steps, nor does it necessarily need to be executed in the described order. For example, some operations / steps can also be decomposed, combined or partially merged, so the actual execution order may be changed according to the actual situation.

[0031] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0032] SiC MOSFET technology is a power semiconductor device technology based on silicon carbide material, with excellent characteristics such as high temperature, high voltage, and high frequency. The device structures of existing SiC MOSFETs mainly include: a channel region, a source region, a drain region, and a gate region. The channel region is composed of P-type SiC, the source region is composed of N+-type SiC, the drain region is composed of an N+-doped SiC substrate and a metal contact layer, and the gate region is composed of metal or polysilicon (Poly). However, in the existing planar-gate SiC MOSFETs, since the channel region of the SiC MOSFET is formed in the SiC layer, a prominent problem is that the inversion layer (channel) mobility of the device is low and the on-resistance is high. Moreover, compared with the trench-gate SiC MOSFET, the planar-gate SiC MOSFET structure has an inherent JFET region and JFET resistance, and as the structural design size becomes smaller and smaller, the JFET resistance becomes larger and larger. In view of this, the present invention proposes a planar-gate SiC MOSFET device structure and a preparation method thereof. An N-type Si is epitaxially grown above the N-type SiC EPI epitaxial layer, and the channel region of the planar-gate SiC MOSFET and the gate dielectric layer above the channel region are realized in the Si epitaxial layer instead of in the SiC epitaxial layer as in the conventional case, so that the channel mobility of the MOSFET device is greatly improved, the current-carrying capacity of the channel is enhanced, and the channel resistance of the device is greatly reduced; at the same time, trenches are introduced into the JFET region, and the bottom and side walls of the trenches have gate dielectric layers, and the trenches are filled with polysilicon and connected to the polysilicon above the channel region of the planar-gate SiC MOSFET. In this way, when the MOSFET is turned on, the voltage applied to the polysilicon gate makes the N-type SiC epitaxial layer and the N-type Si epitaxial layer adjacent to the side walls of the trenches become N-type accumulation regions, thereby reducing the current conduction resistance of the JFET region and improving the current-carrying capacity; in addition, a P+ shielding layer is introduced at the bottom of the trenches, which can significantly improve the breakdown damage of the strong electric field to the region above the JFET region and the trench gate dielectric layer, and improve the breakdown voltage and reliability of the device.

[0033] See Figures 1 to 5 As shown, the embodiment of the present invention provides a planar-gate SiC MOSFET device structure, including: A substrate structure, which sequentially includes an N+-type SiC substrate 1 (N-SiC SUB), an N-type SiC epitaxial layer 2 (N-SiC EPI), and an N-type Si epitaxial layer 3 (N-Si EPI) from bottom to top; P-type base region 4 (P-base), the P-type base region 4 extends downward through the N-type Si epitaxial layer 3 (N-Si EPI) and partially embeds into the N-type SiC epitaxial layer 2 (N-SiC EPI); an N+ source region 5 (N+) and a P+ contact region 6 (P+) are formed on the top of the P-type base region 4 (P-base), and the N+ source region 5 (N+) and the P+ contact region 6 (P+) simultaneously penetrate the lower surface of the N-type Si epitaxial layer 3 (N-Si EPI) and extend to the N-type SiC epitaxial layer 2 (N-SiC EPI); A trench structure 7 formed in the JFET region, a P+ shielding layer 8 is formed by implantation at the bottom of the trench structure 7, and a gate dielectric layer 9 is formed by oxidation growth. A polysilicon gate 10 (gate poly) structure is formed by deposition inside the trench; A source metal layer 11 and a gate metal layer formed on the surface of the device structure, and a drain metal layer 12 formed on the back of the N+-type SiC substrate 1 (N-SiCSUB).

[0034] Compared with the existing planar gate SiC MOSFET device structure where the channel region and the gate dielectric layer above the channel region are both realized in the N-type SiC epitaxial layer, the planar gate SiC MOSFET device structure provided by the present invention grows an additional layer of N-type Si epitaxial layer 3 on the N-type SiC epitaxial layer 2. The channel region of the MOSFET device and the gate dielectric layer 9 above the channel region are both realized in the N-type Si epitaxial layer 3. A trench structure 7 is introduced in the JFET region. The bottom and side walls of the trench structure 7 have a gate dielectric layer 9. The inside of the trench structure 7 is filled with polysilicon and is connected to the polysilicon above the channel region of the planar gate SiC MOSFET. A P+ shielding layer 8 is introduced at the bottom of the trench structure 7.

[0035] In this embodiment, the N-type Si epitaxial layer 3 is a layer of N-type Si epitaxial layer 3 grown to cover the upper surface of the N-type SiC epitaxial layer 2 before manufacturing the SiC MOSFET device. A part of the P-type base region 4 (P-base), the N+ source region 5 (N+), and the P+ contact region 6 (P+) are in the N-type Si epitaxial layer 3 (N-Si EPI), and the other part is in the N-type SiC epitaxial layer 2 (N-SiC EPI).

[0036] Among them, the upper parts of the P-type base region 4 (P-base), the N+ source region 5 (N+), and the P+ contact region 6 (P+) are located in the N-type Si epitaxial layer 3 (N-Si EPI), and the lower parts are located in the N-type SiC epitaxial layer 2 (N-SiC EPI).

[0037] In this embodiment, the trench structure 7 penetrates the N-type Si epitaxial layer 3 (N-Si EPI) and extends into the N-type SiC epitaxial layer 2 (N-SiC EPI) through photolithography and etching.

[0038] In this embodiment, the gate dielectric layer 9 is a SiO2 layer formed by thermal oxidation, covering the surface of the channel region and extending to the sidewalls of the trench in the JFET region. The polysilicon gate structure is deposited inside the trench structure 7 by CVD process.

[0039] In this embodiment, the conductive channel of the MOSFET device structure is formed on the surface of the P-base region in the N-type Si epitaxial layer 3 (N-Si EPI). The gate dielectric layer 9 is directly grown on the surface of the N-type Si epitaxial layer 3 (N-Si EPI); the lateral extension range of the P+ implantation shielding layer covers the projection area of the trench bottom.

[0040] In this embodiment, the trench structure 7 includes a U-shaped, V-shaped or stepped cross-sectional shape.

[0041] See Figures 1 to 4 As shown, the embodiment of the present invention also provides a preparation method for a planar gate SiC MOSFET device structure, including the following steps: a) Grow an N-type Si epitaxial layer 3 (N-Si EPI) on the upper surface of the N-type SiC epitaxial layer 2 (N-SiC EPI); b) Form a P-type base region 4 (P-base), an N+ source region 5 (N+) and a P+ contact region 6 (P+) in the N-type Si epitaxial layer 3 (N-Si EPI) and the N-type SiC epitaxial layer 2 (N-SiC EPI) by implantation and annealing, with a part in the N-type Si epitaxial layer 3 (N-Si EPI) and the other part in the N-type SiC epitaxial layer 2 (N-SiC EPI); c) Form a trench in the JFET region by photolithography and etching, implant a P+ shielding layer 8 at the bottom of the trench, and oxidize and grow a gate dielectric layer 9. A polysilicon gate 10 (gate poly) structure is deposited inside the trench; d) Form a source metal layer 11 and a gate metal layer on the surface of the device structure, and form a drain metal layer 12 on the back of the N+-type SiC substrate 1 (N-SiC SUB).

[0042] When preparing the planar gate SiC MOSFET device structure by the above preparation method, as Figure 1As shown, before fabricating the SiC MOSFET device, a layer of N-type Si epitaxial layer 3 is grown on the surface of the N-type SiC epitaxial layer 2; then, a P-type base region 4 (P-base), an N+ source region 5 (N+), and a P+ contact region 6 (P+) are formed in the N-type SiC epitaxial layer 2 and the N-type Si epitaxial layer 3 through implantation and annealing, that is, a part (upper part) of the P-type base region 4 (P-base), the N+ source region 5 (N+), and the P+ contact region 6 (P+) is in the N-type Si epitaxial layer 3 (N-Si EPI), and the other part (lower part) is in the N-type SiC epitaxial layer 2 (N-SiC EPI), as Figure 2 shown; then, a trench is formed in the JFET region through photolithography and etching, a P+ shielding layer 8 is formed at the bottom of the trench through implantation, a gate dielectric layer 9 is formed through an oxidation process (specifically noted that the gate oxide layer is also formed in the N-Si Epi epitaxial layer), and a polysilicon gate 10 (gate poly) is formed through a CVD process, as Figure 3 shown. Finally, through processes such as photolithography, etching, CVD, and sputtering, a source metal layer 11 and a gate metal layer (not shown in the figure) are formed on the surface of the device; through processes such as back thinning and metal sputtering, a device drain metal layer 12 is formed on the back of the N+-type SiC substrate 1 (N-SiC SUB), as Figure 4 shown.

[0043] Among them, the channel of the MOSFET is formed within the Si epitaxial layer (not within the SIC epitaxial layer), and the gate oxide layer above the channel is also formed within the Si epitaxial layer; the regions of the base / P+ / N+ and the trench both include the Si epitaxial layer and the SiC epitaxial layer.

[0044] For the planar gate SiC MOSFET device structure prepared by the preparation method of the present invention, an N-type Si is epitaxially grown above the N-type SiC EPI epitaxial layer, and the channel region of the planar gate SiC MOSFET and the gate dielectric layer above the channel region are changed from being realized in the SiC epitaxial layer conventionally to being realized in the Si epitaxial layer, so that the channel mobility of the MOSFET device is greatly improved, the current-carrying capacity of the channel is enhanced, and the channel resistance of the device is greatly reduced; at the same time, a trench is introduced in the JFET region, and there is a gate dielectric layer at the bottom and side walls of the trench. The trench is filled with polysilicon and is connected to the polysilicon above the channel region of the planar gate SiC MOSFET. In this way, when the MOSFET is turned on, the voltage applied to the polysilicon gate makes the N-type SiC epitaxial layer and the N-type Si epitaxial layer adjacent to the side wall of the trench become N-type accumulation regions, thereby reducing the current conduction resistance of the JFET region and improving the current-carrying capacity; in addition, by introducing a P+ shielding layer at the bottom of the trench, the breakdown damage of the strong electric field to the region above the JFET region and the trench gate dielectric layer can be significantly improved, and the breakdown voltage and reliability of the device are improved.

[0045] It should be noted that the evolution of the groove shape, as mentioned in this embodiment, is a U-shaped groove, but it can also be a V-shaped or stepped cross-sectional shape as shown in Figure 5 Any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention shall be included within the protection scope of the embodiments of the present invention.

[0046] In summary, the planar gate SiC MOSFET device structure and its manufacturing method provided by the present invention grow an N-type Si epitaxial layer on the N-type SiC epitaxial layer, changing the formation of the channel region and the gate dielectric layer above it from the traditional formation in the SiC epitaxial layer to the formation in the Si epitaxial layer, thereby significantly improving the channel mobility of the MOSFET device, enhancing the current-carrying capacity of the channel, and reducing the channel resistance of the device. At the same time, a groove is introduced in the JFET region. The bottom and side walls of the groove have a gate dielectric layer. The inside of the groove is filled with polysilicon and is connected to the polysilicon above the channel region of the planar gate SiC MOSFET. In this way, when the MOSFET is turned on, the voltage applied to the polysilicon gate makes the N-type SiC epitaxial layer and the N-type Si epitaxial layer near the side wall of the groove become N-type accumulation regions, thereby reducing the current conduction resistance of the JFET region and improving the current-carrying capacity. In addition, by introducing a P+ shielding layer at the bottom of the groove, the breakdown damage of the strong electric field to the region above the JFET region and the gate dielectric layer of the groove is further improved, and the breakdown voltage and reliability of the device are enhanced.

[0047] The above are the exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein do not need to be executed in any specific order. In addition, although the elements disclosed in the embodiments of the present invention can be described or claimed in individual form, they can also be understood as plural unless clearly limited to the singular.

[0048] It should be understood that, as used herein, unless the context clearly supports an exception, the singular form "a" is also intended to include the plural form. It should also be understood that the "and / or" used herein refers to any and all possible combinations including one or more of the associated listed items. The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0049] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A planar-gate SiC MOSFET device structure, characterized in that, It includes the following components: A base structure, which sequentially includes an N+-type SiC substrate, an N-type SiC epitaxial layer, and an N-type Si epitaxial layer from bottom to top; A P-type base region, which extends downward through the N-type Si epitaxial layer and partially embeds into the N-type SiC epitaxial layer; an N+-type source region and a P+-type contact region are formed on the top of the P-type base region, and the N+-type source region and the P+-type contact region simultaneously penetrate the lower surface of the N-type Si epitaxial layer and extend to the N-type SiC epitaxial layer; A trench structure formed in the JFET region, a P+-type shielding layer is formed by implantation at the bottom of the trench structure, and a gate dielectric layer is formed by thermal oxidation. A polysilicon gate structure is formed by deposition inside the trench; A source metal layer and a gate metal layer formed on the surface of the device structure, and a drain metal layer formed on the back surface of the N+-type SiC substrate.

2. The planar-gate SiC MOSFET device structure according to claim 1, wherein The N-type Si epitaxial layer is an N-type Si epitaxial layer grown to cover the upper surface of the N-type SiC epitaxial layer before manufacturing the SiC MOSFET device.

3. The planar-gate SiC MOSFET device structure according to claim 1, wherein A part of the P-type base region, the N+-type source region, and the P+-type contact region is in the N-type Si epitaxial layer, and the other part is in the N-type SiC epitaxial layer.

4. The planar-gate SiC MOSFET device structure according to claim 1, characterized in that, The trench structure penetrates the N-type Si epitaxial layer and extends into the N-type SiC epitaxial layer through photolithography and etching.

5. The planar-gate SiC MOSFET device structure according to claim 4, characterized in that, The gate dielectric layer is a thermally oxidized SiO2 layer, which covers the surface of the channel region and extends to the sidewall of the trench in the JFET region.

6. The planar-gate SiC MOSFET device structure according to claim 5, wherein, A polysilicon gate structure is formed by CVD deposition inside the trench structure.

7. The planar-gate SiC MOSFET device structure according to claim 1, wherein The conductive channel of the MOSFET device structure is formed on the surface of the P-base region in the N-type Si epitaxial layer, and the gate dielectric layer is directly grown on the surface of the N-type Si epitaxial layer.

8. The planar gate SiC MOSFET device structure according to claim 1, characterized in that, The trench structure includes a U-shaped, V-shaped, or stepped cross-sectional shape.

9. The planar-gate SiC MOSFET device structure according to claim 1, wherein, The lateral extension range of the P+-type shielding layer covers the projection area of the trench bottom.

10. A method for fabricating a planar-gate SiC MOSFET device structure, characterized in that, Implement the method based on the planar-gate SiC MOSFET device structure according to any one of claims 1-9, and the method includes the following steps: a) Grow and form an N-type Si epitaxial layer on the upper surface of the N-type SiC epitaxial layer; b) Form a P-type base region, an N+-type source region, and a P+-type contact region in the N-type Si epitaxial layer and the N-type SiC epitaxial layer by implantation and annealing, with a part in the N-type Si epitaxial layer and the other part in the N-type SiC epitaxial layer; c) Form a trench in the JFET region through photolithography and etching, form a P+-type shielding layer by implantation at the bottom of the trench, and form a gate dielectric layer by thermal oxidation. A polysilicon gate structure is formed by deposition inside the trench; d) Form a source metal layer and a gate metal layer on the surface of the device structure, and form a drain metal layer on the back surface of the N+-type SiC substrate.

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