A method for preparing a terminal structure and a chip

Abstract

The present application belongs to the technical field of power devices and provides a method for preparing a terminal structure and a chip, wherein an N-type drift region is formed on the front surface of an N-type silicon carbide substrate, a main junction is formed on the N-type drift region, and a tail trench is formed by etching in a preset area at the end of the main junction, so that the first side tilt angle of the tail trench is less than 16°, and the second side wall of the tail trench extends to the edge of the chip, wherein a field limiting ring area is provided between the first side of the tail trench and the main junction, thereby only requiring the addition of a junction terminal extension area and a mask process for the tail trench, and combining the field limiting ring, the junction terminal extension area and the trench structure to effectively shorten the terminal length and reduce the area occupied by the chip while ensuring the voltage resistance performance of the device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular relates to a method for preparing a terminal structure and a chip. Background Art

[0002] As a new generation of wide-bandgap semiconductor materials, silicon carbide exhibits excellent performance in harsh environments such as high voltage, high temperature, and high frequency, and therefore holds broad application prospects in power electronics, rail transportation, and other fields. However, due to the limited size of semiconductor devices, electric field concentration occurs at the edge of the main junction, which can easily lead to premature device breakdown and reduce the device's voltage resistance. To alleviate this problem, terminal protection structures are often installed at the device edge. Common terminal structures include field plates, field-limiting rings, and junction terminal extensions.

[0003] While traditional field-limiting ring (FLR) termination structures can effectively increase device breakdown voltage, they require multiple FLR rings, resulting in a large chip footprint and increased production costs. Junction termination extension technology, while capable of reducing termination length, is inefficient in reducing surface electric fields, resulting in a relatively large termination area, high sensitivity to implantation dose, and a narrow process window. Summary of the Invention

[0004] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a terminal structure and a chip, by forming a tail groove in the N-type drift region and etching the tail groove so that the first side wall inclination angle is less than 16°, thereby effectively reducing the terminal length while ensuring the voltage resistance and reducing the terminal occupied area.

[0005] A first aspect of an embodiment of the present application provides a method for preparing a terminal structure, the method comprising:

[0006] Providing an N-type silicon carbide substrate, and forming an N-type drift region on a front surface of the N-type silicon carbide substrate;

[0007] forming a main junction on the N-type drift region;

[0008] A tail trench is formed by etching in a preset end region of the main junction; wherein the first side tilt angle of the tail trench is less than 16°, and a field limiting ring region is formed between the first side of the tail trench and the main junction.

[0009] In some embodiments, before etching the predetermined end region of the main junction to form the tail trench, the method further includes:

[0010] Implanting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein the field limiting ring structure includes a plurality of spaced field limiting rings;

[0011] P-type impurities are superimposedly implanted into the field limiting ring region to form a junction termination extension region; wherein the junction termination extension region covers the field limiting ring region and extends to the tail trench.

[0012] In some embodiments, after etching the predetermined end region of the main junction to form a tail trench, the method further includes:

[0013] Implanting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein the field limiting ring structure includes a plurality of spaced field limiting rings;

[0014] P-type impurities are superimposedly implanted into the field limiting ring region to form a junction termination extension region; wherein the junction termination extension region covers the field limiting ring region and extends to the tail trench.

[0015] In some embodiments, the step of implanting P-type impurities into the field limiting ring region to form the field limiting ring structure includes:

[0016] Multiple masks and multiple doping ion implantation processes are used to implant P-type impurities into predetermined areas of the field limiting ring region to form multiple spaced field limiting rings; wherein, the junction depth of the field limiting ring is 1 μm, and the junction concentration of the field limiting ring is approximately skewed, with the highest concentration near the interface.

[0017] In some embodiments, the step of superimposing and implanting P-type impurities in the field limiting ring region to form a junction termination extension region includes:

[0018] P-type impurities are superimposedly implanted into the field limiting ring region to form a junction terminal extension region covering the field limiting ring region; wherein the doping concentration of the junction terminal extension region is box-shaped.

[0019] In some embodiments, after the P-type impurities are superimposedly implanted into the field limiting ring region to form a junction termination extension region, the method further includes:

[0020] A field limiting ring isolation trench is formed by etching an area on each field limiting ring, and an insulating dielectric material is filled in the field limiting ring isolation trench; wherein the depth of the field limiting ring isolation trench is less than or equal to the thickness of the junction terminal extension region.

[0021] In some embodiments, after etching the predetermined end region of the main junction to form a tail trench, the method further includes:

[0022] Depositing an insulating dielectric material to form an insulating dielectric material layer; wherein the insulating dielectric material layer fills the tail trench and covers the area between the main junction end and the chip edge;

[0023] A first electrode layer is formed in contact with the main junction, and a second electrode layer is formed on the back surface of the N-type silicon carbide substrate.

[0024] In some embodiments, etching a predetermined region at the end of the main junction to form a tail trench includes:

[0025] A hard mask is used to define the tail groove area, and under the protection of the hard mask, a dry etching process is adjusted to etch the tail groove area on the N-type drift region to form the tail groove; wherein the first side tilt angle of the tail groove is related to the etching time, etching ion gas ratio, energy, angle and thickness of the hard mask of the dry etching process.

[0026] In some embodiments, etching a predetermined region at the end of the main junction to form a tail trench includes:

[0027] A hard mask or photoresist is used to define the tail groove area, and a wet etching process is used to etch the tail groove area on the N-type drift region under the protection of the hard mask to form the tail groove; wherein the first side tilt angle of the tail groove is related to the etching time, etching solution concentration, energy, and thickness of the hard mask or photoresist of the wet etching process.

[0028] A second aspect of an embodiment of the present application further provides a chip, comprising a silicon carbide power device, wherein the silicon carbide power device comprises a terminal structure prepared by the method for preparing a terminal structure as described in any one of the above items.

[0029] The beneficial effects of the embodiments of the present application are as follows: an N-type drift region is formed on the front side of the N-type silicon carbide substrate, a main junction is formed on the N-type drift region, and a tail trench is formed by etching in a preset area at the end of the main junction, so that the first side tilt angle of the tail trench is less than 16°, and the second side wall of the tail trench extends to the edge of the chip, wherein a field limiting ring region is provided between the first side of the tail trench and the main junction, thereby only requiring the addition of a junction terminal extension region and a mask process for the tail trench, and combining the field limiting ring, the junction terminal extension region and the trench structure to effectively shorten the terminal length and reduce the area occupied by the chip while ensuring the voltage resistance performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic flow chart of a method for preparing a terminal structure provided in an embodiment of the present application;

[0031] Figure 2 This is a schematic flow chart of a method for preparing a terminal structure provided in an embodiment of the present application;

[0032] Figure 3 This is a schematic flow chart of a method for preparing a terminal structure provided in an embodiment of the present application;

[0033] Figure 4This is a schematic flow chart of a method for preparing a terminal structure provided in an embodiment of the present application;

[0034] Figure 5 This is a schematic flow chart of a method for preparing a terminal structure provided in an embodiment of the present application;

[0035] Figure 6 This is a schematic diagram of a process for preparing a terminal structure provided in an embodiment of the present application;

[0036] Figure 7 This is a schematic diagram of a process for preparing a terminal structure provided in an embodiment of the present application;

[0037] Figure 8 This is a schematic diagram of a process for preparing a terminal structure provided in an embodiment of the present application;

[0038] Figure 9 This is a schematic diagram of a process for preparing a terminal structure provided in an embodiment of the present application;

[0039] Figure 10 1 is a schematic structural diagram of a terminal structure prepared by the method for preparing a terminal structure provided in an embodiment of the present application;

[0040] Figure 11 Schematic diagram of the voltage resistance of the silicon carbide device terminal structure provided by the embodiment of the present application and the traditional terminal structure;

[0041] Figure 12 It is a schematic diagram of the electric field distribution of the traditional terminal structure;

[0042] Figure 13 and Figure 14 Schematic diagram of the electric field distribution of the terminal structure of the silicon carbide device provided in an embodiment of the present application;

[0043] Figure 15 This is a schematic diagram of the relationship between the inclination angle of the tail groove of the terminal structure and the withstand voltage provided by the embodiment of the present application;

[0044] Figure 16 This is a schematic diagram of the relationship between the JTE doping and withstand voltage of the terminal structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0046] While existing field-limiting ring (FLR) termination structures can improve device breakdown voltage, they require multiple FLR rings, resulting in a large chip footprint and increased production costs. Furthermore, while junction termination extension technology can reduce termination length, its effectiveness in reducing surface electric fields is low, resulting in a relatively large termination area and ineffective chip utilization.

[0047] In order to solve the above technical problems, the present invention provides a method for preparing a terminal structure. Figure 1 、 Figure 6-9 As shown, the method for preparing the terminal structure in this embodiment at least includes steps S100 to S300.

[0048] In step S100 , an N-type silicon carbide substrate 210 is provided, and an N-type drift region 220 is formed on a front surface of the N-type silicon carbide substrate 210 .

[0049] In step S200 , a main junction 310 is formed on the N-type drift region 220 .

[0050] In step S300 , etching is performed at a predetermined end region of the main junction 310 to form a tail trench 710 .

[0051] In this embodiment, a tail trench 710 with a first tilt angle of less than 16° is formed by etching a predetermined region at the end of the main junction 310. The predetermined field-limiting ring region is defined between the first side of the tail trench 710 and the main junction 310. The tail trench 710 interrupts the junction termination extension within the predetermined field-limiting ring region, transforming the original cylindrical junction into a planar junction. This reduces electric field concentration and significantly improves the device's withstand voltage. While maintaining the same withstand voltage, the width of the terminal structure in this embodiment is smaller than that of a conventional field-limiting ring terminal, significantly saving chip area.

[0052] In some embodiments, the second sidewall of the tail trench 710 extends to the edge of the chip.

[0053] In some embodiments, the first sidewall of the tail trench 710 is close to the preset field limiting ring region, and the first sidewall inclination angle is the angle between the first sidewall of the tail trench 710 and the horizontal plane of the N-type drift region 220. In a 1200V withstand voltage device, a safety margin of 20% is generally required, so the actual withstand voltage is greater than 1500V. Figure 15As shown in the model simulation diagram in FIG, when the angle between the first sidewall of the tail trench 710 and the horizontal plane of the N-type drift region 220 is less than 16 degrees, the breakdown voltage of the withstand voltage device is greater than 1500 V. By providing the tail trench 710 with a first tilt angle less than 16°, the junction termination extension region within the predetermined field-limiting ring region is interrupted, transforming the original cylindrical junction into a planar junction, reducing electric field concentration, and thus significantly improving the withstand voltage of the device. Under the same withstand voltage requirement, the width of the terminal structure in this embodiment is smaller than that of a traditional field-limiting ring terminal, which can significantly save chip area.

[0054] In some embodiments, combined Figure 2 As shown, step S300: before etching the predetermined end region of the main junction 310 to form the tail trench 710, it also includes steps S410 and S420.

[0055] In step S410 , P-type impurities are implanted into the field limiting ring region to form a field limiting ring structure.

[0056] In this embodiment, combined with Figure 6 and Figure 7 As shown, before etching the tail trench 710, Figure 6 and Figure 7 Based on the schematic structure (a) in FIG, a field limiting ring structure can be formed by injecting P-type impurities into the field limiting ring region through an ion implantation process, and the obtained Figure 6 and Figure 7 Schematic structure (b) in FIG. 1 , wherein the main junction 310 in step S200 and the field limiting ring structure in step S410 can share the same mask, thus saving one mask.

[0057] Combine Figure 6 and Figure 7 In the schematic structure (b), the field limiting ring structure includes a plurality of spaced field limiting rings 410. The width of the plurality of spaced field limiting rings 410 can be determined by the pattern of the ion implantation mask. The ion implantation depth and ion doping concentration of the plurality of spaced field limiting rings 410 can also be different by using multiple masks.

[0058] In step S420 , P-type impurities are superimposedly implanted into the field limiting ring region to form a junction termination extension region 510 .

[0059] In this embodiment, combined with Figure 6 and Figure 7 In the schematic structure (c), multiple junction termination extension regions 510 cover the field limiting ring area and extend to the tail trench 710.

[0060] In some embodiments, combined Figure 3As shown, step S300: after etching the predetermined end region of the main junction to form a tail trench, it also includes steps S410 and S420.

[0061] In step S410 , P-type impurities are implanted into the field limiting ring region to form a field limiting ring structure.

[0062] Combine Figure 8 As shown, in Figure 8 An etching mask 602 is formed on the basis of the schematic structure (a) in FIG. 1 , and etching is performed under the cover of the etching mask 602 to obtain Figure 8 In the schematic structure (b), after the etching process of the tail trench 710 is completed, P-type impurities are implanted into the field limiting ring region by an ion implantation process to form a field limiting ring structure, and the Figure 8 In the schematic structure (c), the field limiting ring structure includes a plurality of spaced field limiting rings 410 .

[0063] In some embodiments, combined Figure 8 As shown in the schematic structure (c) in FIG, the inclination angle of the first sidewall of the tail trench 710 is less than 16°, and the second side of the tail trench 710 extends to the edge of the chip.

[0064] In step S420 , P-type impurities are superimposedly implanted into the field limiting ring region to form a junction termination extension region.

[0065] In this embodiment, combined with Figure 8 As shown in the schematic structure (d) in FIG, the junction termination extension region 510 covers the field limiting ring region and extends to the tail trench 710.

[0066] In some embodiments, the order of step S410 and step S420 can be swapped.

[0067] In some embodiments, step S300 may also be provided between step S410 and step S420.

[0068] In some embodiments, the JTE junction depth concentration of the field limiting ring 410 has a typical box-shaped distribution.

[0069] In some embodiments, the JTE junction depth of the field limiting ring 410 is about 0.5 μm.

[0070] In some embodiments, the sidewall inclination angle of the field limiting ring 410 is less than 90°, which can reduce the electric field concentration caused by the curvature effect.

[0071] In some embodiments, the depth of the tail trench 710 is in the range of 0.6-0.7 μm.

[0072] In some embodiments, the second sidewall inclination angle of the tail trench 710 ranges from 0° to 90°.

[0073] In some embodiments, combined Figure 8 As shown in the schematic structure (d) in FIG, the second sidewall inclination angle of the tail trench 710 is 0°, and the second side of the tail trench 710 extends to the edge of the chip.

[0074] In some embodiments, the second sidewall of the tail trench 710 has an inclination angle of 90°.

[0075] In some embodiments, the junction termination extension region 510 extends from the end of the main junction 310 beyond the field limiting ring 410 by a distance in the range of 15-20 μm.

[0076] In some embodiments, a junction terminal extension region 510 (i.e., a JTE structure) can be formed by superimposing P-type dopant ions (e.g., aluminum ions) on the field limiting ring region. The junction depth of the junction terminal extension region 510 is less than or equal to three-fifths of the junction depth of the field limiting ring 410.

[0077] In some embodiments, in step S420, the junction termination extension region 510 includes a lightly doped region surrounding the main junction 310, with a doping concentration of typically 10 16 cm -3 ~10 18 cm -3 .

[0078] In some embodiments, in step S420, the doping concentration of the junction termination extension region 510 gradually decreases from the main junction 310 outward. This can be formed through multiple masks and multiple ion implantation processes, and the depth of the junction termination extension region 510 can also gradually decrease from the main junction 310 outward. When a reverse bias is applied, the main junction depletion layer laterally expands to the JTE region, causing the electric field distribution to "disperse" outward from the edge of the main junction, distributing the high voltage over a longer lateral distance. In addition, the tail trench 710 truncates the junction termination extension region 510, transforming the original cylindrical junction into a planar junction, reducing electric field concentration, and thus significantly improving the device's withstand voltage. Under the same withstand voltage requirement, the width of the terminal structure in this embodiment is smaller than that of a traditional field-limiting ring terminal, which can significantly save chip area.

[0079] In some embodiments, multiple P-type dopant ion implantations with different energies can be performed to gradually reduce the depth of the junction terminal extension region 510 from the main junction 310 outward, thereby achieving a depth-gradient JTE structure.

[0080] In some embodiments, in step S420, multiple junction termination extension regions 510 are provided on the N-type drift region 220. These multiple junction termination extension regions 510 can introduce different amounts of additional charge in different regions, further optimizing the electric field distribution and improving the withstand voltage capability. The junction termination extension regions 510 require high process control, requiring precise control of parameters such as ion implantation dose and depth to ensure that the doping concentration and width of the extension region meet design requirements.

[0081] In some embodiments, in step S410 , P-type dopant ions may be implanted multiple times on the N-type drift region 220 , so that the junction concentration of the field limiting ring 410 is approximately skewed, with the highest concentration near the interface.

[0082] In this embodiment, the junction concentration of the field limiting ring 410 is approximately skewed and may be an asymmetric Gaussian distribution. P-type doping ions may be implanted into the field limiting ring region using a variety of P-type impurities, resulting in a higher concentration near the surface. During the implantation, ions at the edge of the mask may be scattered into the bottom of the mask, resulting in a higher concentration near the interface than in the central region. High-temperature annealing causes the implanted ions to diffuse toward the surface and laterally, further enhancing the concentration near the interface.

[0083] In some embodiments, P-type dopant ions are implanted into the field limiting ring region using a variety of P-type impurities. The implantation concentrations of the plurality of field limiting rings 410 are laterally graded or multi-level distributed, which can smooth the electric field peak.

[0084] In some embodiments, the field limiting ring 410 is a P-type ring, and the junction depth of the field limiting ring 410 is about 1 μm.

[0085] In some embodiments, a P-type ring is a commonly used terminal structure in power semiconductor devices. It is a P-type ring structure with the same type of doping located near the main junction 310. Under reverse bias, the electric lines of force generated by the ionized acceptors in the P-type ring interact with the electric lines of force emitted by the ionized donors in the N region of the main junction 310, effectively introducing additional charges near the main junction 310. The electric field generated by these additional charges is in the opposite direction to the electric field of the main junction 310, thereby weakening the electric field peak of the main junction 310, reducing the curvature effect of the main junction 310, expanding the depletion region width, optimizing the electric field distribution, and increasing the breakdown voltage of the device.

[0086] In some embodiments, there may be one or more P-type rings, which may be formed in the same process as the main junction 310. By adjusting process parameters such as the spacing between the P-type rings, junction depth, and ion implantation concentration, the voltage resistance can be adjusted. The P-type ring structure is relatively simple to design, requiring relatively low process implementation difficulty, and can be formed by diffusion simultaneously with the main junction 310, eliminating the need for additional process steps.

[0087] In some embodiments, the number of P-type rings is greater than 2, and can be set to 4 or 5.

[0088] In some embodiments, a tail trench 710 is formed at the end of the JTE structure. The depth of the tail trench 710 is approximately 0.6-0.7 μm, the trench angle is less than 16 degrees, and the interior of the trench is filled with an insulating dielectric. This effectively reduces the terminal length and reduces the area occupied by approximately 40%-60% while maintaining the device's withstand voltage performance. This process only requires the addition of masking steps for the JTE and trench, resulting in a simple and low-cost process.

[0089] Combine Figure 16 As shown, the doping dose of the junction terminal extension region 510 is 3.5E12-4.0E12cm -2 When the breakdown voltage of the voltage-resistant device is greater than 1500V, by setting the angle between the first side wall of the tail trench 710 and the horizontal plane of the N-type drift region 220 to be less than 16 degrees, the doping dose of the junction terminal extension region 510 can have a wider ion injection range, reducing the influence of the voltage-resistant range of the device on the doping concentration, which is beneficial to improving the voltage-resistant stability of the device.

[0090] In some embodiments, step S410: implanting P-type impurities into the field limiting ring region to form a field limiting ring structure includes: using multiple masks and multiple doping ion implantation processes to implant P-type impurities into predetermined regions of the field limiting ring region to form a plurality of spaced field limiting rings 410 .

[0091] In this embodiment, the junction depth of the field limiting ring 410 is 1 μm, and the junction concentration of the field limiting ring 410 presents an approximately skewed distribution, with the highest concentration near the interface.

[0092] In some embodiments, step S420 : superimposing and implanting P-type impurities in the field limiting ring region to form a junction termination extension region 510 , includes superimposing and implanting P-type impurities in the field limiting ring region to form a junction termination extension region 510 covering the field limiting ring region.

[0093] In this embodiment, the doping concentration of the junction termination extension region 510 is box-shaped.

[0094] In some embodiments, combined Figure 4 As shown, step S410: superimposing and implanting P-type impurities in the field limiting ring region to form a junction terminal extension region, and then further comprising: etching the region on each of the field limiting rings 410 to form a field limiting ring isolation trench 720, and filling the field limiting ring isolation trench 720 with an insulating dielectric material.

[0095] In this embodiment, if Figure 10As shown, the depth of the field-limiting ring isolation trench is less than or equal to the thickness of the junction terminal extension region. Each field-limiting ring 410 is provided with a field-limiting ring isolation trench 720, resulting in a concave vertical cross-section of the field-limiting ring 410. This helps extend the length of the JTE structure between the main junction 310 and the chip edge, improving the device's withstand voltage performance, effectively shortening the terminal length, and reducing chip area.

[0096] In some embodiments, the field limiting ring isolation trench 720 and the tail trench 710 can share the same mask. Figure 6 、 Figure 7 、 Figure 9 In the schematic structure (c) in FIG, the field limiting ring 410 is etched through an etching mask to obtain a field limiting ring isolation trench 720 . The depth of the field limiting ring isolation trench 720 is the same as that of the tail trench 710 .

[0097] In some embodiments, combined Figure 5 As shown, step S300: after etching the predetermined end region of the main junction to form a tail trench, it also includes steps S510 and S520.

[0098] In step S510 , an insulating dielectric material is deposited to form an insulating dielectric material layer.

[0099] In this embodiment, combined with Figure 6-9 As shown in the schematic structure (e) in FIG, the insulating dielectric material layer 610 fills the tail trench 710 and covers the area between the end of the main junction and the edge of the chip.

[0100] In step S520 , a first electrode layer 120 is formed in contact with the main junction 310 , and a second electrode layer 110 is formed on the back surface of the N-type silicon carbide substrate 210 .

[0101] In this embodiment, combined with Figure 6-9 As shown in the schematic structure (f) in FIG, a first electrode layer 120 may be formed on the main junction 310 by depositing an electrode material, and a second electrode layer 110 may be formed on the back side of the N-type silicon carbide substrate 210 .

[0102] In some embodiments, step S300: etching a preset end area of ​​the main junction to form a tail trench, including: using a hard mask to define the tail trench area, and adjusting the dry etching process under the protection of the hard mask to etch the tail trench area on the N-type drift region to form the tail trench.

[0103] In this embodiment, combined with Figure 6As shown in the schematic structure (d) in FIG, a tail trench 710 with a specific bevel angle is formed by combining a hard mask 601 with dry etching. The first side tilt angle of the tail trench 710 is related to the etching time, etching ion gas ratio, energy, angle and thickness of the hard mask 601 in the dry etching process.

[0104] In some embodiments, step S300: etching a preset area at the end of the main junction to form a tail trench, including: using a hard mask or photoresist to define the tail trench area, and using a wet etching process to etch the tail trench area on the N-type drift region under the protection of the hard mask to form the tail trench.

[0105] In this embodiment, combined with Figure 7 As shown in the schematic structure (d) in FIG, a tail trench area is defined by a hard mask 601 or a photoresist 602. Under the protection of the hard mask 601 or the photoresist 602, a tail trench 710 with a specific bevel angle is formed in combination with a wet etching process. The first side tilt angle of the tail trench 710 is related to the etching time, etching solution concentration, energy, and thickness of the hard mask or photoresist in the wet etching process.

[0106] In some embodiments, combined Figure 11 As shown, under the same EPI conditions, the BV of the silicon carbide device with the traditional terminal structure S10 is 1586V, which is Figure 6-9 The silicon carbide power device with the terminal structure S20 shown in the schematic structure (f) has a BV of 1764V. Figure 6-9 The silicon carbide power device with the silicon carbide device terminal structure shown in the schematic structure (f) has a higher voltage resistance.

[0107] In some embodiments, combined Figure 12 As shown, when the first electrode layer 120 is connected to a voltage of 1586V, the electric field distribution is as follows: Figure 12 As shown, Figure 6-9 The electric field peak of the terminal structure of the silicon carbide device shown in the schematic structure (f) is located on the right side of the fourth ring. At the same time, the left slope of the groove also plays a certain role in bearing pressure. The electric field on the right side of the fourth ring is much stronger than the left slope of the groove, indicating that the terminal structure still has room for optimization and improvement. The electric field between the two points presents an ideal box-shaped distribution. When the electric field on the right side of the fourth ring is close to the electric field on the left slope of the groove, the model will reach the optimal state. When the first electrode layer 120 of the silicon carbide device with a traditional terminal structure is connected to a voltage of 1586V, its electric field distribution is as follows: Figure 12 As shown, the electric field peak of FLRs is located on the right side of the 6th-7th ring near the main junction. Figure 12 In the traditional terminal structure, the length of the FLRs terminal excluding the main junction is 110μm, and when the voltage is 1586V, the electric field distribution is as follows Figure 13 and Figure 14 As shown above, the length excluding the main junction is only 43μm. Figure 13 and Figure 14 The horizontal coordinate Y in represents the horizontal distance of the terminal structure. Figure 13 The longitudinal coordinate X in represents the longitudinal distance of the terminal structure, Figure 14 The vertical coordinate in represents the electric field strength. Figure 13 and Figure 14 As shown, Figure 6-9 In the terminal structure (S20) of the silicon carbide device shown in the schematic structure (f), at a lateral distance of 45 μm, the electric field on the right side of the fourth ring of the terminal structure is much stronger than the left slope of the groove. At this time, Figure 6-9 The terminal length shown in the schematic structure (f) is reduced by about 60%.

[0108] An embodiment of the present application further provides a chip including a silicon carbide power device, wherein the silicon carbide power device includes a terminal structure prepared by the method for preparing a terminal structure as described in any one of the above items.

[0109] In this embodiment, the chip includes a chip substrate, and one or more terminal structure preparation methods are provided on the substrate. The terminal structure preparation method can be a terminal structure preparation method in any of the above embodiments provided on the chip substrate.

[0110] In some embodiments, the silicon carbide power device may be any one of a silicon carbide MOSFET, a silicon carbide diode, and a silicon carbide IGBT.

[0111] The silicon carbide device terminal structure described in any of the above embodiments can be applied to any high-voltage power device produced based on SiC materials, including but not limited to silicon carbide MOSFETs, silicon carbide diodes, silicon carbide IGBTs, etc.

[0112] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit together with the terminal structure preparation method.

[0113] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0114] The beneficial effects of the embodiments of the present application are as follows: a field limiting ring structure including multiple field limiting rings is provided at the end of the main junction, a tail groove is formed between the field limiting ring structure and the edge of the chip, and the first sidewall inclination angle of the tail groove is set to be less than 16°, the second sidewall of the tail groove extends to the edge of the chip, and the field limiting ring area is covered by multiple junction terminal extension areas and extends to the tail groove, thereby combining the field limiting ring, the junction terminal extension area and the groove structure, and effectively shortening the terminal length and reducing the area occupied by the chip while ensuring the voltage resistance performance of the device.

[0115] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned doping regions and devices is only used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into a single unit, each unit can exist physically separately, or two or more units can be integrated into a single unit.

[0116] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application.

[0117] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0118] In addition, each doping region in each embodiment of the present application may be integrated into one unit, each unit may exist physically separately, or two or more units may be integrated into one unit.

[0119] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing a terminal structure, characterized in that: The preparation method of the terminal structure comprises: Providing an N-type silicon carbide substrate, and forming an N-type drift region on a front surface of the N-type silicon carbide substrate; forming a main junction on the N-type drift region; Implanting P-type impurities into the field limiting ring region to form a field limiting ring structure; wherein the field limiting ring structure includes a plurality of spaced field limiting rings; Superimposing and implanting P-type impurities in the field limiting ring region to form a junction terminal extension region; A tail trench is formed by etching in a preset area at the end of the main junction; wherein the junction terminal extension region covers the field limiting ring region and extends to the tail trench, and the doping concentration of the junction terminal extension region gradually decreases from the main junction outward through multiple masks and multiple ion implantation processes, the first sidewall inclination angle of the tail trench is less than 16°, and the field limiting ring region is between the first side of the tail trench and the main junction; wherein the first sidewall inclination angle is the angle between the first sidewall of the tail trench and the horizontal plane of the N-type drift region, and the junction terminal extension region is truncated by the tail trench.

2. The method for preparing a terminal structure according to claim 1, wherein: The step of implanting P-type impurities into the field limiting ring region to form a field limiting ring structure comprises: Multiple masks and multiple doping ion implantation processes are used to implant P-type impurities into predetermined areas of the field limiting ring region to form multiple spaced field limiting rings; wherein, the junction depth of the field limiting ring is 1 μm, and the junction concentration of the field limiting ring is approximately skewed, with the highest concentration near the interface.

3. The method for preparing a terminal structure according to claim 1, wherein: After the field limiting ring region is superimposed with the implantation of P-type impurities to form a junction terminal extension region, the method further comprises: A field limiting ring isolation trench is formed by etching an area on each field limiting ring, and an insulating dielectric material is filled in the field limiting ring isolation trench; wherein the depth of the field limiting ring isolation trench is less than or equal to the thickness of the junction terminal extension region.

4. The method for preparing a terminal structure according to claim 1, wherein: After etching the predetermined end region of the main junction to form a tail trench, the method further includes: Depositing an insulating dielectric material to form an insulating dielectric material layer; wherein the insulating dielectric material layer fills the tail trench and covers the area between the main junction end and the chip edge; A first electrode layer is formed in contact with the main junction, and a second electrode layer is formed on the back surface of the N-type silicon carbide substrate.

5. The method for preparing a terminal structure according to claim 1, wherein: The step of etching a predetermined region at the end of the main junction to form a tail trench comprises: A hard mask is used to define the tail groove area, and under the protection of the hard mask, a dry etching process is adjusted to etch the tail groove area on the N-type drift region to form the tail groove; wherein the first side tilt angle of the tail groove is related to the etching time, etching ion gas ratio, energy, angle and thickness of the hard mask of the dry etching process.

6. The method for preparing a terminal structure according to claim 1, wherein: The step of etching a predetermined region at the end of the main junction to form a tail trench comprises: A hard mask or photoresist is used to define the tail groove area, and a wet etching process is used to etch the tail groove area on the N-type drift region under the protection of the hard mask to form the tail groove; wherein the first side tilt angle of the tail groove is related to the etching time, etching solution concentration, energy, and thickness of the hard mask or photoresist of the wet etching process.

7. A chip, characterized in that: A silicon carbide power device is provided, wherein the silicon carbide power device comprises a terminal structure prepared by the method for preparing a terminal structure according to any one of claims 1 to 6.

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