Depletion type gate metal manufacturing method
By simplifying the production process of Y-gate semiconductor devices, and using sputtering and electroplating technology to form the second metal layer, the problems of low production efficiency and prone to gate cracks in the prior art are solved, and more efficient gate conductivity and morphological stability are achieved.
Patent Information
- Application Number
- CN202510509307.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2025-07-25
AI Technical Summary
During the production process of existing Y-gate semiconductor devices, multiple process steps are required to increase the cross-sectional area of the Y-gate, resulting in low production efficiency and prone to cracks at the gate.
By defining the Y gate bottom line width and etching the channel, sputtering the first metal layer, performing top photolithography and metal deposition, removing excess metal layer, simplifying the baking step, and forming the second metal layer by electroplating to increase the cross-sectional area and avoiding cracks.
The conductivity and sheet efficiency of the gate are improved, the gate morphology is ensured to be free of cracks, the cross-sectional area of the gate is increased, the gate resistance is reduced, and the CD uniformity is improved.
Smart Images
Figure CN120379324A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of gate metals, and particularly to a method for manufacturing a depletion-type gate metal. Background Art
[0002] The production process of a Y-gate semiconductor device generally undergoes the following processes: Process 1: Device source S / drain D metallization process; Process 2: Y-gate bottom lithography process: (1) Photoresist coating, such as Figure 1 ; (2) Development, such as Figure 2 ; (3) Baking, such as Figure 3 ; The function of baking is to make the photoresist reflow (i.e., make the photoresist flow and form a gentler photoresist topography), so that there will be no cracks in the subsequent metal evaporation. During the Figures 2 to 3 process, the macro distance will become smaller, and CD1>CD2; Process 3: Y-gate top lithography process; Process 4: Y-gate metallization deposition process. In order to improve the conductivity at the Y-gate, since the length of the Y-gate is fixed, it is necessary to increase the cross-sectional area of the Y-gate. At this time, it is also necessary to add a step of raising the Y-gate metal after the Y-gate metallization deposition process, that is, to perform another metal deposition on the Y-gate. At this time, an additional Y-gate metal raising deposition process will be added. Each process also includes multiple processing steps, such as surface cleaning, exposure and development, metallization or etching deposition, etc. In this way, manufacturing a taller Y-gate semiconductor device requires more process steps. Summary of the Invention
[0003] The purpose of the present invention is to provide a method for manufacturing a depletion-type gate metal, which can solve the problems raised in the above background art.
[0004] The technical solution of the present invention:
[0005] A method for manufacturing a depletion-type gate metal is as follows:
[0006] Step 1: Define the line width at the bottom of the Y-gate and etch a channel in the substrate;
[0007] Step 2: Sputter a first metal layer on the Y-gate;
[0008] Step 3: Perform top lithography on the Y-gate;
[0009] Step 4: Perform metal deposition on the Y-gate;
[0010] Step 5: Remove the top photoresist;
[0011] Step 6: Remove the excess first metal layer;
[0012] Step 7: Remove the photoresist at the bottom of the Y-gate.
[0013] Further, in the step 1, define the bottom line width of the Y-gate, that is, use I-line or electron beam to expose and develop the first photoresist to form the first opening groove; then do not perform the baking process;
[0014] In the step 1, the thickness of the channel is 30 nm to 50 nm.
[0015] Further, the first photoresist is a positive photoresist with a thickness not greater than 700 nm.
[0016] Further, in the step 2, sputter the Y-gate, that is, sputter the top of the first photoresist, the first opening groove and the channel. The material used for sputtering is titanium, and the thickness of the first metal layer formed by sputtering is 30 nm to 100 nm.
[0017] Further, in the step 3, perform photolithography on the top of the Y-gate, that is, use I-line or electron beam to expose and develop the second photoresist to form the second opening groove.
[0018] Further, the second photoresist is a negative photoresist with a thickness of 1000 nm.
[0019] Further, in the step 4, deposit metal on the Y-gate, that is, use the electroplating process to electroplate the second opening groove and the first metal layer located in the first opening groove to form the second metal layer; the metal used for electroplating is gold.
[0020] Further, in the step 5, remove the top photoresist, that is, remove the second photoresist.
[0021] Further, in the step 6, remove the redundant first metal layer, that is, use dry etching to remove the first metal layer other than the first metal layer under the second metal layer.
[0022] Further, in the step 7, remove the photoresist at the bottom of the Y-gate, that is, remove the first photoresist.
[0023] Advantages of the present invention:
[0024] (1) In the gate process, electroplating significantly increases the cross-sectional area, reduces the gate resistance, and increases the current.
[0025] (2) Remove the baking station for defining the bottom line width in the process flow, improve the wafer yield; improve the gate CD uniformity; when baking, the photoresist will flow, and the amount of photoresist flowing at each place will be different, resulting in a decrease in the gate CD uniformity of the whole gate;
[0026] In the process flow of the present invention, the baking station for defining the bottom line width is removed, and the gate topography can still be crack-free with this method. Description of the Drawings
[0027] Figure 1 It is a schematic diagram of photoresist coating in the background technology.
[0028] Figure 2 It is a schematic diagram of development in the background technology.
[0029] Figure 3 It is a schematic diagram of baking in the background technology.
[0030] Figure 4 It is a schematic diagram of the first opening groove.
[0031] Figure 5 It is a schematic diagram of the channel.
[0032] Figure 6 It is a schematic diagram of the first metal layer.
[0033] Figure 7 It is a schematic diagram of the second opening groove.
[0034] Figure 8 It is a schematic diagram of the second metal layer.
[0035] Figure 9 It is a schematic diagram of the second metal layer (without the second photoresist).
[0036] Figure 10 It is a schematic diagram of the second metal layer (after removing the redundant first metal layer).
[0037] Figure 11 It is a schematic diagram of the second metal layer (after removing the first photoresist).
[0038] Figure 12 It is a comparison schematic diagram of the present method and the original evaporation process.
[0039] In the figure: S is the source electrode, and D is the drain electrode.
[0040] Substrate 1, channel 2, first metal layer 3, first photoresist 4, first opening groove 5, second photoresist 6, second opening groove 7, second metal layer 8. Detailed implementation manners
[0041] The present invention will be further described below with reference to the accompanying drawings.
[0042] As Figures 4 - 12 shown, the present invention provides a method for fabricating a depletion-type gate metal, and the method is as follows:
[0043] Step 1: Define the line width CD of the bottom of the Y gate, and etch the channel 2 on the substrate 1;
[0044] Step 2: Sputter the first metal layer 3 on the Y gate;
[0045] Step 3: Lithography on the top of the Y-gate;
[0046] Step 4: Metal deposition on the Y-gate;
[0047] Step 5: Remove the top photoresist;
[0048] Step 6: Remove the excess first metal layer 3;
[0049] Step 7: Remove the photoresist at the bottom of the Y-gate.
[0050] Furthermore, in the said Step 1, define the line width at the bottom of the Y-gate, that is, use I-line or electron beam to expose and develop the first photoresist 4 to form the first opening groove 5; then do not perform the baking process;
[0051] In the said Step 1, the thickness of the channel 2 is 30 nm to 50 nm.
[0052] Furthermore, the first photoresist 4 is a positive photoresist with a thickness not greater than 700 nm.
[0053] Furthermore, in the said Step 2, sputter the Y-gate, that is, sputter the top of the first photoresist 4, the first opening groove 5 and the channel 2, the material used for sputtering is titanium, and the thickness of the first metal layer 3 formed by sputtering is 30 nm to 100 nm.
[0054] Furthermore, in the said Step 3, lithography on the top of the Y-gate, that is, use I-line or electron beam to expose and develop the second photoresist 6 to form the second opening groove 7.
[0055] Furthermore, the second photoresist 6 is a negative photoresist with a thickness of 1000 nm.
[0056] Furthermore, in the said Step 4, metal deposition on the Y-gate, that is, use the electroplating process to electroplate the second opening groove 7 and the first metal layer 3 located in the first opening groove 5 to form the second metal layer 8; the metal used for electroplating is gold.
[0057] Furthermore, in the said Step 5, remove the top photoresist, that is, remove the second photoresist 6.
[0058] Furthermore, in the said Step 6, remove the excess first metal layer 3, that is, use dry etching to remove the first metal layer 3 other than the first metal layer 3 under the second metal layer 8.
[0059] Furthermore, in the said Step 7, remove the photoresist at the bottom of the Y-gate, that is, remove the first photoresist 4.
[0060] The following further illustrates the present invention in conjunction with a specific embodiment:
[0061] A method for fabricating a depletion-mode gate metal
[0062] a. As Figure 4 , define the bottom line width of the Y gate, generally positive photoresist, generally described by I-line or electron beam, without baking process after development, and the profile is as follows;
[0063] The thickness of the photoresist is generally not greater than 700 nm;
[0064] After that, perform etching to etch a channel in the substrate, as Figure 5 (This part is not shown in the subsequent schematic diagrams); the thickness of the channel is generally between 30 nm and 50 nm, and the thickness of the sputtered metal needs to be greater than the thickness of the channel to ensure that there is no fault in the sputtered metal layer; and the first layer of enhanced metal is generally Pt, with a thickness of generally 10 nm (if the thickness is insufficient, there will be a fault), so this invention is specifically for the depletion-mode gate metal process; b. As Figure 6 , sputtering process; this method uses Ti for the depletion-mode pHEMT, and generally 30 - 100 nm subsequently;
[0065] c. As Figure 7 , Y gate top lithography process; generally use negative photoresist with a thickness of 1000 nm;
[0066] d. As Figure 8 , Y gate metal deposition process; use electroplating process, and the metal used is Au; the electroplating process has a planarizing effect, which will flatten the originally sunken area and further increase the cross-sectional area;
[0067] e. As Figure 9 , remove the top-layer photoresist;
[0068] f. As Figure 10 , remove the sputtered metal layer by dry etching;
[0069] g. Remove the Y gate bottom photoresist; as Figure 11 ;
[0070] h. Compare this method (as Figure 12 the upper half) with the original evaporation process (as Figure 12 the lower half), it can be seen that the cross-section increases;
[0071] The above are only the preferred embodiments of the present invention and should not be construed as limitations to this application. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope covered by the present invention.
Claims
1. A method for fabricating a depletion-mode gate metal, characterized in that, The method is as follows: Step 1: Define the bottom line width of the Y-gate and etch a channel in the substrate; Step 2: Sputter a first metal layer on the Y-gate; Step 3: Perform photolithography on the top of the Y-gate; Step 4: Deposit metal on the Y-gate; Step 5: Remove the top photoresist; Step 6: Remove the excess first metal layer; Step 7: Remove the photoresist at the bottom of the Y-gate.
2. A method for fabricating a depletion-mode gate made of metal, characterized in that, In Step 1, when defining the bottom line width of the Y-gate, that is, using I-line or electron beam to expose and develop the first photoresist to form a first opening groove; then no baking process is performed; In Step 1, the thickness of the channel is 30 nm to 50 nm.
3. A method for fabricating a depletion-mode gate made of metal, as claimed in claim 2, wherein The first photoresist is a positive photoresist with a thickness not greater than 700 nm.
4. A method for fabricating a depletion-mode gate made of metal, as claimed in claim 2, wherein In Step 2, when sputtering the Y-gate, that is, sputtering on the top of the first photoresist, the first opening groove and the channel. The material used for sputtering is titanium, and the thickness of the first metal layer formed by sputtering is 30 nm to 100 nm.
5. A method for fabricating a depletion-mode gate made of metal, as claimed in claim 4, wherein, In Step 3, when performing photolithography on the top of the Y-gate, that is, using I-line or electron beam to expose and develop the second photoresist to form a second opening groove.
6. A method for fabricating a depletion-mode gate made of metal, characterized in that, The second photoresist is a negative photoresist with a thickness of 1000 nm.
7. A method for fabricating a depletion-mode gate made of metal according to claim 5, wherein In Step 4, when depositing metal on the Y-gate, that is, using an electroplating process to electroplate the second opening groove and the first metal layer located in the first opening groove to form a second metal layer; the metal used for electroplating is gold.
8. A method for fabricating a depletion-mode gate made of metal, as claimed in claim 7, wherein In Step 5, when removing the top photoresist, that is, removing the second photoresist.
9. A method for fabricating a depletion-mode gate made of metal, characterized in that, In Step 6, when removing the excess first metal layer, that is, using dry etching to remove the first metal layers other than the first metal layer under the second metal layer.
10. A depletion-mode gate metal manufacturing method according to claim 9, characterized in that, In Step 7, when removing the photoresist at the bottom of the Y-gate, that is, removing the first photoresist.