Manufacturing method of thermopile device based on 3D stacked structure design

Abstract

The present invention discloses a method for fabricating a thermopile device based on a 3D stacked structure design. The method includes performing metal connection processing on the upper surface of a pre-installed silicon substrate using a complementary metal oxide semiconductor process to form an interconnecting metal and a passivation layer, wherein the interconnecting metal connects each pre-installed thermopile; depositing a layer of silicon oxide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane; etching the passivation layer and the sacrificial layer above the interconnecting metal to form openings, through which the interconnecting metal is exposed; and selectively etching the sacrificial layer to release the thermopile support membrane and the polycrystalline silicon thermopile structure thereon from the silicon substrate to form thermal isolation within the device. This method achieves high-density integration of thermopile units and application-specific integrated circuits, improving the integration level of the thermopile chip and reducing chip size. This allows for more circuit functions to be accommodated within the same chip size. It also increases the size of the thermopile unit and improves signal strength.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for manufacturing a thermopile device based on a 3D stacked structure design. Background Art

[0002] CMOS-MEMS integration is the trend in existing thermopile temperature measurement technology. Digital thermopiles consist of two components: a thermopile and an ASIC. Integration methods include interconnecting two chips or single-chip integration, with array devices often utilizing single-chip integration. The area of ​​the thermopile thin film affects output voltage and performance; larger thin films improve performance. In monolithic integrated single-point digital thermopiles and array devices, the thermopile and ASIC are located at different locations on the wafer, creating a trade-off between their areas. Increasing the thermopile area improves the output signal, but reduces the ASIC area and functionality. Increasing ASIC functionality requires expanding its area, which in turn reduces the thermopile area, lowering the output signal and increasing ASIC requirements. The dual-polysilicon process used to manufacture thermopile units increases development cycles. Existing technologies place the two components horizontally. Reducing the thermopile size reduces the output signal, impacting performance and accuracy, and also results in lower integration and higher costs. Vertical placement can address some of these issues, but requires bonding, increasing process complexity. For large-array digital thermopiles, using advanced process technology can reduce ASIC area or increase functionality. However, reducing the thermopile area to reduce costs also reduces the output signal and temperature measurement accuracy. These factors mutually restrict each other, making existing technologies face numerous challenges in terms of performance, cost, and process. Summary of the Invention

[0003] The embodiment of the present invention provides a method for manufacturing a thermopile device based on a 3D stacked structure design, aiming to solve the problem in the existing technical methods that the standard single-layer polysilicon complementary metal oxide semiconductor process cannot improve the overall signal transmission and reception strength of the thermopile device.

[0004] An embodiment of the present invention provides a method for manufacturing a thermopile device based on a 3D stacked structure design, the method comprising: manufacturing a dedicated integrated circuit on a silicon substrate using a complementary metal oxide semiconductor process, the dedicated integrated circuit comprising a passivation layer, and reserving an interconnect metal area in a top metal area within the dedicated integrated circuit, the interconnect metal connecting preset thermopiles to determine a predetermined area of ​​a thermopile suspension membrane; depositing a layer of silicon oxide as a sacrificial layer below the predetermined area of ​​the thermopile suspension membrane; etching the passivation layer and the sacrificial layer above the interconnect metal to form openings, the interconnect metal being exposed through the openings; depositing silicon nitride above the sacrificial layer to form a silicon nitride layer to fill the openings, the silicon nitride layer covering the sacrificial layer; depositing silicon oxide, silicon nitride, and aluminum oxide materials above the thermopile to form a thermopile support film, the support film being designed as a multi-layer structure, the silicon oxide material in the thermopile support film not being in contact with the silicon oxide material in the sacrificial layer; The thermopile is subjected to polysilicon deposition and the formed first layer of polysilicon is selectively doped and etched to form a first polysilicon thermocouple layer of the thermopile; silicon nitride is deposited on the first polysilicon thermocouple layer to form a dielectric layer; polysilicon is deposited on the thermopile and the formed second layer of polysilicon is selectively doped and etched to form a second polysilicon thermocouple layer of the thermopile; silicon nitride is deposited on the second polysilicon thermocouple layer to form an insulating layer, and holes are opened in the passivation layer, the sacrificial layer, the thermopile support film, and the insulating layer; a metal layer is deposited, the first polysilicon thermocouple layer and the second polysilicon thermocouple layer are interconnected to form a thermocouple, and the thermocouple is interconnected with the application-specific integrated circuit through the metal layer; a passivation layer is deposited on the metal layer; and the sacrificial layer is selectively etched to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to achieve thermal isolation within the thermopile device.

[0005] This method achieves high-density integration of thermopile units and ASICs, improving the integration level of thermopile chips while reducing chip size. While maintaining strict compatibility with standard single-layer polysilicon complementary metal oxide semiconductor (CMOS) processes, this method, through an innovative 3D stacked structure design, achieves high-density integration of thermopile units and ASICs. This improves the integration level of thermopile chips, reduces chip size, accommodates more circuit functions, and increases the size of thermopile units, improving signal strength. This effectively resolves the inherent conflict between signal enhancement, circuit functionality, and chip size in the development of high-performance digital thermopile devices. This solution produces thermopile devices with superior performance. This significantly reduces development difficulty, shortens development cycles, reduces manufacturing costs, and improves process compatibility with existing ASIC designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0007] Figure 1 A process flow chart of a method for manufacturing a thermopile device based on a 3D stacked structure design provided by an embodiment of the present invention;

[0008] Figure 2 A schematic diagram of the actual process flow of a thermopile device manufacturing method based on a 3D stacked structure design provided by an embodiment of the present invention;

[0009] Figure 3 A schematic diagram of the actual process flow of a thermopile device manufacturing method based on a 3D stacked structure design provided by an embodiment of the present invention;

[0010] Figure 4 A schematic diagram of the actual process flow of a thermopile device manufacturing method based on a 3D stacked structure design provided by an embodiment of the present invention.

[0011] Figure numerals: 1. silicon substrate; 2. application-specific integrated circuit; 2-1. interconnect metal; 2-2. pad area; 3. metal layer; 4. first layer of silicon nitride; 5. preset reserved area; 6. second layer of silicon nitride; 7. thermopile support film; 8. first layer of polysilicon; 9. third layer of silicon nitride deposited dielectric layer; 10. second layer of polysilicon; 11. fourth layer of silicon nitride deposited dielectric layer; 13. fifth layer of silicon nitride deposited passivation layer. DETAILED DESCRIPTION

[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0013] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0014] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0016] In this example, see Figure 1 As shown in the figure, an embodiment of the present invention provides a method for manufacturing a thermopile device based on a 3D stacked structure design, wherein the method includes steps S110 to S220.

[0017] S110. Using a complementary metal oxide semiconductor process to manufacture a dedicated integrated circuit on a silicon substrate, the dedicated integrated circuit includes a passivation layer, and an interconnect metal area is reserved in a top metal area of ​​the dedicated integrated circuit. The interconnect metal connects the preset thermopiles to determine a predetermined area of ​​the thermopile suspension membrane.

[0018] S120 , depositing a layer of silicon oxide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane.

[0019] S130 , etching the passivation layer and the sacrificial layer above the interconnect metal respectively to form openings, and the interconnect metal is exposed through the openings.

[0020] S140 , depositing silicon nitride on the sacrificial layer to form a silicon nitride layer to fill the opening, wherein the silicon nitride layer covers the sacrificial layer.

[0021] S150 , depositing silicon oxide, silicon nitride, and aluminum oxide materials above the thermopile to form a thermopile support film.

[0022] The support film is designed to be a multi-layer structure, and the silicon oxide material in the thermopile support film is not in contact with the silicon oxide material in the sacrificial layer.

[0023] S160 , depositing polysilicon on the thermopile and selectively doping and etching the formed first layer of polysilicon to form a first polysilicon thermocouple layer of the thermopile.

[0024] S170 , depositing silicon nitride on the first polysilicon thermocouple layer to form a dielectric layer.

[0025] S180 , depositing polysilicon on the thermopile and selectively doping and etching the formed second layer of polysilicon to form a second polysilicon thermocouple layer of the thermopile.

[0026] S190 , depositing silicon nitride material on the second polysilicon thermocouple layer to form an insulating layer, and opening holes in the passivation layer, the sacrificial layer, the thermopile support film, and the insulating layer.

[0027] S200 , depositing a metal layer, interconnecting the first polysilicon thermocouple layer and the second polysilicon thermocouple layer to form a thermocouple, and interconnecting the thermocouple and the dedicated integrated circuit through the metal layer.

[0028] S210 , depositing a passivation layer on the metal layer.

[0029] S220 , selectively etching the sacrificial layer to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to complete thermal isolation within the thermopile device.

[0030] As a key component in infrared temperature measurement, digital thermopile technology, with its broad application prospects, is undergoing a technological evolution from single-point, analog to array-based, digital technology, particularly driven by the mainstream trend of CMOS-MEMS integration. The core components of a digital thermopile device include a MEMS thermopile for infrared radiation detection and an ASIC for signal processing. These two components can be physically integrated in two ways: one is to fabricate them on separate chips and then electrically interconnect them through wire bonding or TSV wafer-level bonding, a method common in early single-point devices; the other is to integrate both on the same chip. This single-chip integration approach not only avoids the complexity of dual-chip interconnection, improves reliability, and reduces package size, but is also the only viable solution for thermopile array devices due to the large number of pixel units and extremely complex interconnections.

[0031] In single-chip digital thermopile devices, whether in single-point or array form, the thermopile element often occupies a significant chip area. This leads to a key design trade-off: within limited chip size and process conditions, to enhance the thermopile element's output signal (typically by increasing the area of ​​the thin film receiving infrared radiation, thereby improving resolution and accuracy), the thermopile element's area must be increased, which inevitably reduces the area of ​​the ASIC, potentially reducing its functionality. Conversely, increasing the functionality of the ASIC to achieve more complex signal processing or control requires a corresponding increase in its area, which in turn sacrifices the area of ​​the thermopile element, reducing the thermopile element's output signal strength and placing higher demands on the ASIC's processing power. Therefore, under the same chip size and process, there is an inherent trade-off between the thermopile element's signal strength and the functionality of the ASIC, which requires careful consideration by designers.

[0032] To further enhance the thermopile unit's output signal, the industry typically uses a double-polysilicon process, which stacks two layers of polysilicon (separated by a dielectric layer). This double-polysilicon structure does not increase the area of ​​the film that absorbs infrared radiation. While maintaining the same dimensions, the thermocouple unit is constructed from a single layer of polysilicon and then double layers. This increases the number of signal-generating structures within the thermocouple unit from one to two, thereby enhancing the thermopile device's output signal.

[0033] (The smallest unit of a thermopile is a thermocouple, which can be composed of one type of polysilicon or two types of polysilicon. However, this process has compatibility issues with the standard semiconductor process used to make application-specific integrated circuits, because the standard process usually only includes a single-layer polysilicon structure. To achieve double polysilicon based on the standard process, it is often necessary to modify the process, which not only increases the development difficulty and extends the product development cycle, but may also increase manufacturing costs. Therefore, how to maintain the standard single-layer polysilicon semiconductor circuit process unchanged while still achieving high-performance thermopile units on the same chip has become a potential key breakthrough point for reducing development cycles, improving process compatibility, and promoting the further development of digital thermopile technology.

[0034] As digital thermopile technology evolves toward single-chip integration and arrays, it faces a core technical challenge: ensuring a sufficiently high signal output from the thermopile unit (to enhance detection sensitivity and accuracy) while also leaving enough area for the ASIC to implement complex functions within a limited chip area. Traditional solutions, such as using a double-polysilicon process to enhance the signal, often require modifications to the standard single-polysilicon ASIC process, resulting in extended development cycles and poor process compatibility, hindering technological advancement.

[0035] like Figure 2-4As shown, S1-S17 represent the actual design process for a thermopile device based on a 3D stacked structure implemented in this embodiment. The core concept is to achieve the fabrication of high-performance thermopile units through ingenious 3D stacked structure design without changing the existing standard single-layer polysilicon semiconductor circuit process. This effectively balances the inherent contradiction between thermopile performance and ASIC functionality, reduces development cycles, and improves process compatibility. First, a ASIC (including an ASIC circuit with a passivation layer) is fabricated on a silicon substrate using a complementary metal oxide semiconductor (CMOS) process, and an interconnect metal area is reserved (on the top metal layer) (S110). Next, a layer of silicon oxide is deposited as a sacrificial layer in a specific area below the pre-determined thermopile suspension membrane (S120). Then, an etching process is used to open holes in the passivation and sacrificial layers, exposing the interconnect metal (S130). Next, a silicon nitride layer is deposited over the sacrificial layer, filling the holes and covering the sacrificial layer (S140). On this basis, a multilayer thermopile support film composed of silicon oxide, silicon nitride, and aluminum oxide is deposited (S150). The key is that the silicon oxide material in the support film does not directly contact the silicon oxide material in the sacrificial layer, leaving space for the subsequent release of the sacrificial layer. Next, a first layer of polysilicon is deposited, selectively doped, and etched to form the first polysilicon thermocouple layer of the thermopile (S160). Then, silicon nitride is deposited as a dielectric layer to separate the first and second polysilicon layers (S170). Subsequently, a second layer of polysilicon is deposited, doped, and etched to form a second polysilicon thermocouple layer, thereby constructing a structure similar to a double layer of polysilicon in the vertical direction. "Increasing the thermopile area" means that, for the same chip size, in conventional existing technology solutions, since the thermopile portion is on the same layer as the ASIC portion, the total chip size is the thermopile portion plus the ASIC portion. In the present invention, the thermopile portion is located above the ASIC portion, with the chip size defined by the ASIC size. The ASIC circuitry (including traces, diodes, MOS transistors, resistors, capacitors, and other components that make up the ASIC circuitry) is arranged below the thermopile portion. This minimizes chip size constraints on the thermopile unit structure, allowing the unit size to be increased to improve the unit output signal; or, using the same unit size, the number of thermopile units can be increased to improve the resolution of the thermopile device. This improves signal output (S180). A silicon nitride insulating layer is deposited above the second polysilicon thermocouple layer, and holes are opened in the passivation layer, sacrificial layer, support film, and insulating layer (S190). A metal layer is then deposited to interconnect the thermocouple pre-ASIC (S200). Finally, a passivation layer is deposited above the metal layer (S210), and the sacrificial layer (silicon oxide) is removed by selective etching (S220).Due to the design of the support film, the removal of the sacrificial layer allows the thermopile support film and the polycrystalline silicon thermopile structure on it to be released from the silicon substrate, forming a key 3D suspended structure, achieving thermal isolation between the thermopile unit and the substrate, and ensuring that infrared radiation energy can be efficiently absorbed by the thermopile unit and converted into electrical signals.

[0036] In summary, this 3D stacked structure design cleverly utilizes sacrificial layers and multilayer film technology to achieve vertical polysilicon stacking while maintaining the standard single-layer polysilicon process, thereby improving signal strength without requiring additional ASIC process modifications. This approach is expected to effectively resolve the conflict between signal enhancement and process compatibility in existing technologies, opening up new avenues for the development of high-performance, low-cost, and easily integrated digital thermopile devices.

[0037] Furthermore, a complementary metal oxide semiconductor process is used to manufacture a dedicated integrated circuit on a silicon substrate. Before the dedicated integrated circuit includes a passivation layer, the method includes presetting a deposition position unit on the thermopile; using a PVD method to deposit metal on the thermopile support film to form a high-reflectivity metal layer, the metal deposition uses a high-reflectivity metal material, and the thickness of the high-reflectivity metal layer is 10nm-1um.

[0038] Furthermore, after metal is deposited on the thermopile support film using PVD to form a high-reflectivity metal layer, the method includes depositing a nitride layer on the high-reflectivity metal layer to form a nitride layer surface, the nitride layer deposition uses silicon nitride material, and the nitride layer surface completely covers the high-reflectivity metal layer.

[0039] Placing a highly reflective metal layer above the ASIC circuitry and below the thermopile is inherently innovative. Rather than simply adding a material layer, this design intentionally leverages the metal layer's physical properties (high reflectivity) to enhance the thermopile's infrared absorption, a feature not common in standard thermopile designs. This cleverly exploits a "gap" in the standard complementary metal-oxide-semiconductor (CMOS) process flow, embedding the enhanced functional layer without adding complex process steps such as photolithography, which requires precise alignment between multiple layers. Following the deposition of the highly reflective metal layer, a layer of silicon nitride (SiN) is deposited on top, completely covering the metal layer. Silicon nitride is a good electrical insulator, isolating the highly reflective metal layer from the subsequently deposited polysilicon layer, preventing unwanted electrical connections. It also protects the underlying metal layer from damage during subsequent etching and high-temperature processing (such as polysilicon doping). Silicon nitride itself also has certain reflective or transmissive properties for certain wavelengths of infrared light. While its primary function is covering and protecting, its presence also affects the light propagation path within the thermopile structure. This may synergize with the underlying metal reflective layer to further optimize the thermopile's infrared radiation absorption efficiency. Furthermore, it provides a flat and stable surface for the subsequent precise deposition of the first polysilicon layer. This novel design combines silicon nitride directly onto a highly reflective metal layer and uses it as the foundation for the deposition of the thermopile's polysilicon layer. It not only addresses the electrical and processing challenges associated with direct contact between the metal layer and the semiconductor material, but also offers the potential for more precise control of infrared absorption through the optical interference effect of the multilayer film. The 3D stacked structure not only increases the thermopile's "physical" area, but also significantly enhances its "effective" infrared radiation absorption through the synergistic effect of the highly reflective metal and silicon nitride layers. The metal layer reflects unabsorbed light, while the silicon nitride layer further optimizes the optical path and protects the structure, enabling the thermopile unit to capture more infrared energy per unit area, significantly improving the sensor's sensitivity, response speed, and signal-to-noise ratio. The entire solution, from the bottom layer of high-reflectivity metal to the middle silicon nitride insulating / protective layer, to the upper and lower polysilicon thermocouples, and finally to the outermost passivation layer and interconnect metal, forms a multi-layered, multifunctional, and highly optimized 3D structure. The material selection and placement of each layer are carefully designed to enhance infrared absorption, achieve thermal isolation, ensure electrical connectivity, and maintain process compatibility. While metal and silicon nitride deposition steps are added, they are both well-established and easily integrated processes (PVD and PECVD) in standard semiconductor manufacturing. These steps, inserted before standard CMOS interconnect metal processing, do not disrupt or complicate the core CMOS logic circuit manufacturing flow, maintaining the solution's high compatibility with standard single-layer polysilicon processes. This means that development time and cost increases remain minimal.The significant performance improvement and potential cost reduction make this solution a strong contender in demanding infrared temperature measurement applications, such as high-precision medical temperature measurement, long-distance security monitoring, and precise temperature control in industrial processes. Its high single-chip integration, compact size, and low power consumption also hold great potential for application in consumer electronics. In summary, by introducing two key steps—a high-reflectivity metal layer and a silicon nitride capping layer—this solution, while maintaining its original innovative advantages (3D stacking structure and process compatibility), further optimizes its optical and structural design to achieve a significant increase in infrared absorption efficiency.

[0040] After depositing a layer of silicon oxide as a sacrificial layer below a predetermined region of the thermopile suspension membrane, the method includes setting a sacrificial layer deposition region on the surface of the suspension membrane for silicon oxide deposition, etching the silicon oxide outside a predetermined reserved region of the sacrificial layer, and, after silicon oxide deposition, removing the unnecessary silicon oxide and retaining the required silicon oxide, which is referred to as the "predetermined reserved region." Position 5 in step S4 represents the "predetermined reserved region," and the thickness of the sacrificial silicon oxide layer is set to 1-10 μm.

[0041] Furthermore, polysilicon is deposited on the thermopile and the formed first layer of polysilicon is selectively doped and etched to form a first polysilicon thermocouple layer of the thermopile, including using boron or phosphorus as a doping material. The second layer of polysilicon is selectively doped and etched in the same manner.

[0042] Specifically, cleaning and drying the substrate surface before depositing the sacrificial layer (or other thin film) is a standard and crucial pre-treatment step in semiconductor processing. This step removes surface adsorbed moisture and other contaminants, ensuring good, uniform adhesion between the deposited layer and the substrate. This is crucial for subsequent sacrificial layer etching, polysilicon deposition, and ultimately the formation of a stable and reliable suspended structure. This demonstrates the rigorous attention to detail in the proposed process. The sacrificial layer is clearly deposited below the surface of the suspended film, with a thickness range of 1-10 microns, providing a clear physical foundation for the subsequent formation of the suspended structure. Sufficient thickness is essential for effective thermal isolation, ensuring that the thermopile junction can sense the infrared radiation temperature of the target object without being excessively affected by the temperature of the silicon substrate. Furthermore, the 1-10 micron thickness range is optimized for infrared temperature measurement, matching the two commonly used infrared temperature measurement wavelengths of 5-14 μm or 8-14 μm, thereby enhancing the film's absorption rate in these wavelengths. The sacrificial layer needs to support the subsequent multilayer structure (support film, polysilicon thermocouple layer, etc.), and therefore requires sufficient mechanical strength. At the same time, the sacrificial layer must be completely removed during the subsequent release etch step. A thickness range of 1-10 microns provides a wide range of process options, allowing for tailoring to specific thermal performance requirements and material properties. Silicon oxide (SiO2), the sacrificial layer material, exhibits excellent etch selectivity (e.g., relative to silicon and polysilicon), facilitating the subsequent release process. The formation of the suspended structure ensures that the desired 3D suspended structure can be reliably released through selective etching of the sacrificial layer, achieving effective thermal isolation between the thermopile unit and the silicon substrate. Selective doping and etching of polysilicon with boron or phosphorus is a well-established and standard process technology in the semiconductor industry, easily integrated into existing CMOS-MEMS manufacturing flows. From a high-reflectivity metal layer, a silicon nitride capping layer, a precisely-thick silicon oxide sacrificial layer, to a multi-layer polysilicon structure, a carefully designed 3D stacked thermopile structure is formed, designed to maximize infrared absorption, achieve efficient thermal isolation, and precise electrical functionality. The entire process, from surface pretreatment, thin film deposition, selective etching, selective doping, to the final release step, utilizes mature and compatible technologies from semiconductor manufacturing. In particular, it has been clarified that within the framework of the standard single-layer polysilicon process, a small number of compatible steps (such as PVD, PECVD, and selective doping) can be added to achieve a similar effect to double-layer polysilicon. This directly resolves the contradiction between signal enhancement and process complexity / cost in existing technologies. Combined with the optical optimization of the high-reflectivity metal layer and silicon nitride capping layer, as well as the precise design of the sacrificial layer and multilayer structure, this solution is expected to achieve a significantly enhanced infrared signal response, improving the sensitivity and accuracy of the thermopile.

[0043] In another embodiment of the present invention, a ASIC is fabricated on a silicon substrate using a complementary metal oxide semiconductor process. After the ASIC includes a passivation layer, the method includes depositing a layer of polyimide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane.

[0044] In the above embodiment, after depositing a layer of polyimide as a sacrificial layer below the predetermined area of ​​the thermopile suspension membrane, the method includes depositing silicon oxide to form a thermopile support membrane, and setting the thermopile support membrane to a single-layer membrane structure.

[0045] Preferably, after depositing a layer of polyimide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane, the method includes depositing silicon oxide, silicon nitride and aluminum nitride materials above the thermopile to form a thermopile support membrane, wherein the support membrane is designed to be a multi-layer structure.

[0046] Specifically, after completing the CMOS interconnect metal and passivation layers, the solution offers another option: depositing a polyimide layer as a sacrificial layer beneath the predetermined area of ​​the thermopile suspension membrane. Polyimide is an organic polymer material with excellent high-temperature resistance, good insulation properties, and ease of uniform deposition over large areas through methods such as spin coating. Compared to inorganic materials such as silicon oxide, it differs in deposition process and etching characteristics. Introducing polyimide as a sacrificial layer demonstrates the solution's flexibility in material selection. This provides more possibilities for tailoring to specific process requirements or performance targets (e.g., specific thermal isolation performance or etching selectivity). The deposition and subsequent etching processes for polyimide may differ from those for silicon oxide, but they can still achieve the goal of releasing the suspension structure. After depositing the polyimide sacrificial layer, the solution offers two methods for constructing the thermopile support membrane: Silicon oxide deposition is used to form the thermopile support membrane, and the support membrane is designed as a single-layer membrane structure. Silicon oxide, silicon nitride, and aluminum nitride are sequentially deposited on top of the thermopile to form the thermopile support membrane. The support membrane is designed as a multilayer structure. Using a single material (silicon oxide) to form the support membrane simplifies the process and potentially reduces costs. Silicon oxide has good insulation properties and a certain degree of mechanical strength, meeting basic structural support requirements. Combining multiple materials, such as silicon oxide, silicon nitride, and aluminum nitride, allows for more precise performance control. Providing both single-layer and multi-layer support membrane design options further demonstrates the flexibility and adaptability of this invention. Designers can select the most appropriate support membrane structure based on the specific performance requirements of the target device (such as response speed, sensitivity, operating temperature range, and reliability). By introducing polyimide as an alternative to the sacrificial layer and offering both single-layer and multi-layer support membrane design options, this invention demonstrates design diversity and a deep understanding of practical application needs. This demonstrates that the inventors not only addressed the core technical issues (signal enhancement and process compatibility) but also considered the impact of different material combinations and structural designs on the ultimate device performance. Sacrificial layer material selection (silicon oxide vs. polyimide): provides different trade-off options in terms of process compatibility, cost, material properties, etc. Support membrane structure design (single layer vs. multi-layer): provides different optimization paths in terms of structural stability, thermal management, mechanical properties, etc.

[0047] Furthermore, the selective etching of the sacrificial layer includes pre-etching the pad region of the sacrificial layer to expose the silicon nitride layer in the interconnect metal region, wherein the thickness of the silicon nitride layer is set to be 50-300 nm.

[0048] Furthermore, after selectively etching the sacrificial layer to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to complete thermal isolation within the thermopile device, the method includes etching the entire thermopile device through silicon nitride, with the etching depth being set to the thickness of the silicon nitride retained above the pad area within the thermopile device to expose the pad area.

[0049] Before performing large-scale selective etching of the sacrificial layer, the solution incorporates a pre-etch step for the pad area of ​​the sacrificial layer. This pre-etch step exposes the silicon nitride layer within the interconnect metal area, avoiding the need for additional photolithography steps (such as vacuum adsorption, spin coating, stripping, and cleaning) after sacrificial layer etching and after the thermopile structure is suspended, thereby reducing the likelihood of film damage. The solution also specifies a thickness range of 50 to 300 nm for the silicon nitride layer. The pad area is a critical interface for subsequent device packaging and testing. Pre-etching ensures that the pad area is accurately and completely exposed during the release of the 3D suspended structure, providing a reliable contact point for subsequent wire bonding or other connection methods. This prevents potential damage to the pad or underlying interconnect metal during the overall release process. Pre-etching and limiting the silicon nitride thickness demonstrate the solution's high degree of control over the etching process. Precise control of etch depth and selectivity is crucial for ensuring device yield and reliability. This detail demonstrates the inventors' thorough consideration of the device's overall integrity and manufacturability, focusing not only on the core thermopile sensing element but also fully considering the device's integrity and the connection to subsequent processes. After successfully etching the sacrificial layer, releasing the 3D suspended structure, and achieving thermal isolation, the solution includes a subsequent step: etching the entire thermopile device through silicon nitride. The etch depth is set to just remove the remaining silicon nitride above the pad area, fully exposing the pad area. Although the pre-etching step already exposes some silicon nitride, this final etch step ensures that the pad area is not covered by any insulating layer (silicon nitride), providing the lowest contact resistance and the most reliable electrical connection interface. This is crucial for ensuring effective device signal output and test accuracy. This step is the final critical step in the device manufacturing process, ensuring the device's physical structure and electrical integrity. Similarly, this step requires precise etch control to avoid damaging the underlying interconnect metal or thermopile structure. These two newly added steps—pre-etching the pad area and final silicon nitride etching of the pad area after device release—further refine the overall process flow and highlight the solution's commitment to manufacturing precision and device integrity. They ensure controllable release processes and initial exposure of the pad area. The final pad etch ensures perfect exposure of the electrical connection interface, laying a solid foundation for final device packaging and testing.

[0050] In an embodiment of the present invention, a method for manufacturing a thermopile device based on a 3D stacked structure design is provided. The method includes: using a complementary metal oxide semiconductor process to perform metal connection processing on the upper surface of a silicon substrate pre-installed with a dedicated integrated circuit to form an interconnect metal and a passivation layer, wherein the interconnect metal connects each thermopile; depositing a layer of silicon oxide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane; etching the passivation layer and the sacrificial layer above the interconnect metal to form an opening, through which the interconnect metal is exposed; depositing silicon nitride above the sacrificial layer to form a silicon nitride layer to fill the opening, and the silicon nitride layer covers the sacrificial layer; depositing silicon oxide, silicon nitride and aluminum oxide materials above the thermopile to form a thermopile support film, wherein the support film is designed to be The multi-layer structure is characterized in that the silicon oxide material in the thermopile support film is not in contact with the silicon oxide material in the sacrificial layer; polysilicon is deposited on the thermopile and the formed first layer of polysilicon is selectively doped and etched to form a first polysilicon thermocouple layer of the thermopile; silicon nitride is deposited on the first polysilicon thermocouple layer to form a dielectric layer; polysilicon is deposited on the thermopile and the formed second layer of polysilicon is selectively doped and etched to form a second polysilicon thermocouple layer of the thermopile; a passivation layer is deposited on the second polysilicon thermocouple layer; and the sacrificial layer is selectively etched to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to complete thermal isolation within the thermopile device.

[0051] All embodiments of the present invention achieve significant improvements in thermopile unit performance (especially signal strength) through an innovative 3D stacked structure design, while maintaining strict compatibility with standard single-layer polysilicon complementary metal oxide semiconductor (CMOS) processes. This effectively resolves the inherent conflict between signal enhancement and process compatibility in the development of high-performance digital thermopile devices. A key advantage of this approach is that it enables the production of thermopile devices with enhanced performance without modifying the mainstream, cost-effective single-layer polysilicon standard CMOS process. This significantly reduces development effort, shortens development cycles, reduces manufacturing costs, and enhances process compatibility with existing ASIC designs. The sacrificial layer technology and the vertical 3D stacked structure effectively increase the thermopile's absorption area, achieving signal enhancement similar to that achieved by a double-layer polysilicon structure while avoiding the complex process requirements of a double-layer structure. Combined with subsequent optimization measures such as an optional high-reflectivity metal layer and silicon nitride capping layer, the device's infrared absorption efficiency and overall performance are further enhanced. The present invention not only proposes a core 3D structure, but also carefully considers and optimizes details such as the selection of sacrificial layer materials (silicon oxide / polyimide), support membrane structure design (single layer / multi-layer), sacrificial layer deposition pretreatment, pre-etching steps, and final pad exposure, ensuring the feasibility and controllability of the process and the ultimate reliability of the device.

[0052] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for manufacturing a thermopile device based on a 3D stacked structure design, characterized in that: The method comprises: A ASIC is fabricated on a silicon substrate using a complementary metal oxide semiconductor process. The ASIC includes a passivation layer and an interconnect metal region is reserved in a top metal region of the ASIC. The interconnect metal region connects the preset thermopiles and defines a predetermined region of the thermopile suspension membrane. depositing a layer of silicon oxide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane; Etching the passivation layer and the sacrificial layer above the interconnect metal respectively to form openings, through which the interconnect metal is exposed; Depositing silicon nitride on the sacrificial layer to form a silicon nitride layer to fill the opening, wherein the silicon nitride layer covers the sacrificial layer; Depositing silicon oxide, silicon nitride, and aluminum oxide materials above the thermopile to form a thermopile support film, wherein the support film is designed to have a multi-layer structure, and the silicon oxide material in the thermopile support film does not contact the silicon oxide material in the sacrificial layer; Depositing polysilicon on the thermopile and selectively doping and etching the formed first layer of polysilicon to form a first polysilicon thermocouple layer of the thermopile; Depositing silicon nitride over the first polysilicon thermocouple layer to form a dielectric layer; Depositing polysilicon on the thermopile and selectively doping and etching the formed second layer of polysilicon to form a second polysilicon thermocouple layer of the thermopile; Depositing silicon nitride material on the second polysilicon thermocouple layer to form an insulating layer, and opening holes in the passivation layer, the sacrificial layer, the thermopile support film, and the insulating layer; Depositing a metal layer, wherein the first polysilicon thermocouple layer and the second polysilicon thermocouple layer are interconnected to form a thermocouple, and the thermocouple and the ASIC are interconnected through the metal layer; Depositing a passivation layer over the metal layer; The sacrificial layer is selectively etched to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to achieve thermal isolation within the thermopile device.

2. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: The method of manufacturing an ASIC on a silicon substrate using a complementary metal oxide semiconductor process, before the ASIC includes a passivation layer, comprises: Presetting a deposition position unit on the thermopile; The thermopile support film is subjected to metal deposition by PVD to form a high-reflectivity metal layer. The metal deposition adopts a high-reflectivity metal material. The thickness of the high-reflectivity metal layer is 10 nm-1 um.

3. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 2, characterized in that: After metal deposition is performed on the thermopile support film by PVD to form a high-reflectivity metal layer, the method includes: A nitride layer is deposited on the high-reflectivity metal layer to form a nitride layer surface. The nitride layer is deposited using silicon nitride material. The nitride layer surface completely covers the high-reflectivity metal layer.

4. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: After depositing a layer of silicon oxide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane, the method includes: A sacrificial layer deposition area is set on the surface of the suspension membrane to deposit silicon oxide, and the silicon oxide in a preset reserved area of ​​the sacrificial layer is etched. The thickness of the silicon oxide sacrificial layer is set to 1-10 μm.

5. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: Depositing polysilicon on the thermopile and selectively doping and etching the formed first layer of polysilicon to form a first polysilicon thermocouple layer of the thermopile includes: Boron is used as a doping material.

6. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: After the ASIC is manufactured on a silicon substrate using a complementary metal oxide semiconductor process and the ASIC includes a passivation layer, the method includes: A layer of polyimide is deposited under a predetermined area of ​​the thermopile suspension membrane as a sacrificial layer.

7. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 6, characterized in that: After depositing a layer of polyimide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane, the method includes: Silicon oxide is deposited to form a thermopile support film, and the thermopile support film is set to a single-layer film structure.

8. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 6, characterized in that: After depositing a layer of polyimide as a sacrificial layer below a predetermined area of ​​the thermopile suspension membrane, the method includes: Silicon oxide, silicon nitride and aluminum nitride are deposited on the thermopile to form a thermopile support film, which is designed to be a multi-layer structure.

9. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: The selectively etching the sacrificial layer comprises: The pad area of ​​the sacrificial layer is pre-etched to expose the silicon nitride layer in the interconnect metal area, wherein the thickness of the silicon nitride layer is set to be 50-300 nm.

10. The method for manufacturing a thermopile device based on a 3D stacked structure design according to claim 1, characterized in that: After selectively etching the sacrificial layer to release the thermopile support film and the polysilicon thermopile structure thereon from the silicon substrate to form a 3D suspended structure to achieve thermal isolation within the thermopile device, the method includes: The entire thermopile device is subjected to silicon nitride etching, wherein the etching depth is set to the thickness of the silicon nitride remaining above the pad area in the thermopile device so as to expose the pad area.

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