Systems and methods for context-dependent multi-core interrupt facilitation

Abstract

The multi-core processor may include: a plurality of cores including at least a first core and a second core; comprising a plurality of interrupt register banks, the plurality of interrupt register banks comprising at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core; and a plurality of communication bridges including at least a first bridge docked between the first core and the shared peripheral and at least a second bridge docked between the second core and the shared peripheral. The first core may be configured to program the first interrupt register set via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second block of interrupt registers via the second bridge to configure the shared peripheral for access by the second core.

Description

Technical Field

[0001] The present disclosure generally relates to circuits for electronic devices, including but not limited to personal portable devices such as wireless telephones and media players, and more particularly, to systems and methods for context - related interrupt facilitation in multi - core processing devices. Background Art

[0002] Many mobile devices (e.g., mobile phones) include one or more cameras for capturing images. To provide image stabilization and focusing, under the control of a camera controller, the position of the camera in a plane substantially parallel to the image object and the position of the camera lens in a direction perpendicular to that plane can be controlled by multiple motors. A control system can be implemented using an application processor of the mobile device that is coupled via a communication interface (e.g., an internal integrated circuit or I2C interface) to the camera controller that is local to the camera and its various motors. For example, the application processor can communicate a data vector regarding the target position of the application processor to the camera controller, while the camera controller can communicate a vector regarding the actual position of the camera sensed by multiple magnetic sensors (e.g., Hall sensors) and / or other suitable sensors to the application processor.

[0003] As mobile devices become increasingly complex, camera control on these mobile devices also becomes increasingly complex. Thus, camera controllers are increasingly implemented using multi - core processors, which can include multiple processing cores and multiple peripheral blocks on a single integrated circuit. In such a multi - core processor, there may be multiple processes running on different cores that can consume data or context from peripheral blocks or can run on different execution contexts provided by peripheral blocks.

[0004] In an embedded multi - core system, there may be static, serial, and / or joint ownership of processing and / or data from peripheral blocks, which can pose many challenges. One challenge in an embedded multi - core system is that accessing a peripheral block not specified in a core domain incurs the risk of communication bus conflicts / overheads and / or communication bus stalls for that core.

[0005] A second challenge is that while interrupt request lines may be mapped to different cores on a multi - core processor, each core may need a mechanism to individually enable / disable or clear / set interrupts based on channel readiness or related error conditions. For example, in a particular use case, a first core may need a data - ready interrupt from a sensor channel to process control mathematics, while a second core may need a voltage - related interrupt to perform signal compensation associated with voltage levels. Each of the two cores may also need to access the interrupt register without conflicting with the writes of the other core.

[0006] A third challenge may be context awareness. In addition to replicating the interrupt request registers for each core to access, the peripheral block must also be able to detect the context in which an interrupt is generated. A single core may need to have the ability to enable / disable interrupts based on the type of transfer on a communication link (also known as an endpoint). Endpoint-based interrupts provide an execution context, and the core must be able to configure and schedule tasks associated with that endpoint. Summary of the Invention

[0007] In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with existing methods of implementing multi-core systems may be reduced or eliminated.

[0008] According to an embodiment of the present disclosure, a multi-core processor may include: a plurality of cores including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges including at least a first bridge docking between the first core and the shared peripheral device and at least a second bridge docking between the second core and the shared peripheral device. The first core may be configured to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core. The second core may be configured to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

[0009] In accordance with these and other embodiments of the present disclosure, a method may be provided for a multi-core processor having: a plurality of cores including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges including at least a first bridge docking between the first core and the shared peripheral device and at least a second bridge between the second core and the shared peripheral device. The method may include configuring the first core to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core and configuring the second core to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

[0010] Based on the accompanying drawings, the description, and the claims included herein, the technical advantages of the present disclosure may be apparent to those skilled in the art. The objectives and advantages of the embodiments will be achieved and attained at least by the elements, features, and combinations particularly pointed out in the claims.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory and do not limit the claims set forth in this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the examples, embodiments thereof, and certain advantages can be obtained by reference to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate like features, and in which:

[0013] Figure 1 A block diagram showing selected components of an example mobile device in accordance with an embodiment of the present disclosure;

[0014] Figure 2 A block diagram showing selected components of an example multi-core processor in accordance with an embodiment of the present disclosure, the example multi-core processor being usable to implement a control subsystem of a camera controller; and

[0015] Figure 3A and Figure 3B (which may be collectively referred to herein as "FIG. 3") shows a timing diagram of a time division of a communication transmission in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Figure 1 A block diagram showing selected components of an example mobile device 102 in accordance with an embodiment of the present disclosure. As Figure 1 shown, the mobile device 102 may include a housing 101, an application processor 103, a microphone 106, a radio transmitter / receiver 108, a speaker 110, and a camera module 109 including a camera 107 and a camera controller 112.

[0017] The housing 101 may include any suitable housing, enclosure, or other casing for housing the various components of the mobile device 102. The housing 101 may be constructed of plastic, metal, and / or any other suitable material. Additionally, the housing 101 may be adapted (e.g., sized and shaped) such that the mobile device 102 can be easily carried on the person of a user of the mobile device 102. Accordingly, the mobile device 102 may include, but is not limited to, a smart phone, a tablet computing device, a handheld computing device, a personal digital assistant, a laptop computer, a video game controller, or any other device that can be easily carried on the person of a user of the mobile device 102.

[0018] The application processor 103 may be housed within the housing 101 and may include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and may include, but is not limited to, a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or any other digital or analog circuit configured to interpret and / or execute program instructions and / or process data. In some embodiments, the application processor 103 may interpret and / or execute program instructions and / or process data stored in a memory (not explicitly shown) and / or other computer-readable media accessible to the application processor 103.

[0019] The microphone 106 may be at least partially housed within the housing 101, may be communicatively coupled to the application processor 103, and may include any system, device, or apparatus configured to convert sound incident at the microphone 106 into an electrical signal that can be processed by the application processor 103, wherein such sound is converted into an electrical signal using a diaphragm or membrane having a capacitance that varies based on acoustic vibrations received at the diaphragm or membrane. The microphone 106 may include an electrostatic microphone, a capacitive microphone, an electret microphone, a microelectromechanical systems (MEM) microphone, or any other suitable capacitive microphone.

[0020] The radio transmitter / receiver 108 may be housed within the housing 101, may be communicatively coupled to the application processor 103, and may include any system, device, or apparatus configured to generate and transmit radio frequency signals with the aid of an antenna, as well as receive radio frequency signals and convert the information carried by these received signals into a form usable by the application processor 103. The radio transmitter / receiver 108 may be configured to transmit and / or receive various types of radio frequency signals, including but not limited to cellular communications (e.g., 2G, 3G, 4G, LTE, etc.), short-range wireless communications (e.g., BLUETOOTH), commercial radio signals, television signals, satellite radio signals (e.g., GPS), Wi-Fi, etc.

[0021] The speaker 110 can be at least partially housed within the housing 101, or can be external to the housing 101, can be communicatively coupled to the application processor 103, and can include any system, device, or apparatus configured to generate sound in response to an electrical audio signal input. In some embodiments, the speaker 110 can include a dynamic loudspeaker that employs a lightweight diaphragm mechanically coupled to a rigid frame via a flexible suspension that constrains a voice coil to axially move through a magnetic gap. When an electrical signal is applied to the voice coil, the current in the voice coil generates a magnetic field, making it a variable electromagnet. The voice coil and the magnetic system of the driver interact to generate a mechanical force that causes the voice coil (and thus the attached cone) to move back and forth, thereby reproducing sound under the control of the applied electrical signal from an amplifier.

[0022] The camera 107 can be at least partially housed within the housing 101 (and partially outside the housing 101 to allow light to enter the lens of the camera 107), and can include any suitable system, device, or apparatus for recording an image (moving or still) into one or more electrical signals that can be processed by the application processor 103. As Figure 1 shown, the camera 107 can include a plurality of motors 114, sensors 116, and an image capture assembly 118.

[0023] The image capture assembly 118 can include a collection of components configured to capture an image, including but not limited to one or more lenses and an image sensor for sensing the intensity and wavelength of the received light. Such an image capture assembly 118 can be coupled to the application processor 103 such that the camera 107 can communicate the captured image to the application processor 103.

[0024] The motors 114 can be mechanically coupled to one or more of the image capture assemblies 118, and each motor 114 can include any suitable system, device, or apparatus configured to mechanically move such one or more image capture assemblies 118 to a desired camera position based on a control signal received from the camera controller 112 indicating the desired camera position.

[0025] The sensors 116 can be mechanically coupled to one or more of the image capture assembly 118 and / or the motors 114, and can be configured to sense a position associated with the camera 107. For example, a first sensor 116 can sense a first position of the camera 107 relative to a first linear direction (e.g., an x position), a second sensor 116 can sense a second position of the camera 107 relative to a second linear direction perpendicular to the first linear direction (e.g., a y position), and a third sensor 116 can sense a third position of the camera 107 (e.g., the position of the lens) relative to a third linear direction perpendicular to the first and second linear directions (e.g., a z position).

[0026] The camera controller 112 can be housed within the housing 101, can be communicatively coupled to the camera 107 and the application processor 103 (e.g., via an Inter-Integrated Circuit (I2C) interface), and can include any system, device, or apparatus configured to control the motor 114 or other components of the camera 107 to place the components of the camera 107 in a desired position. The camera controller 112 can also be configured to receive signals from the sensor 116 regarding the actual position of the camera 107 and / or regarding the status of the camera 107. As Figure 1 shown, the camera controller 112 can include a control subsystem 111 and a motor driver 113.

[0027] The control subsystem 111 can be integrated into the camera controller 112 and can include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and can include, but is not limited to, a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or any other digital or analog circuit configured to interpret or execute program commands and / or process data. In some embodiments, the control subsystem 111 can interpret and / or execute program instructions stored in a memory and / or other computer-readable media accessible to the control subsystem 110 and / or process data. Specifically, the control subsystem 111 can be configured to perform the functions of the camera controller 112, including but not limited to controlling the motor 114 and receiving and processing data from the sensor 116. In some embodiments, the control subsystem 111 can include a multi-core processor.

[0028] The motor driver 113 can include a plurality of circuits, each such circuit being configured to receive one or more control signals (including but not limited to a signal indicating a desired target current of the motor 114) from the control subsystem 111 and drive a drive signal (e.g., a current mode signal) to the corresponding motor 114 in accordance with the one or more control signals so as to control the operation of such corresponding motor 114.

[0029] Figure 2 A block diagram of selected components of an example multi-core processor 200 according to an embodiment of the present disclosure is shown, and the example multi-core processor 200 can be used to implement the control subsystem 111 of the camera controller 112. As Figure 2As shown, the multi-core processor 200 may include: a plurality of cores 202 including cores 202a and 202b, a memory 204 (e.g., memories 204a and 204a), a bus matrix 206, a plurality of bridges 208 including bridges 208a and 208b each dedicated to a corresponding core 202, a shared peripheral 210, and a plurality of interrupt request lines 222 including interrupt request lines 222a and 222b each dedicated to a corresponding core 202. Although for clarity and illustrative purposes, Figure 2 only a single shared peripheral 210 is depicted, it will be understood that the multi-core processor 200 may include a plurality of shared peripherals 210.

[0030] Each core 202 may include a separate processing unit that can read and execute program instructions such that the multi-core processor 200 can execute instructions simultaneously on multiple cores 202, which can increase the overall execution speed of an instruction program that supports multi-threading or other parallel computing techniques. In some embodiments, the core 202 may interpret and / or execute program instructions and / or process data stored in one or more memories 204 and / or another component of the multi-core processor 200.

[0031] The memory 204 may be communicatively coupled to the core 202 via the bus matrix 206 and may include any system, device, or apparatus (e.g., a computer-readable medium) configured to retain program instructions and / or data over a period of time. The memory 204 may include RAM, EEPROM, PCMCIA cards, flash memory, magnetic memory, magneto-optical memory, or any suitable selection and / or array of volatile or non-volatile memory.

[0032] The bus matrix 206 may include any suitable communication bus for communicatively coupling the core 202, the memory 204, and the bridges 208 to each other. In some embodiments, the bus matrix 206 may include an Advanced High-Performance Bus (AHB) compliant with the Advanced Microcontroller Bus Architecture specification.

[0033] The bridge 208 may include a peripheral bus interface configured to communicatively couple the shared peripheral device 210 to the core 202 via the bus matrix 206. Specifically, each bridge 208 may be dedicated to a particular core 202. For example, bridge 208a may be dedicated to bus communication between core 202a and the shared peripheral device 210, and bridge 208b may be dedicated to bus communication between core 202b and the shared peripheral device 210. Thus, by using the bridges 208, the cores 202 may access the features of the shared peripheral device 210, such as the register interface of the peripheral registers 212 of the shared peripheral 21. In some embodiments, the bridge 208 may include an Advanced Peripheral Bus (APB) compliant with the Advanced Microcontroller Bus Architecture specification.

[0034] The shared peripheral device 210 may include any auxiliary block of the multi-core processor 200 that may receive information from and send information to the cores 202. For example, the shared peripheral device 210 may actually include the input / output interface of the multi-core processor 200, which may interface with components external to the multi-core processor 200, such as the motor 114, the sensor 116, and / or the application processor 103. As Figure 2 shown, the shared peripheral device 210 may include peripheral registers 212 and a peripheral interrupt interface 214.

[0035] The peripheral registers 212 may include memory local to the shared peripheral device 210 for storing any relevant data and / or metadata related to access of the shared peripheral 21 by the cores 202.

[0036] The peripheral interrupt interface 214 may include any suitable interface for configuring the interrupt handling of interrupt requests from the shared peripheral device 210 to the cores 202, and may include a plurality of interrupt register groups 216, including interrupt register groups 216a and 216b each dedicated to a respective core 202. For its respective core 202, each interrupt register group 216 may include a static interrupt configuration 218 for enabling and disabling channel data-based interrupts and a statically configured but dynamically triggered interrupt configuration 220 for enabling and disabling endpoint-based interrupts. In other words, the interrupt register group 216a may include a static interrupt configuration 218a for enabling and disabling channel data-based interrupts for core 202a and a statically configured but dynamically triggered interrupt configuration 220a for enabling and disabling endpoint-based interrupts, while the interrupt register group 216b may include a static interrupt configuration 218b for enabling and disabling channel data-based interrupts for core 202b and a statically configured but dynamically triggered interrupt configuration 220b for enabling or disabling endpoint-based interrupts.

[0037] For example, each core 202 can individually enable channel data ready interrupts for available channels by programming appropriate registers of the core's associated static interrupt configuration 218. Duplication of the interrupt registers for each core 202 can allow each core 202 to select which channels interrupt that core 202.

[0038] As another example, each core 202 can individually enable endpoint-based interrupts by programming appropriate registers of the core's associated interrupt configuration 220. Endpoint communication hardware can dynamically detect the endpoints (i.e., transmission types) embedded in communication packets and generate interrupt requests to each core 202 for which interrupts have been enabled for that endpoint.

[0039] In addition, as Figure 2 shown, based on the interrupt configuration settings, the shared interrupt interface 214 can map dedicated interrupt request lines 222 to each core 202.

[0040] In addition, based on the interrupt configuration settings, the shared interrupt interface 214 can allow dynamic reallocation of interrupts from one core 202 to a subset of one or more other cores 202 in order to effectively perform load balancing according to the configured control mode.

[0041] Therefore, Figure 2 the architecture of the multi-core processor 200 shown and described above can be provided for the following:

[0042] · Mapping of each of the multiple interrupt request lines 222, where each interrupt request line 222 is dedicated to a corresponding core 202;

[0043] · Multiple interrupt register sets 216 for access and configuration of the multiple cores 202, where each interrupt register set 216 is dedicated to a corresponding core 202;

[0044] o The interrupt register set 216 can include a static interrupt configuration 218 for enabling and disabling channel data-based interrupts for its corresponding core 202;

[0045] o The interrupt register set 216 can include a static but dynamically triggered interrupt configuration 220 for enabling and disabling endpoint-based interrupts for its corresponding core 202; and

[0046] · Multiple bridges 208, where each bridge 208 is dedicated to a corresponding core 202.

[0047] Providing a dedicated bridge 208 for each core can significantly minimize arbitration through the bus matrix 206, but may make the bus structure of the bus matrix 206 more complex and larger, which may have a negative impact on the overall maximum clock speed of the cores 202. To reduce or eliminate these drawbacks due to the simultaneous access of the cores 202 to the shared peripherals 210, the multi-core processor 200 may include a software architecture configured to time-division the access of the cores 202 to the shared peripherals. In this case, time-division may refer to dividing communication transmissions into non-overlapping time periods, such as time-critical transmission time periods and non-critical transmission time periods. As a specific example, one core 202a may be an application core that manages peripheral interactions during time-critical segments, while the operating system core may manage peripheral interactions during non-critical time periods. FIG. 3 shows a timing diagram for time-dividing communication transmissions from the cores 202 to the shared peripherals 210 between a time-critical time period 302 and a non-time-critical time period 304 according to an embodiment of the present disclosure. Other time-division techniques may include managing the access of the cores 202 to the shared peripherals 210 within interrupts having different periodicities between the cores 202. Although such time-division techniques may not completely eliminate arbitration through the bus matrix 206, such techniques can significantly minimize arbitration.

[0048] Although the foregoing has considered the use of multi-core processors in the context of camera controllers, it should be understood that the systems and methods described herein may be applied to any suitable application.

[0049] As used herein, when two or more elements are referred to as being "coupled" to each other, the term indicates that the two or more elements are in electronic communication or mechanical communication (as applicable), either directly or indirectly connected, with or without intermediate elements.

[0050] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that would be understood by a person of ordinary skill in the art. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that would be understood by a person of ordinary skill in the art. Additionally, in the appended claims, a reference to a device or system or a component of a device or system that is adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function includes that device, system, or component, whether or not the particular function is activated, turned on, or unlocked, so long as the device, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, the systems, devices, and methods described herein may be modified, added to, or omitted without departing from the scope of this disclosure. For example, components of the systems and devices may be integrated or separated. Additionally, the operations of the systems and devices disclosed herein may be performed by more, fewer, or other components, and the methods described may include more, fewer, or other steps. Further, the steps may be performed in any suitable order. As used herein, "each" refers to each member of a set or each member of a subset of a set.

[0051] Although the exemplary embodiments are shown in the drawings and described below, the principles of this disclosure may be implemented using any number of techniques, whether currently known or not. This disclosure should not in any way be limited to the exemplary embodiments and techniques shown in the drawings and described above.

[0052] Unless otherwise specifically stated, the items depicted in the drawings are not necessarily drawn to scale.

[0053] All of the examples and conditional language recited herein are intended for pedagogical purposes to assist the reader in understanding the disclosure and the concepts contributed by the inventor to further the art, and are to be construed as not being limited to such specifically recited examples and conditions. Although the embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to the disclosure without departing from the spirit and scope of the disclosure.

[0054] While specific advantages have been recited above, various embodiments may include some, none, or all of the recited advantages. Additionally, other technical advantages may become apparent to a person of ordinary skill in the art after reading the foregoing drawings and description.

[0055] To assist the Patent Office and any readers of any patent issued on this application in interpreting the appended claims, the applicant wishes to note that unless the words "means for" or "step for" are expressly used in a particular claim, they do not intend to invoke 35 U.S.C. § 112(f) for any of the appended claims or claim elements.

Claims

1. A multi-core processor, comprising: A plurality of cores, including at least a first core and a second core; A shared peripheral device, including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; And A plurality of communication bridges, including at least a first bridge docking between the first core and the shared peripheral device and at least a second bridge docking between the second core and the shared peripheral device; Wherein: The first core is configured to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core; and The second core is configured to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

2. The multi-core processor according to claim 1, wherein, The shared peripheral device is configured to: In response to the first core programming the first interrupt register group, map a first interrupt request line to the first core; and In response to the second core programming the second interrupt register group, map a second interrupt request line to the second core.

3. The multi-core processor according to claim 1 or 2, wherein: The first interrupt register group includes a first static interrupt configuration for the first core to dynamically enable and disable interrupts based on channel data; and The second interrupt register group includes a second static interrupt configuration for the second core to dynamically enable and disable interrupts based on channel data.

4. The multi-core processor according to claim 1 or 2, wherein: The first interrupt register group includes a first static interrupt configuration for the first core to enable and disable endpoint-based interrupts; and The second interrupt register group includes a second static interrupt configuration for the second core to enable and disable endpoint-based interrupts.

5. The multi-core processor according to any one of claims 1-4, further comprising a bus matrix serving as an interface between the plurality of cores and the plurality of communication bridges.

6. The multi-core processor according to any one of claims 1-5, further comprising a software architecture configured to time-share access of the plurality of cores to the shared peripheral device.

7. The multi-core processor according to any one of claims 1-5, further comprising a software architecture configured to time-share access of the plurality of cores to the shared peripheral device between time-critical time periods and non-time-critical time periods.

8. The multi-core processor according to any one of claims 1-7, wherein, The plurality of cores are configured to dynamically reassign an interrupt of one core among the plurality of cores to a subset of one or more other cores among the plurality of cores based on an interrupt configuration setting and a configuration control mode, so as to perform load balancing on the interrupts.

9. A method for a multi-core processor, the multi-core processor having: a plurality of cores, including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges, including at least a first bridge docking between the first core and the shared peripheral device and at least a second bridge docking between the second core and the shared peripheral device, the method comprising: Configuring the first core to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core; and Configuring the second core to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

10. The method according to claim 9, further comprising: In response to the first core programming the first interrupt register group, mapping a first interrupt request line to the first core through the shared peripheral device; and In response to the second core programming the second interrupt register group, mapping a second interrupt request line to the second core through the shared peripheral device.

11. The method according to claim 9 or 10, wherein: The first interrupt register group includes a first static interrupt configuration for the first core to dynamically enable and disable interrupts based on channel data; and The second interrupt register group includes a second static interrupt configuration for the second core to dynamically enable and disable interrupts based on channel data.

12. The method according to claim 9 or 10, wherein: The first interrupt register group includes a first static interrupt configuration for the first core to enable and disable endpoint-based interrupts; and The second interrupt register group includes a second static interrupt configuration for the second core to enable and disable endpoint-based interrupts.

13. The method according to any one of claims 9-12, further comprising docking a bus matrix between the plurality of cores and the plurality of communication bridges.

14. The method according to any one of claims 9-13, further comprising time-division multiplexing the access of the plurality of cores to the shared peripheral device using a software architecture.

15. The method according to any one of claims 9-13, further comprising time-division multiplexing the access of the plurality of cores to the shared peripheral device between time-critical time periods and non-time-critical time periods using a software architecture.

16. The method according to any one of claims 9-15, further comprising dynamically reallocating an interrupt of one core among the plurality of cores to a subset of one or more other cores among the plurality of cores based on interrupt configuration settings and configuration control modes for load balancing of interrupts.

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