Coating process applied to sequencing chip
Patent Information
- Application Number
- CN202410121533.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-07-29
AI Technical Summary
The coating process of existing sequencing chips is unstable, affecting the chip quality and it is difficult to monitor whether the standards are met.
After forming a silicon oxide layer on the substrate surface and hydroxylation treatment, the thickness of the silicon oxide layer was measured using an ellipsometer, and then the amino acid layer was formed by chemical vapor deposition. The total thickness of the amino acid layer was measured using an ellipsometer to determine whether the coating process met the standards.
Accurate monitoring of the coating process is achieved, reducing the loss of the positive film and reducing production costs.
Smart Images
Figure CN120384270A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of biotechnology, and in particular to a coating process applied to a sequencing chip. Background Art
[0002] The microarray sequencing chip is one of the essential conditions for realizing high-throughput sequencing. The currently used DNA Nano Ball (DNB) sequencing technology needs to fix the DNB on the sequencing chip for the next sequencing biochemical reaction. Taking the currently used sequencing chip as an example, each chip surface has nearly 200 million DNB binding sites. In order to firmly fix the DNB on the binding sites, the surface of the sequencing chip needs to be aminated. The areas other than the non-binding sites on the chip surface need to be treated otherwise to minimize non-specific adsorption as much as possible and improve the sequencing quality.
[0003] In the manufacturing process of the sequencing chip, an aminated layer is generally formed on the silicon wafer through a coating process. When the coating process is unstable or does not meet the standards, it will affect the quality of the obtained sequencing chip. Summary of the Invention
[0004] One object of this application is to provide a coating process applied to a sequencing chip, which can monitor whether the coating process meets the standards.
[0005] One embodiment of this application provides a coating process applied to a sequencing chip, including the following steps: providing a substrate, the substrate including a dummy wafer or including a dummy wafer and a positive wafer; forming a silicon oxide layer on the surface of the substrate; performing hydroxylation treatment on the silicon oxide layer; using an ellipsometer to measure the thickness of the silicon oxide layer on the dummy wafer after hydroxylation treatment; forming an aminated layer on the surface of the silicon oxide layer after hydroxylation treatment by chemical vapor deposition; using the ellipsometer to measure the total thickness of the silicon oxide layer and the aminated layer on the dummy wafer; obtaining the thickness of the aminated layer based on the thickness value measured by the ellipsometer; comparing the thickness of the aminated layer with a preset thickness to determine whether the coating process meets the standards.
[0006] In some embodiments, the hydroxylation treatment is performed by heating.
[0007] In some embodiments, the heating conditions for the hydroxylation treatment include: a heating temperature of 450 - 550 °C, a heating time of 1.5 - 2.5 h, and a heating atmosphere of air or oxygen.
[0008] In some embodiments, the substrate after hydroxylation treatment is placed at room temperature for less than 2 days.
[0009] In some embodiments, the matrix after hydroxylation treatment is placed in a dry sealed container.
[0010] In some embodiments, a desiccant is placed in the sealed container.
[0011] In some embodiments, the substance used to form the amination layer by the chemical vapor deposition method is 3 - aminopropyl - trimethoxysilane.
[0012] In some embodiments, the matrix includes at least one of a silicon wafer, a glass wafer, a metal wafer, or a plastic wafer.
[0013] In some embodiments, the step of "forming an amination layer on the surface of the hydroxylated silica layer by chemical vapor deposition" includes: placing the hydroxylated matrix on both sides of the reaction chamber of the chemical vapor deposition equipment.
[0014] The coating process for sequencing chips provided by the embodiments of the present application monitors whether the coating process meets the standard by measuring the thickness of the amination layer formed on the companion wafer through the coating process. The method is simple and easy to operate. Moreover, using an ellipsometer to measure the thickness of the amination layer on the companion wafer has high precision and is conducive to monitoring whether the coating process meets the standard. In addition, by measuring the thickness of the amination layer on the companion wafer instead of the thickness of the amination layer on the main wafer, it is possible to monitor whether the coating process for manufacturing sequencing chips meets the standard, reduce the loss of the main wafer, and lower the production cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:
[0016] Figure 1 is a cross - sectional schematic diagram of a matrix provided by an embodiment of the present application.
[0017] Figure 2 is Figure 1 a cross - sectional schematic diagram after forming a silica layer on the shown matrix.
[0018] Figure 3 is Figure 2 a cross - sectional schematic diagram after forming an amination layer on the shown silica layer.
[0019] MAIN ELEMENT SYMBOL DESCRIPTION
[0020] Matrix 10
[0021] Silica layer 20
[0022] Amination layer 30 DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] The technical solutions in the embodiments of the present application will be described clearly and in detail below. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0024] The professional terms used herein are for the purpose of describing specific embodiments and are not intended to limit this application. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "comprising", when used in this specification, refers to the presence of the recited features, values, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, values, steps, operations, elements, components, and / or combinations thereof. When describing the embodiments of this application, the use of "may" means "one or more embodiments of this application".
[0025] An embodiment of the present application provides a coating process applied to a sequencing chip, including the following steps.
[0026] Step S1, refer to Figure 1 , and provide a substrate 10.
[0027] The substrate 10 is used to prepare a sequencing chip. The substrate 10 includes a blank wafer or includes a blank wafer and a positive wafer. The blank wafer is used to prepare a sequencing chip used as a test chip, and the positive wafer is used to prepare a sequencing chip for sequencing. The substrate 10 can be selected from at least one of a silicon wafer, a glass wafer, a metal wafer, or a plastic wafer. That is, both the blank wafer and / or the positive wafer can be selected from at least one of a silicon wafer, a glass wafer, a metal wafer, or a plastic wafer. In this embodiment, the substrate 10 is a silicon wafer.
[0028] Step S2, refer to Figure 2 , and form a silicon oxide layer 20 on the surface of the substrate 10.
[0029] The silicon oxide layer 20 is composed of silicon dioxide. In this embodiment, the silicon oxide layer 20 is formed on the surface of the silicon wafer by a thermal oxidation process. The thickness of the silicon oxide layer 20 is 40 - 60 nm, preferably 50 nm.
[0030] Step S3, perform hydroxylation treatment on the silicon oxide layer 20.
[0031] Through the hydroxylation treatment, hydroxyl groups are introduced on the surface of the silicon oxide layer 20, enhancing the activity of the surface of the silicon oxide layer 20 and improving the hydrophilicity. The hydroxyl groups are provided by the silanol groups (Si-OH) formed after the silicon oxide layer 20 ionizes and adsorbs hydroxide ions in water. These hydroxyl groups can react with chemical substances to connect amino groups on the surface of the silicon oxide layer 20.
[0032] In this embodiment, hydroxylation treatment is carried out by heating. Specifically, the substrate 10 formed with the silicon oxide layer 20 is placed in a muffle furnace for heating to achieve hydroxylation. The heating conditions for the hydroxylation treatment include: the heating temperature is 450 - 550 °C, preferably 500 °C; the heating time is 1.5 - 2.5 h, preferably 2 h; and the heating atmosphere is air or oxygen. During the heating process, the silicon-oxygen bonds on the surface of the silicon oxide layer 20 are broken, and then react with the water vapor in the muffle furnace to generate silanol groups.
[0033] In another embodiment, hydroxylation treatment is carried out by plasma treatment and hydrophilic treatment in sequence. Among them, a Si - dangling bond is formed on the surface of the silicon oxide layer 20 by plasma treatment using a plasma cleaner, and a silanol bond is formed on the surface of the silicon oxide layer 20 by hydrophilic treatment. The plasma gas source is air or oxygen, and the surface of the silicon oxide layer 20 is bombarded with plasma to break the Si - O bonds in the silicon oxide layer 20 to form Si - dangling bonds. The reagent for hydrophilic treatment is a mixed solution of ammonia water, hydrogen peroxide and water or deionized water. In the hydrophilic treatment, the hydroxyl groups of the hydrophilic treatment reagent are adsorbed by the silicon dangling bonds on the surface of the silicon oxide layer after plasma treatment to form silanol bonds.
[0034] Silanol groups are unstable. As the exposure time in air prolongs, the silanol groups will gradually be passivated and return to the stable silicon-oxygen bonds. Therefore, when the substrate 10 after hydroxylation treatment is placed at room temperature for a period of time, the hydroxyl groups on the surface of the silicon oxide layer 20 will be passivated, which will affect the subsequent reaction between the chemical substance and the hydroxyl groups, and further affect the thickness of the subsequent formed aminated layer. In some embodiments, the substrate 10 after hydroxylation treatment is placed at room temperature for less than 2 days. In this application, room temperature refers to the indoor ambient temperature, generally 20 - 30 °C. When the time that the substrate 10 after hydroxylation treatment is placed at room temperature is within the above range, fewer hydroxyl groups on the surface of the silicon oxide layer 20 are passivated, and the influence on the thickness of the subsequent formed aminated layer is smaller, improving the accuracy of the thickness measurement of the aminated layer. When the time that the substrate 10 after hydroxylation treatment is placed at room temperature is greater than 2 days, more hydroxyl groups on the surface of the silicon oxide layer 20 are passivated, and the influence on the thickness of the aminated layer is greater.
[0035] In some embodiments, the substrate 10 after hydroxylation treatment is placed in a dry sealed container to reduce the risk of passivation of the hydroxyl groups on the surface of the silicon oxide layer 20. In some embodiments, a desiccant is placed in the sealed container to reduce the humidity inside the container, and further reduce the risk of passivation of the hydroxyl groups on the surface of the silicon oxide layer 20. Specifically, the substrate 10 after hydroxylation treatment is placed in a dry Lock&Lock box or placed in a nitrogen cabinet.
[0036] Step S4, measure the thickness of the silicon oxide layer 20 on the companion wafer after hydroxylation treatment using an ellipsometer. As Figure 2 shown, the thickness of the silicon oxide layer 20 is t1 nm.
[0037] The ellipsometer has high measurement accuracy. Measuring the thickness using an ellipsometer can improve the accuracy of the measured thickness; and measuring the thickness of the silicon oxide layer 20 on the companion wafer instead of the silicon oxide layer 20 on the main wafer can reduce the loss of the main wafer caused by measurement. In step S4, the thickness of the silicon oxide layer 20 is the average value of the thicknesses obtained by measuring multiple times using an ellipsometer. During measurement, the companion wafer after hydroxylation treatment is placed at a fixed position on the sample stage of the ellipsometer for multiple measurements. The measurement incident angle of the ellipsometer is 60° - 70°, for example, 60°, 65°, 70°.
[0038] Step S5, please refer to Figure 3 , form an aminated layer 30 on the surface of the silicon oxide layer 20 after hydroxylation treatment by chemical vapor deposition.
[0039] The aminated layer 30 has amino groups. Through the chemical vapor deposition coating process, a dense aminated layer 30 can be formed on the surface of the silicon oxide layer 20. Specifically, step S5 includes: placing the matrix 10 after hydroxylation treatment on both sides of the reaction chamber of the chemical vapor deposition equipment, and performing chemical vapor deposition to form an aminated layer 30 on the surface of the silicon oxide layer 20. During chemical vapor deposition, the companion wafer is placed on both sides of the reaction chamber so that the companion wafer does not hinder the entry of the main wafer into the reaction chamber, which is beneficial to improving production efficiency. Among them, the substance used to form the aminated layer 30 by chemical vapor deposition is 3-aminopropyl-trimethoxysilane (APTM S), and the hydroxyl group reacts with 3-aminopropyl-trimethoxysilane to form amino groups grafted on the silicon hydroxyl group.
[0040] Step S6, measure the total thickness of the silicon oxide layer 20 and the aminated layer 30 on the companion wafer using an ellipsometer. As Figure 3 shown, the total thickness of the silicon oxide layer 20 and the aminated layer 30 is t2 nm.
[0041] In step S6, the total thickness of the silicon oxide layer 20 and the aminated layer 30 is the average value of the thicknesses obtained by measuring multiple times using an ellipsometer. During measurement, the companion wafer formed with the silicon oxide layer 20 and the aminated layer 30 is placed at a fixed position on the sample stage of the ellipsometer for multiple measurements. The measurement incident angle of the ellipsometer is 60° - 70°, for example, 60°, 65°, 70°.
[0042] Step S7, obtain the thickness of the aminated layer 30 based on the thickness value measured by the ellipsometer.
[0043] As Figure 3As shown, the thickness of the amination layer 30 is t nm, where t = t2 - t1. The thickness t1 of the silicon oxide layer 20 and the total thickness t2 of the silicon oxide layer 20 and the amination layer 30 are measured by an ellipsometer, and the thickness t of the amination layer 30 is indirectly measured, improving the measurement accuracy of the thickness of the amination layer 30. It can be understood that when the coating process is performed on the spacer and the wafer simultaneously, the thickness of the amination layer 30 on the surface of the wafer is the same as the thickness of the amination layer 30 on the surface of the spacer; when only the spacer is subjected to the coating process, the thickness of the amination layer 30 on the surface of the spacer is the same as the thickness of the amination layer 30 formed on the surface of the wafer coated with the same coating process. Therefore, the thickness of the amination layer 30 on the surface of the spacer can be used to indirectly reflect the thickness of the amination layer 30 on the surface of the wafer.
[0044] Step S8, compare the thickness of the amination layer 30 with a preset thickness to determine whether the coating process meets the standard. When the thickness of the amination layer 30 formed by chemical vapor deposition is the same as the preset thickness, the chemical vapor deposition coating process meets the standard. When the substrate 10 includes a spacer and a wafer, it indicates that the sequencing chip made from the wafer coated simultaneously with the spacer is a qualified product, and the qualified coating process can be directly used for subsequent coating of the wafer. When the substrate 10 only includes a spacer, the qualified coating process can be directly used for coating the wafer. When the thickness of the amination layer 30 formed by chemical vapor deposition is different from the preset thickness, the chemical vapor deposition coating process does not meet the standard. When the substrate 10 includes a spacer and a wafer, it indicates that the sequencing chip made from the wafer coated simultaneously with the spacer is an unqualified product, and the unqualified coating process needs to be adjusted, and then the substrate 10 is coated until it is determined that the coating process meets the standard. It can be directly used for subsequent coating of the wafer. When the substrate 10 only includes a spacer, the unqualified coating process needs to be adjusted, and then the spacer is coated until it is determined that the coating process meets the standard and then the wafer is coated.
[0045] The coating process for sequencing chips provided by the embodiments of the present application monitors whether the coating process meets the standard by measuring the thickness of the amination layer 30 formed on the spacer through the coating process. The method is simple and easy to operate. Moreover, using an ellipsometer to measure the thickness of the amination layer 30 on the spacer has high accuracy and is conducive to monitoring whether the coating process meets the standard. In addition, by measuring the thickness of the amination layer 30 on the spacer instead of measuring the thickness of the amination layer 30 on the wafer, to monitor whether the coating process for manufacturing the sequencing chip meets the standard, the loss of the wafer can be reduced and the production cost can be lowered.
[0046] The above-disclosed is only the preferred embodiment of the present application. Of course, the present application cannot be limited by this. Therefore, the equivalent changes made according to the present application still fall within the scope covered by the present application.
Claims
1. A coating process applied to a sequencing chip, characterized in that, Including the following steps: Providing a substrate, the substrate including a cover slip or including a cover slip and a positive film; Forming a silicon oxide layer on the surface of the substrate; Performing hydroxylation treatment on the silicon oxide layer; Measuring the thickness of the silicon oxide layer after hydroxylation treatment on the cover slip using an ellipsometer; Forming an amination layer on the surface of the silicon oxide layer after hydroxylation treatment by chemical vapor deposition; Measuring the total thickness of the silicon oxide layer and the amination layer on the cover slip using the ellipsometer; Obtaining the thickness of the amination layer based on the thickness value measured by the ellipsometer; Comparing the thickness of the amination layer with a preset thickness to determine whether the coating process meets the standard.
2. The coating process according to claim 1, wherein, Performing the hydroxylation treatment by heating.
3. The coating process according to claim 2, characterized in that, The heating conditions for performing the hydroxylation treatment include: a heating temperature of 450 - 550 °C, a heating time of 1.5 - 2.5 h, and a heating atmosphere of air or oxygen.
4. The coating process according to claim 1, characterized in that, Placing the substrate after hydroxylation treatment at room temperature for less than 2 days.
5. The coating process according to claim 1, wherein Placing the substrate after hydroxylation treatment in a dry sealed container.
6. The coating process according to claim 5, characterized in that, A desiccant is placed in the sealed container.
7. The coating process according to claim 1, wherein The substance used to form the amination layer by the chemical vapor deposition is 3 - aminopropyl - trimethoxysilane.
8. The coating process according to claim 1, wherein The substrate includes at least one of a silicon wafer, a glass sheet, a metal sheet, or a plastic sheet.
9. The coating process according to claim 1, characterized in that, The step "forming an amination layer on the surface of the silicon oxide layer after hydroxylation treatment by chemical vapor deposition" includes: Placing the substrate after hydroxylation treatment on both sides of the reaction chamber of the chemical vapor deposition equipment.