Inverted packaging structure of silicon optical chip

Abstract

The invention relates to the technical field of chip packaging, and discloses a silicon optical chip flip packaging structure which comprises a PCB substrate, a silicon optical chip, an optical fiber array and a lens assembly, the upper surface of the PCB substrate is provided with a containing groove, the silicon optical chip is arranged on the upper surface of the PCB substrate in a flip mode, and a positioning structure and the silicon optical chip are arranged at intervals; the positioning structure is provided with a first coupling surface, and the silicon optical chip is provided with a second coupling surface overhung in the accommodating groove and an optical waveguide extending to the second coupling surface. A glue blocking part is further arranged on the bottom face, close to the second coupling face, of the silicon optical chip, an overflow gap is formed between the glue blocking part and the PCB substrate, the glue blocking part forms a transverse barrier on the bottom face of the silicon optical chip, the overflow gap allows glue to overflow and limits a diffusion path, and filling glue is prevented from being accumulated in an optical area of the silicon optical chip. The surface of the glue blocking part is arranged to be the lyophobic surface, so that the filling glue is prevented from crossing the glue blocking part to flow to the second coupling surface due to wetting diffusion, and the problem of pollution of the coupling surface and the lens caused by overflow of the filling glue is eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and particularly to a flip-chip packaging structure for a silicon photonics chip. Background Art

[0002] Currently, a silicon photonics chip is an optoelectronic integrated device made of a silicon-based material, which includes optical waveguides, modulators, detectors, coupling structures, etc. The silicon photonics chip has advantages such as high integration, low loss, and high transmission rate, and has become the core device of an optical communication system.

[0003] For example, a Chinese invention patent with an application publication number of CN117406350A and an application publication date of January 16, 2024 discloses a flip-chip bonding structure and method for a laser and a silicon optical waveguide, which includes: a silicon substrate having a first placement groove, and the bottom surface of the first placement groove of the silicon substrate is provided with a second placement groove, so that a step is formed at the junction of the first placement groove and the second placement groove, and a solder is placed in the second placement groove; a silicon photonics chip fixedly provided on the silicon substrate and located on one side of the first placement groove, and a first waveguide structure is provided in the silicon photonics chip; a laser chip placed in the first placement groove, and the laser chip is supported on the step, and the laser chip is electrically connected to the silicon substrate through the solder.

[0004] Among them, the step includes a first step on the side of the laser chip close to the silicon photonics chip, which can prevent the underfill glue from overflowing from the bottom of the laser chip after the chip mounting is completed. However, the silicon photonics chip is arranged on the PCB substrate in a flip-chip manner, and glue needs to be filled between the silicon photonics chip and the PCB substrate, and the glue may still overflow to the coupling end face of the waveguide, causing pollution to the coupling end face and affecting the coupling accuracy and reliability of the optical signal. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that when glue is filled between the silicon photonics chip and the PCB substrate, the glue may still overflow to the coupling end face of the waveguide, causing pollution to the coupling end face and affecting the coupling accuracy and reliability of the optical signal.

[0006] To solve the above technical problem, the present invention provides a technical solution for a flip-chip packaging structure of a silicon photonics chip: the flip-chip packaging structure of the silicon photonics chip includes a PCB substrate, a silicon photonics chip, an optical fiber array, and a lens assembly. A placement groove is provided on the upper surface of the PCB substrate, and a positioning structure is provided at the end of the optical fiber array, and the positioning structure is fixedly installed in the placement groove; The silicon photonics chip is flip-chip installed on the upper surface of the PCB substrate and is electrically connected to the PCB substrate. Along the length direction of the optical fiber array, the positioning structure and the silicon photonics chip are arranged at intervals; the positioning structure has a first coupling surface facing the silicon photonics chip, and the silicon photonics chip has a second coupling surface extending above the placement groove; The silicon photonic chip is provided with an optical waveguide extending to the second coupling surface. The lens assembly includes a first lens disposed on the first coupling surface and aligned with the optical fiber, and a second lens disposed on the second coupling surface and aligned with the optical waveguide. A glue blocking portion is further provided on the bottom surface of the silicon photonic chip near the second coupling surface. Along the width direction of the optical fiber array, the coverage range of the glue blocking portion is greater than the distribution width of the optical waveguide. A filling glue is provided between the silicon photonic chip and the PCB substrate, and an overflow gap is provided between the glue blocking portion and the PCB substrate. The surface of the glue blocking portion is a hydrophobic surface, which is used to form surface repulsion with the filling glue.

[0007] Furthermore, the hydrophobic surface is a perfluoropolyether coating, a fluorosilane SAM coating or a nano-composite fluorine coating. The surface energy of the hydrophobic surface is less than 25 mN / m, and the heat-resistant temperature is greater than 200 °C.

[0008] Furthermore, the protrusion height of the glue blocking portion is h, and the distance between the bottom surface of the silicon photonic chip and the upper surface of the PCB substrate is H, satisfying: 0.1H ≤ h ≤ 0.5H.

[0009] Furthermore, the value range of the protrusion height h of the glue blocking portion is: 5 μm ≤ h ≤ 30 μm, and the value range of the minimum width d of the overflow gap is: 40 μm ≤ d ≤ 75 μm.

[0010] Furthermore, the glue blocking portion has a guiding portion disposed away from the second coupling surface. The guiding portion is disposed in an inclined, arc-shaped or stepped manner; in the direction from the middle of the silicon photonic chip to the second coupling surface, the guiding portion is disposed towards the side gradually away from the silicon photonic chip.

[0011] Furthermore, one side edge of the accommodating groove corresponding to the second coupling surface is an overflow glue edge. The glue blocking portion is disposed at intervals directly above the overflow glue edge. The glue blocking portion further has an arc portion located at the upper inner part of the accommodating groove. The arc portion is arranged in a circular arc shape with the top of the overflow glue edge as the center of the circle.

[0012] Furthermore, a micro-nano rough structure is provided on the surface of the hydrophobic surface. The micro-nano rough structure is nano-silica embedded in a fluoropolymer.

[0013] Furthermore, a plurality of micro-copper pillars are provided on the bottom surface of the silicon photonic chip. The height of the micro-copper pillars is 50 μm to 80 μm. The optical waveguide is disposed at a position near the bottom surface of the silicon photonic chip; a PI layer is further provided on the bottom surface of the optical waveguide. The glue blocking portion is integrally formed with the PI layer, or the glue blocking portion is made by a dispensing process.

[0014] Further, the flip-chip packaging structure of the silicon photonics chip further includes a driver and a transimpedance amplifier. The driver and the transimpedance amplifier are disposed on the upper surface of the PCB substrate and electrically connected to the PCB substrate. The silicon photonics chip and the driver and the transimpedance amplifier are arranged at intervals. Alternatively, the driver and the transimpedance amplifier are flip-chip mounted on the surface of the silicon photonics chip away from the PCB substrate. The silicon photonics chip is provided with through-silicon vias in its thickness direction, and the through-silicon vias are filled with conductor posts. The conductor posts electrically connect the PCB substrate and the driver and the transimpedance amplifier.

[0015] Further, the positioning structure includes a bottom plate and a cover plate. The bottom plate is fixedly disposed in the accommodating groove, the cover plate is attached to the surface of the bottom plate, and a plurality of optical fibers of the fiber array are positioned and installed between the bottom plate and the cover plate. The plurality of optical fibers of the fiber array are spaced apart along the width direction of the fiber array.

[0016] Compared with the prior art, a flip-chip packaging structure of a silicon photonics chip of the present invention has the following beneficial effects: The flip-chip packaging structure of the silicon photonics chip adopts a design form of a PCB substrate, a silicon photonics chip, a fiber array, and a lens assembly. An accommodating groove is formed on the upper surface of the PCB substrate. The silicon photonics chip is flip-chip mounted on the upper surface of the PCB substrate, and the positioning structure and the silicon photonics chip are arranged at intervals in the length direction; the positioning structure has a first coupling surface, the silicon photonics chip has a second coupling surface extending into the accommodating groove, the silicon photonics chip is provided with an optical waveguide extending to the second coupling surface, and the lens assembly includes a first lens disposed on the first coupling surface and aligned with the optical fiber, and a second lens disposed on the second coupling surface and aligned with the optical waveguide.

[0017] By using a flip-chip process to attach the silicon photonics chip to the upper surface of the PCB substrate, the signal loss during high-speed transmission caused by traditional gold wire connection is avoided; the fiber array is installed in the accommodating groove by the positioning structure in a sunk manner, so that the fiber array can adapt to the small distance between the optical waveguide of the silicon photonics chip and the PCB substrate, ensuring that the optical path height of the fiber array can be compressed to 50 μm to 75 μm. The vertical height of the first coupling surface and the second coupling surface relative to the PCB substrate is effectively reduced, ensuring the alignment coupling of the optical signal between the fiber array and the silicon photonics chip, and meeting the packaging requirements of high-density optical interconnection.

[0018] Among them, a glue blocking portion is further provided on the bottom surface of the silicon photonics chip near the second coupling surface. Along the width direction of the fiber array, the coverage range of the glue blocking portion is larger than the distribution width of the optical waveguide. An overflow gap is provided between the glue blocking portion and the PCB substrate. The glue blocking portion forms a lateral barrier on the bottom surface of the silicon photonics chip to directly block the glue flow to the second coupling surface. At the same time, the overflow gap also allows the glue to overflow and restricts the diffusion path, preventing the filling glue from accumulating in the optical area of the silicon photonics chip. More importantly, the surface of the glue blocking portion is set as a hydrophobic surface, so that the contact angle between the filling glue and the surface of the glue blocking portion is >90°, forming a surface repulsion effect.

[0019] In the flip-chip packaging process, the filling glue overflows outward due to capillary action or pressure. Under the synergistic action of the surface repulsion effect of the hydrophobic surface and the self-surface tension of the filling glue, the filling glue tends to automatically contract toward the PCB substrate side, avoiding the filling glue from flowing across the glue blocking portion to the second coupling surface due to wetting diffusion, eliminating the problem of coupling surface and lens contamination caused by the overflow of the filling glue, and ensuring the coupling accuracy and reliability of the optical signal. Description of the Drawings

[0020] Figure 1 is a schematic plan view of the flip-chip packaging structure of the silicon photonics chip in the embodiment of the present invention; Figure 2 is a schematic cross-sectional view of the flip-chip packaging structure of the silicon photonics chip in the embodiment of the present invention; Figure 3 is a schematic view of the bottom surface of the silicon photonics chip in the embodiment of the present invention; Figure 4 is a partial cross-sectional view of the flip-chip packaging structure of the silicon photonics chip in other embodiments of the present invention; Figure 5 is a schematic cross-sectional view of the flip-chip packaging structure of the silicon photonics chip in other embodiments of the present invention; Figure 6 is Figure 5 an enlarged schematic view of the silicon photonics chip in In the figure: 1, PCB substrate; 10, accommodation groove; 11, glue overflow edge; 2, silicon photonics chip; 21, second coupling surface; 22, optical waveguide; 23, glue blocking portion; 230, hydrophobic surface; 231, guiding portion; 232, arc portion; 24, overflow gap; 25, micro copper column; 26, silicon through hole; 27, conductor column; 28, PI layer; 3, fiber array; 30, positioning structure; 31, first coupling surface; 32, bottom plate; 33, cover plate; 4, lens assembly; 41, first lens; 42, second lens; 5, driver and transimpedance amplifier; 6, integrated circuit IC; 7, passive component. Detailed Embodiments

[0021] The specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0022] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. in the present invention is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0023] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0024] In the present invention, unless otherwise clearly specified and defined, the terms "mounted", "connected", "connected to", "fixed" and other terms should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0025] As Figures 1 to 3 shown, a flip-chip packaging structure of a silicon photonic chip according to an embodiment of the present invention includes a PCB substrate 1, a silicon photonic chip 2, an optical fiber array 3, and a lens assembly 4. A receiving groove 10 is formed on the upper surface of the PCB substrate 1. A positioning structure 30 is provided at the end of the optical fiber array 3, and the positioning structure 30 is fixedly installed in the receiving groove 10; the silicon photonic chip 2 is flip-chip installed on the upper surface of the PCB substrate 1 and is electrically connected to the PCB substrate 1. Along the length direction of the optical fiber array 3, the positioning structure 30 and the silicon photonic chip 2 are arranged at intervals; the positioning structure 30 has a first coupling surface 31 facing the silicon photonic chip 2, and the silicon photonic chip 2 has a second coupling surface 21 extending above the receiving groove 10.

[0026] The silicon photonics chip 2 is provided with an optical waveguide 22 extending to the second coupling surface 21. The lens assembly 4 includes a first lens 41 disposed on the first coupling surface 31 and aligned with the optical fiber, and a second lens 42 disposed on the second coupling surface 21 and aligned with the optical waveguide 22. Near the bottom surface of the silicon photonics chip 2 and close to the second coupling surface 21, there is also a glue blocking portion 23. Along the width direction of the optical fiber array 3, the coverage range of the glue blocking portion 23 is greater than the distribution width of the optical waveguide 22. There is a filling glue between the silicon photonics chip 2 and the PCB substrate 1, and an overflow gap 24 is provided between the glue blocking portion 23 and the PCB substrate 1. The surface of the glue blocking portion 23 is a hydrophobic surface 230, which is used to form surface repulsion with the filling glue.

[0027] The flip-chip packaging structure of the silicon photonics chip adopts the design form of the PCB substrate 1, the silicon photonics chip 2, the optical fiber array 3 and the lens assembly 4. The upper surface of the PCB substrate 1 is provided with a receiving groove 10. The silicon photonics chip 2 is flip-chip mounted on the upper surface of the PCB substrate 1, and the positioning structure 30 is arranged at intervals with the silicon photonics chip 2 along the length direction. The positioning structure 30 has a first coupling surface 31, and the silicon photonics chip 2 has a second coupling surface 21 that overhangs the receiving groove 10. The silicon photonics chip 2 is provided with an optical waveguide 22 extending to the second coupling surface 21. The lens assembly 4 includes a first lens 41 disposed on the first coupling surface 31 and aligned with the optical fiber, and a second lens 42 disposed on the second coupling surface 21 and aligned with the optical waveguide 22.

[0028] By using the flip-chip process to bond the silicon photonics chip 2 to the upper surface of the PCB substrate 1, the excessive signal loss during high-speed transmission caused by traditional gold wire connection is avoided. The optical fiber array 3 is installed in the receiving groove 10 by sinking through the positioning structure 30, enabling the optical fiber array 3 to adapt to the small distance between the optical waveguide 22 of the silicon photonics chip 2 and the PCB substrate 1, and ensuring that the optical path height of the optical fiber array 3 can be compressed to 50μm - 75μm. The vertical height of the first coupling surface 31 and the second coupling surface 21 relative to the PCB substrate 1 is effectively reduced, ensuring the alignment coupling of the optical signal between the optical fiber array 3 and the silicon photonics chip 2, and meeting the packaging requirements of high-density optical interconnection.

[0029] Among them, near the bottom surface of the silicon photonics chip 2 and close to the second coupling surface 21, there is also a glue blocking portion 23. Along the width direction of the optical fiber array 3, the coverage range of the glue blocking portion 23 is greater than the distribution width of the optical waveguide 22, and an overflow gap 24 is provided between the glue blocking portion 23 and the PCB substrate 1. The glue blocking portion 23 forms a lateral barrier on the bottom surface of the silicon photonics chip 2, which is used to directly block the glue flow to the second coupling surface 21. At the same time, the overflow gap 24 also allows the glue to overflow and restricts the diffusion path, preventing the filling glue from accumulating in the optical area of the silicon photonics chip 2. More importantly, the surface of the glue blocking portion 23 is set as a hydrophobic surface 230, so that the contact angle between the filling glue and the surface of the glue blocking portion 23 > 90°, forming a surface repulsion effect.

[0030] In the flip-chip packaging process, the underfill glue overflows outward due to capillary action or pressure. Under the combined action of the surface repulsion effect of the liquid-repellent surface 230 and the self-surface tension of the underfill glue, the underfill glue tends to automatically contract towards the PCB substrate 1 side, avoiding the underfill glue from wetting and spreading across the glue-blocking part 23 to the second coupling surface 21, eliminating the problem of coupling surface and lens contamination caused by the overflow of the underfill glue, and ensuring the coupling accuracy and reliability of the optical signal.

[0031] It should be noted that the above-mentioned glue and underfill glue both refer to underfill glue, whose main component is epoxy resin, with a relatively low surface tension (30 - 45 mN / m), weak polarity, high viscosity when uncured but may wet and spread along the surface under capillary action. In this embodiment, the liquid-repellent surface 230 is a perfluoropolyether coating (PFPE), whose surface energy is less than 15 mN / m, with super liquid-repellent characteristics, enabling liquid epoxy resin to form a high contact angle to effectively inhibit wetting and spreading, and the heat-resistant temperature of the liquid-repellent surface 230 is greater than 200 °C, ensuring that it can withstand the high temperature of soldering without being damaged. To meet different usage requirements, in other embodiments, the liquid-repellent surface 230 can be selected as a fluorosilane SAM coating or a nano-composite fluorine coating, ensuring that the surface energy of the liquid-repellent surface 230 (<25 mN / m) is less than the surface tension of the underfill glue.

[0032] As Figure 2 shown, the protruding height of the glue-blocking part 23 is h, and the distance between the bottom surface of the silicon photonics chip 2 and the upper surface of the PCB substrate 1 is H, satisfying: 0.1H ≤ h ≤ 0.5H. Specifically, the value range of the protruding height h of the glue-blocking part 23 is: 5 μm ≤ h ≤ 30 μm, and the value range of the minimum width d of the overflow gap 24 is: 40 μm ≤ d ≤ 75 μm. The distance H between the bottom surface of the silicon photonics chip 2 and the upper surface of the PCB substrate 1, that is, the bonding height of the flip-chip of the silicon photonics chip 2, depends on the bump or solder ball height.

[0033] By limiting the height range of the glue-blocking part 23 protruding from the bottom surface of the silicon photonics chip 2, with its lower limit h ≥ 0.1H or 5 μm, it prevents the underfill glue from crossing the glue-blocking part 23 due to surface tension and causing contamination of the coupling surface; its upper limit h ≤ 0.5H or 30 μm avoids excessive squeezing of the overflow gap 24 of the underfill glue, ensuring that the underfill glue forms a complete filling between the silicon photonics chip 2 and the PCB substrate 1, and improving the reliability of the packaging of the silicon photonics chip 2. As a further preferred solution, when h = 15 μm and d = 60 μm are selected, the requirements of preventing glue contamination and smooth overflow are taken into account.

[0034] In other embodiments, the glue-blocking part 23 has a guiding part 231 arranged away from the second coupling surface 21, and the guiding part 231 is arranged in an inclined, arc-shaped or stepped manner; as Figure 4As shown, in the direction from the middle of the silicon photonics chip 2 to the second coupling surface 21, the guiding portion 231 is arranged on the side gradually away from the silicon photonics chip 2. One side edge of the accommodating groove 10 corresponding to the second coupling surface 21 is the glue overflow edge 11. The glue blocking portions 23 are arranged at intervals directly above the glue overflow edge 11. The glue blocking portions 23 also have an arc portion 232 located at the upper inner side of the accommodating groove 10. The arc portion 232 is arranged in an arc shape with the top of the glue overflow edge 11 as the center of the circle.

[0035] The guiding portion 231 of the glue blocking portion 23 is designed to be inclined, arc-shaped or stepped, so that a diversion channel gradually narrowing along the overflow direction is formed between the guiding portion 231 and the PCB substrate 1, ensuring that the filling glue can flow in a preset direction away from the silicon photonics chip 2, and combining with the liquid-repellent surface 230 to increase the contact angle, achieving a super liquid-repellent effect. The arc portion 232 of the glue blocking portion 23 is located at the upper inner side of the accommodating groove, with the top of the glue overflow edge 11 as the center of the circle, forming a concave arc surface, ensuring that the filling glue reliably flows along the tangent direction of the arc portion 232 after passing through the glue overflow edge 11, and optimizing the flow path of the filling glue when overflowing.

[0036] As a further preferred solution, a micro-nano rough structure (not shown in the figure) is provided on the surface of the liquid-repellent surface 230. The micro-nano rough structure is nano-silica embedded in fluoropolymer. It can not only modify the low-surface-energy substance of the liquid-repellent surface 230, but also increase the contact angle between the filling glue and the liquid-repellent surface 230, achieving a super liquid-repellent effect.

[0037] Among them, a plurality of micro-copper pillars 25 are provided on the bottom surface of the silicon photonics chip 2. The height of the micro-copper pillars 25 is 50 μm to 80 μm. The optical waveguide 22 is arranged at a position close to the bottom surface of the silicon photonics chip 2; a PI layer 28 is also provided on the bottom surface of the optical waveguide 22. The glue blocking portion 23 is integrally formed with the PI layer 28, or the glue blocking portion 23 is made by a dispensing process. Electrical interconnection between the silicon photonics chip 2 and the PCB substrate 1 is achieved through the micro-copper pillars 25 on the bottom surface. The PI layer 28 serves as a passivation layer 28 to cover the optical waveguide 22, which can reduce the direct contact between the optical waveguide 22 and the filling glue and avoid refractive index distortion of the optical waveguide 22 caused by the curing stress of the filling glue. The glue blocking portion 23 being integrally formed with the PI layer 28 can effectively eliminate the interface gap and can withstand a soldering high temperature of 300 °C; or, the glue blocking portion 23 is formed by dispensing, which is convenient for flexibly adjusting the shape of the glue blocking portion 23.

[0038] In this embodiment, the flip-chip packaging structure of the silicon photonics chip further includes a driver and a transimpedance amplifier 5. The driver and the transimpedance amplifier 5 are arranged on the upper surface of the PCB substrate 1 and electrically connected to the PCB substrate 1. The silicon photonics chip 2 and the driver and the transimpedance amplifier 5 are arranged at intervals. To meet different usage requirements, in other embodiments, the driver and the transimpedance amplifier 5 are flip-mounted on the surface of the silicon photonics chip 2 away from the PCB substrate 1, such as Figure 5 、Figure 6 As shown, a through-silicon via 26 is provided through the silicon photonic chip 2 in its thickness direction, and a conductor post 27 is filled in the through-silicon via 26. The conductor post 27 is electrically connected to the PCB substrate 1, the driver, and the transimpedance amplifier 5.

[0039] In addition, the positioning structure 30 includes a bottom plate 32 and a cover plate 33. The bottom plate 32 is fixedly arranged in the accommodation groove 10, and the cover plate 33 is attached to the surface of the bottom plate 32. A plurality of optical fibers of the optical fiber array 3 are positioned and installed between the bottom plate 32 and the cover plate 33, and the plurality of optical fibers of the optical fiber array 3 are spaced apart along the width direction of the optical fiber array 3. The bottom plate 32 and the cover plate 33 respectively position the plurality of optical fibers of the optical fiber array 3, ensuring that the plurality of optical fibers are equidistantly spaced along the width direction of the optical fiber array 3 and ensuring the accuracy of the optical fiber positions.

[0040] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and replacements can be made, and these improvements and replacements should also be regarded as the protection scope of the present invention.

Claims

1. A flip-chip packaging structure for a silicon photonics chip, characterized in that, It includes a PCB substrate, a silicon photonics chip, an optical fiber array and a lens assembly. An accommodation groove is formed on the upper surface of the PCB substrate, and a positioning structure is provided at the end of the optical fiber array. The positioning structure is fixedly installed in the accommodation groove. The silicon photonics chip is flip-chip mounted on the upper surface of the PCB substrate and electrically connected to the PCB substrate. Along the length direction of the optical fiber array, the positioning structure and the silicon photonics chip are arranged at intervals. The positioning structure has a first coupling surface facing the silicon photonics chip, and the silicon photonics chip has a second coupling surface extending above the accommodation groove. The silicon photonics chip is provided with an optical waveguide extending to the second coupling surface. The lens assembly includes a first lens disposed on the first coupling surface and aligned with the optical fiber, and a second lens disposed on the second coupling surface and aligned with the optical waveguide. A glue-blocking portion is further provided on the bottom surface of the silicon photonics chip near the second coupling surface. Along the width direction of the optical fiber array, the coverage range of the glue-blocking portion is larger than the distribution width of the optical waveguide. A filling glue is provided between the silicon photonics chip and the PCB substrate, and an overflow gap is provided between the glue-blocking portion and the PCB substrate. The surface of the glue-blocking portion is a hydrophobic surface, which is used to form surface repulsion with the filling glue.

2. The flip-chip packaging structure of the silicon photonics chip according to claim 1, characterized in that, The hydrophobic surface is a perfluoropolyether coating, a fluorosilane SAM coating or a nano-composite fluorine coating. The surface energy of the hydrophobic surface is less than 25 mN / m, and the heat-resistant temperature is greater than 200 °C.

3. The flip-chip packaging structure of the silicon photonics chip according to claim 2, characterized in that, The protruding height of the glue-blocking portion is h, and the distance between the bottom surface of the silicon photonics chip and the upper surface of the PCB substrate is H, satisfying: 0.1H ≤ h ≤ 0.5H.

4. The flip-chip packaging structure of the silicon photonics chip according to claim 2, wherein, The value range of the protruding height h of the glue-blocking portion is: 5 μm ≤ h ≤ 30 μm, and the value range of the minimum width d of the overflow gap is: 40 μm ≤ d ≤ 75 μm.

5. The flip-chip packaging structure of the silicon photonics chip according to claim 1, characterized in that, The glue-blocking portion has a guiding portion disposed away from the second coupling surface. The guiding portion is arranged in an inclined, arc-shaped or stepped shape. From the middle of the silicon photonics chip to the direction of the second coupling surface, the guiding portion is arranged to gradually move away from the side of the silicon photonics chip.

6. The flip-chip packaging structure of the silicon photonic chip according to claim 5, wherein, One side edge of the accommodation groove corresponding to the second coupling surface is an overflow edge. The glue-blocking portion is disposed directly above the overflow edge at intervals. The glue-blocking portion further has an arc portion located at the upper inner part of the accommodation groove. The arc portion is arranged in a circular arc shape with the top of the overflow edge as the center of the circle.

7. The flip-chip packaging structure of the silicon photonics chip according to claim 1, characterized in that, The surface of the hydrophobic surface is provided with a micro-nano rough structure, and the micro-nano rough structure is nano-silica embedded in a fluoropolymer.

8. The flip-chip packaging structure of the silicon photonics chip according to claim 1, wherein, A plurality of micro-copper pillars are provided on the bottom surface of the silicon photonics chip. The height of the micro-copper pillars is 50 μm to 80 μm. The optical waveguide is disposed at a position close to the bottom surface of the silicon photonics chip. A PI layer is further provided on the bottom surface of the optical waveguide. The glue-blocking portion is integrally formed with the PI layer, or the glue-blocking portion is made by a dispensing process.

9. The flip-chip packaging structure of the silicon photonics chip according to claim 1, wherein The flip-chip packaging structure of the silicon photonics chip further includes a driver and a transimpedance amplifier. The driver and the transimpedance amplifier are disposed on the upper surface of the PCB substrate and electrically connected to the PCB substrate. The silicon photonics chip and the driver and the transimpedance amplifier are arranged at intervals. Alternatively, the driver and the transimpedance amplifier are flip-chip mounted on the surface of the silicon photonics chip away from the PCB substrate. The silicon photonics chip is provided with through-silicon vias penetrating along its thickness direction, and the through-silicon vias are filled with conductor posts, and the conductor posts are electrically connected to the PCB substrate and the driver and the transimpedance amplifier.

10. The flip-chip packaging structure of the silicon photonics chip according to claim 1, characterized in that, The positioning structure includes a bottom plate and a cover plate. The bottom plate is fixedly arranged in the accommodating groove, the cover plate is attached to the surface of the bottom plate, and a plurality of optical fibers of the fiber array are positioned and installed between the bottom plate and the cover plate, and the plurality of optical fibers of the fiber array are spaced apart along the width direction of the fiber array.

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