Optical chip structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to an optical chip structure and a preparation method thereof. The optical chip structure comprises a supporting substrate, a first isolation layer located on the surface of one side of the supporting substrate and a photoelectric thin film layer located on the surface of the side, away from the supporting substrate, of the first isolation layer, the photoelectric thin film layer is provided with at least one first area and at least one second area, and a ridge-shaped waveguide structure is formed in the first area; the resistance of the first region is higher than that of the second region, and the low resistance of the second region can timely conduct charges generated by the photorefractive effect or the photovoltaic effect of the photoelectric film layer. The problem that a bias point of the electro-optical modulator changes along with time due to the fact that a non-uniform electric field is generated in the single crystal thin film and at the interface of the single crystal thin film is solved, meanwhile, the light transmittance of the thin film layer is guaranteed through high resistance of the first area, and the light loss of the structure is reduced through the ridge-shaped waveguide structure formed in the first area.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to an optical chip structure and a preparation method thereof. Background Art

[0002] An electro-optic modulator is mainly a modulator made based on the electro-optic effect of electro-optic materials. When a voltage is applied to an electro-optic material such as a lithium niobate crystal or a lithium tantalate crystal, the refractive index of the electro-optic material changes, thereby causing changes in the characteristics of the light wave passing through the electro-optic material. By using the electro-optic effect, modulation of parameters such as the phase, amplitude, intensity, and polarization state of an optical signal can be achieved.

[0003] When incident light irradiates a thin film made of an electro-optic material such as a lithium niobate crystal or a lithium tantalate crystal, due to the photorefractive effect or the photovoltaic effect of the above electro-optic material, charges will be generated on the surface of the thin film. Since the resistance of the above electro-optic material is relatively high, it is difficult for the charges to conduct, and these charges are non-uniformly distributed inside the single-crystal thin film and at the interface of the single-crystal thin film, thereby forming a non-uniform electric field, which causes inconsistent refractive index changes in different regions of the thin film, resulting in changes in the phase and intensity of the optical signal when passing through the thin film, and further causing the problem that the bias point of the electro-optic modulator changes with time. In the prior art, in order to solve the above problems, a reduction reaction is performed on a thin film made of an electro-optic material such as a lithium niobate crystal or a lithium tantalate crystal, so that the content of oxygen components in the crystal is reduced, thereby reducing the resistivity of the thin film. However, this will cause a decrease in the transmittance of the thin film, an increase in the optical loss of the crystal, and limit its application. Summary of the Invention

[0004] In view of the above problems in the prior art, the present application provides an optical chip structure that can avoid the problem that the bias point of an electro-optic modulator changes with time due to the photorefractive effect or the photovoltaic effect of electro-optic materials such as lithium niobate crystals or lithium tantalate crystals, and can also ensure the transmittance of the thin film and reduce the optical loss of the optical chip structure. The specific technical solutions are as follows:

[0005] On the one hand, the present application provides an optical chip structure, including:

[0006] A support substrate;

[0007] A first isolation layer located on one surface of the support substrate;

[0008] An optoelectronic thin film layer located on the surface of the first isolation layer away from the support substrate. The optoelectronic thin film layer is provided with at least one first region and a second region. The first region is formed with a ridge waveguide structure, and the resistance of the first region is higher than that of the second region.

[0009] In a possible implementation, the ridge waveguide structure includes a substrate region and a ridge waveguide region. The ridge waveguide region protrudes from one surface of the substrate region. The substrate region and the ridge waveguide region satisfy at least one of the following characteristics:

[0010] The protruding height of the ridge waveguide region protruding from one surface of the substrate region ranges from 50 to 600 nm;

[0011] The width of the ridge waveguide region ranges from 0.5 to 5 μm;

[0012] The thickness of the substrate region ranges from 50 to 600 nm.

[0013] In a possible implementation, the first region and the second region satisfy at least one of the following characteristics:

[0014] The area of the first region accounts for 1% - 20% of the total area of the optoelectronic thin film layer;

[0015] The area of the second region accounts for 80% - 99% of the total area of the optoelectronic thin film layer;

[0016] The resistivity of the first region ranges from 3×10 10 ~3×10 18 Ω·cm;

[0017] The resistivity of the second region ranges from 1×10 9 ~3×10 11 Ω·cm;

[0018] The content of the oxygen component in the first region is higher than that in the second region.

[0019] In a possible implementation, the optical chip structure further includes a second isolation layer located on the side of the support substrate away from the first isolation layer.

[0020] In a possible implementation, the first isolation layer and the second isolation layer satisfy at least one of the following characteristics:

[0021] The first isolation layer and the second isolation layer have the same thickness;

[0022] The first isolation layer and the second isolation layer are made of the same material.

[0023] In a possible implementation, the optical chip structure further includes a first defect layer located between the first isolation layer and the support substrate.

[0024] In a possible implementation, the optical chip structure further includes a second defect layer located on the surface of the support substrate away from the first defect layer.

[0025] In a possible implementation manner, the structure satisfies at least one of the following characteristics:

[0026] The thickness range of the first defect layer is 300 - 10000 μm;

[0027] The material of the first defect layer includes at least one of polysilicon, polysilicon after ion implantation, amorphous silicon, and single crystal silicon;

[0028] The first defect layer has the same thickness as the second defect layer;

[0029] The first defect layer and the second defect layer are made of the same material.

[0030] In a possible implementation manner, the structure satisfies at least one of the following characteristics:

[0031] The thickness range of the first isolation layer is 1 - 50 μm;

[0032] The thickness range of the second region is 50 - 600 nm;

[0033] The thickness range of the support substrate is 300 - 1000 μm;

[0034] The curvature range of the support substrate is -30 - 30 μm.

[0035] In a possible implementation manner, the structure satisfies at least one of the following characteristics:

[0036] The material of the first isolation layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide;

[0037] The material of the optoelectronic thin film layer includes at least one of lithium niobate, lithium tantalate, and barium titanate;

[0038] The support substrate includes at least one of silicon, silicon carbide, sapphire, and quartz.

[0039] In a possible implementation manner, the structure further includes an electrode structure located on the surface of the second region away from the first isolation layer.

[0040] On the other hand, the present application provides a method for preparing an optical chip structure, and the preparation method includes:

[0041] Providing a support substrate;

[0042] Forming a first isolation layer on one surface of the support substrate;

[0043] Forming an optoelectronic thin film layer on the surface of the first isolation layer away from the support substrate based on a patterning process;

[0044] The optoelectronic thin film layer is provided with at least one first region and a second region, a ridge waveguide structure is formed in the first region, and the resistance of the first region is higher than that of the second region.

[0045] In a possible implementation manner, forming the optoelectronic thin film layer on a surface of the first isolation layer away from the support substrate based on a patterning process includes:

[0046] A preset optoelectronic thin film layer is formed on a surface of the first isolation layer away from the support substrate, the preset optoelectronic thin film layer includes at least one first initial region and a second initial region, and the resistance of the first initial region is higher than that of the second initial region;

[0047] The preset optoelectronic thin film layer is subjected to a patterning etching process to form a ridge waveguide structure in the first initial region to obtain the first region, and the second initial region is thinned to obtain the second region.

[0048] In a possible implementation manner, forming the preset optoelectronic thin film layer on a surface of the first isolation layer away from the support substrate includes:

[0049] An initial optoelectronic thin film layer is formed on a surface of the first isolation layer away from the support substrate;

[0050] A patterned barrier layer is formed on the initial optoelectronic thin film layer, and the barrier layer shields a thin film layer region corresponding to the first region in the initial optoelectronic thin film layer;

[0051] The initial optoelectronic thin film layer with the patterned barrier layer is subjected to a reduction process to reduce the thin film layer region exposed by the barrier layer, and the barrier layer is removed to form the preset optoelectronic thin film layer.

[0052] In a possible implementation manner, before forming the optoelectronic thin film layer on a surface of the first isolation layer away from the support substrate based on a patterning process, the preparation method further includes: forming a second isolation layer on a surface of the support substrate away from the first isolation layer.

[0053] In a possible implementation manner, before forming the optoelectronic thin film layer on a surface of the first isolation layer away from the support substrate based on a patterning process, the preparation method further includes: forming a first defect layer between the first isolation layer and the support substrate.

[0054] In a possible implementation manner, before forming the optoelectronic thin film layer on a surface of the first isolation layer away from the support substrate based on a patterning process, the method further includes: forming a second defect layer on a surface of the support substrate away from the first defect layer.

[0055] Based on the above technical solution, the present application has the following beneficial effects: The technical solution of the present invention provides an optical chip structure, which includes a support substrate, a first isolation layer located on one surface of the support substrate, and an optoelectronic thin film layer located on the surface of the first isolation layer away from the support substrate. The optoelectronic thin film layer is provided with at least one first region and a second region. A ridge waveguide structure is formed in the first region, and the resistance of the first region is higher than that of the second region. By providing at least one first region and a second region on the optoelectronic thin film layer, wherein the resistance of the first region is higher than that of the second region, the low resistance of the second region can timely conduct the charges generated due to the photorefractive effect or the photovoltaic effect of the optoelectronic thin film layer, avoiding the problem that the bias point of the electro-optic modulator changes with time due to the generation of a non-uniform electric field inside the single crystal thin film and at the interface of the single crystal thin film. At the same time, the high resistance of the first region ensures the light transmittance of the thin film layer, reducing the loss of the optical signal of the structure. And a ridge waveguide structure is formed in the first region, which can not only effectively guide and limit the propagation of the optical signal, but also further reduce the loss of the optical signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0057] Figure 1 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0058] Figure 2 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0059] Figure 3 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0060] Figure 4 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0061] Figure 5 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0062] Figure 6 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0063] Figure 7 It is a schematic structural diagram of the optical chip structure in a specific embodiment of the present invention.

[0064] Figure 8 This is a top view of the optical chip structure without an electrode structure in a specific embodiment of the present invention.

[0065] Figure 9 This is a top view of the optical chip structure after adding an electrode mechanism in a specific embodiment of the present invention.

[0066] Figure 10 This is a schematic diagram of the preparation process of the preparation method of the optical chip structure of the present invention.

[0067] In the figure: 101 - support substrate, 102 - first isolation layer, 103 - optoelectronic thin film layer, 1031 - first region, 1032 - second region, 1033 - substrate region, 1034 - ridge waveguide region, 104 - second isolation layer, 105 - first defect layer, 106 - second defect layer, 107 - electrode structure, 108 - initial optoelectronic thin film layer, 109 - barrier layer, 110 - initial photoresist layer, 111 - patterned initial photoresist layer, 112 - patterned barrier layer, 113 - preset optoelectronic thin film layer, 1131 - first initial region, 1132 - second initial region, 114 - photoresist layer, 115 - patterned photoresist layer. Specific Embodiments

[0068] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of the present application.

[0069] For the terms defined below, unless a different definition is given elsewhere in the claims or in this specification, these definitions shall apply. All numerical values, whether or not explicitly indicated, are hereby defined as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a lower value and a higher value is defined as including all the numerical values included in that numerical range and all the sub - ranges included in that numerical range.

[0070] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0071] On the one hand, the following introduces an optical chip structure provided by an embodiment of the present application. As Figure 1 shown, it includes:

[0072] A support substrate 101;

[0073] In some embodiments, the support substrate 101 includes at least one of silicon, silicon carbide, sapphire and quartz. Silicon, sapphire and quartz all have high optical transmittance, which can ensure the effective transmission of optical signals and reduce optical loss, while silicon carbide has a large high breakdown electric field strength and can work under high voltage conditions without electrical breakdown, and can be applied to high voltage devices.

[0074] Specifically, the quartz is fused quartz or single crystal quartz.

[0075] In some embodiments, the thickness range of the support substrate 101 is 300 - 1000 μm. The thickness of the support substrate 101 can be any point value within the above range, and will not be enumerated here. When the thickness of the support substrate 101 is relatively large, it will cause an increase in the loss of light during propagation, and may also increase the manufacturing cost, while when the thickness of the support substrate 101 is too small, the mechanical strength of the chip will be reduced.

[0076] In some embodiments, the curvature range of the support substrate 101 is -30 - 30 μm. The curvature of the support substrate 101 can be any point value within the above range, and will not be enumerated here. By limiting the curvature range, the processability of the chip structure is ensured, and the increase in the difficulty of integration and manufacturing caused by too small a curvature of the support substrate 101 is avoided.

[0077] As Figure 1 shown, the optical chip structure of the present application further includes a first isolation layer 102 located on one side surface of the support substrate 101. Adding the first isolation layer 102 on one side surface of the support substrate 101 can prevent the mutual interference between the support substrate 101 and the optoelectronic thin film layer 103, and thus improve the stability of the electro-optic modulator.

[0078] In some embodiments, the material of the first isolation layer 102 includes at least one of silicon dioxide, silicon nitride, and aluminum oxide; the above materials all have good insulation and low dielectric constant, which can effectively prevent the mutual interference between different layers and reduce the loss of optical signals.

[0079] In some embodiments, the thickness range of the first isolation layer 102 is 1 - 50 μm. The thickness of the first isolation layer 102 can be any point value within the above range, and no enumeration is made here. By limiting the thickness range of the first isolation layer 102, it is avoided that the excessive thickness of the isolation layer increases the optical propagation loss, and the too small thickness of the isolation layer is difficult to ensure the isolation effect. Moreover, the isolation layer within the above thickness range can also reduce the microwave loss of the chip structure.

[0080] In some embodiments, as Figure 3 shown, the optical chip structure further includes a second isolation layer 104 located on the side of the support substrate 101 away from the first isolation layer 102. By adding the second isolation layer 104, the transmission and loss of optical signals can be further reduced, and the stability of the device can be improved.

[0081] In some embodiments, the first isolation layer 102 and the second isolation layer 104 have the same thickness. Two isolation layers with the same thickness can better balance the stress between the support substrate 101 and the optoelectronic thin film layer 103, making the stress distribution more uniform and improving the preparation yield of the optical chip structure.

[0082] Specifically, the thickness range of the second isolation layer 104 is 1 - 50 μm. The thickness of the second isolation layer 104 can be any point value within the above range, and no enumeration is made here.

[0083] In some embodiments, the first isolation layer 102 and the second isolation layer 104 are made of the same material. Using the same material can ensure that the thermal expansion coefficients of the two isolation layers are the same. At different working temperatures, the same thermal expansion coefficient can avoid the internal stress of the chip structure caused by temperature changes and ensure the performance and stability of the device.

[0084] Specifically, the material of the second isolation layer 104 includes at least one of silicon dioxide, silicon nitride, and aluminum oxide.

[0085] In some embodiments, as Figure 5 shown, the optical chip structure further includes a first defect layer 105 located between the first isolation layer 102 and the support substrate 101. The support substrate 101 may generate electrons under the irradiation of incident light, and the first defect layer 105 can absorb the electrons generated by the support substrate 101 to reduce the microwave loss of the device.

[0086] In some embodiments, the thickness of the first defect layer 105 ranges from 300 to 10,000 μm. The thickness of the first defect layer 105 can be any point value within the above range, and no enumeration is made here. The thickness of the first defect layer 105 affects the modulation efficiency, extinction ratio, and bandwidth of the electro-optic modulator. By defining the above thickness range, the performance such as the modulation efficiency, extinction ratio, and bandwidth of the electro-optic modulator is ensured.

[0087] In some embodiments, the material of the first defect layer 105 includes at least one of polysilicon, ion-implanted polysilicon, amorphous silicon, and single-crystalline silicon.

[0088] In some embodiments, as Figure 6 shown, the optical chip structure further includes a second defect layer 106 on the surface of the support substrate 101 away from the first defect layer 105. By adding the second defect layer 106, the microwave loss of the device is further reduced.

[0089] In some embodiments, the first defect layer 105 and the second defect layer 106 have the same thickness.

[0090] Specifically, the thickness of the second defect layer 106 is 300 to 10,000 μm. The thickness of the second defect layer 106 can be any point value within the above range, and no enumeration is made here.

[0091] In some embodiments, the first defect layer 105 and the second defect layer 106 are made of the same material.

[0092] Specifically, the material of the second defect layer 106 includes at least one of polysilicon, ion-implanted polysilicon, amorphous silicon, and single-crystalline silicon. By defining that the first defect layer 105 and the second defect layer 106 have the same material and thickness, a more uniform electric field distribution can be provided, which helps to improve the efficiency of the electro-optic modulator, and can also provide a smoother light transmission path, thereby reducing the insertion loss.

[0093] As Figure 1-2 shown, the optical chip structure of the present application includes a photoelectric thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101. The photoelectric thin film layer 103 is provided with at least one first region 1031 and a second region 1032. A ridge waveguide structure is formed in the first region 1031, and the resistance of the first region 1031 is higher than that of the second region 1032.

[0094] In some embodiments, the material of the photoelectric thin film layer 103 includes at least one of lithium niobate, lithium tantalate, and barium titanate. The above materials have excellent photoelectric effects and are suitable for preparing electro-optic modulators.

[0095] In some embodiments, the area of the first region 1031 accounts for 1% - 20% of the total area of the optoelectronic thin film layer 103. With this setting, it is possible to ensure that the chip structure has good light transmittance and avoid the problem that a smaller area of the first region 1031 may lead to a decrease in the light transmittance of the chip structure and an increase in the optical loss of the crystal.

[0096] In some embodiments, the resistivity range of the first region 1031 is 3×10 10 ~3×10 18 Ω·cm. By limiting the resistivity of the first region 1031, it is possible to effectively reduce the energy loss of the optical signal during transmission, thereby improving the transmission efficiency of the optical signal.

[0097] In some embodiments, the area of the second region 1032 accounts for 80% - 99% of the total area of the optoelectronic thin film layer 103. With this setting, it is possible to ensure that the chip structure can conduct the charges generated by the photorefractive effect or the photovoltaic effect of the optoelectronic thin film layer 103 in a timely manner, and avoid the problem that the bias point of the electro-optic modulator changes with time due to the generation of a non-uniform electric field inside and at the interface of the single crystal thin film.

[0098] In some embodiments, the resistivity range of the second region 1032 is 1×10 9 ~3×10 11 Ω·cm. By setting an appropriate resistivity, it is possible to avoid the problem that the chip structure is difficult to conduct the charges generated on the optoelectronic thin film layer 103 due to too high a resistivity, resulting in the generation of a non-uniform electric field inside and at the interface of the single crystal thin film, and further resulting in the problem that the bias point of the electro-optic modulator changes with time.

[0099] In some embodiments, the thickness range of the second region 1032 is 50 - 600 nm. The thickness of the second region 1032 can be any point value within the above range and will not be enumerated here. When the thickness of the second region 1032 is smaller, its resistivity will increase correspondingly, but the light transmittance will also increase. In order to ensure that the second region 1032 has a low resistance and at the same time ensure a certain light transmittance, the above thickness range is thus limited.

[0100] In some embodiments, the oxygen component content of the first region 1031 is higher than that of the second region 1032. The higher the oxygen component content of the optoelectronic thin film layer 103, the higher its resistivity and the higher its transmittance. Therefore, the oxygen component content of the first region 1031 is set to be higher than that of the second region 1032.

[0101] In some embodiments, such as Figure 2As shown, the ridge waveguide structure includes a substrate region 1033 and a ridge waveguide region 1034. The ridge waveguide region 1034 protrudes from one surface of the substrate region 1033, and the protruding height of the ridge waveguide region 1034 from the one surface of the substrate region 1033 ranges from 50 to 600 nm. The protruding height of the ridge waveguide region 1034 can be any point value within the above range, and no enumeration is made here. The waveguide structure is used to guide and define the region of light propagation. By defining the above protruding height, the propagation path of the optical signal is optimized, the propagation loss of light is reduced, and the coupling efficiency of light is improved.

[0102] In some embodiments, the width of the ridge waveguide region 1034 ranges from 0.5 to 5 μm. The width of the ridge waveguide region 1034 can be any point value within the above range, and no enumeration is made here. By defining the above width, the problem of increased optical loss caused by too narrow a width of the waveguide region is avoided, and at the same time, the problem of possible reduction in the modulation efficiency of the electro-optic modulator when the width of the waveguide region is too wide is also avoided.

[0103] In some embodiments, the thickness range of the substrate region 1033 is from 50 to 600 nm. The thickness of the substrate region 1033 can be any point value within the above range, and no enumeration is made here. By defining the thickness range of the substrate region 1033, the light transmittance of the first region 1031 can be improved, and at the same time, the optical loss of the first region 1031 can be reduced.

[0104] Exemplarily, Figure 8 is a top view of the optical chip structure of the embodiment of the present application. As Figure 8 shown, the first region 1031 and the second region 1032 of the optoelectronic thin film layer 103 are adjacent to each other at intervals, and each first region 1031 and each second region 1032 are arranged alternately.

[0105] In some embodiments, as Figure 4 and Figure 7 shown, the structure further includes an electrode structure 107 on the surface of the second region 1032 away from the first isolation layer 102. Forming the electrode structure 107 in the second region 1032 can not only realize the detection and processing of optical signals, but also effectively control the propagation and modulation of optical signals, improving the performance and efficiency of the modulator.

[0106] Exemplarily, Figure 9 is a top view of the optical chip structure of the embodiment of the present application. As Figure 9 shown, electrode structures 107 are provided on each second region 1032 of the optoelectronic thin film layer 103, and the electrode structures 107 are arranged at intervals.

[0107] On the other hand, the following introduces a preparation method of an optical chip structure provided by an embodiment of the present application. This preparation method is used to prepare the optical chip structure in the above-mentioned embodiment, and this preparation method includes:

[0108] S1: Provide a support substrate 101;

[0109] In some embodiments, the support substrate 101 includes at least one of silicon, silicon carbide, sapphire, and quartz. Silicon, sapphire, and quartz all have high optical transmittance, which can ensure the effective transmission of optical signals and reduce optical loss, while silicon carbide has a large high breakdown electric field strength and can work under high voltage conditions without electrical breakdown, and can be applied to high-voltage devices.

[0110] Specifically, the quartz is fused quartz or single crystal quartz.

[0111] In some embodiments, the thickness range of the support substrate 101 is 300 - 1000 μm. The thickness of the support substrate 101 can be any point value within the above range, and no enumeration is made here. Through this setting, the mechanical strength of the chip structure is ensured, and at the same time, the problem of increased optical loss during light propagation caused by a large thickness of the support substrate 101 is avoided.

[0112] In some embodiments, the curvature range of the support substrate 101 is -30 - 30 μm. The curvature of the support substrate 101 can be any point value within the above range, and no enumeration is made here. By limiting the curvature range of the support substrate 101, the processability of the chip structure is ensured.

[0113] S2: Form a first isolation layer 102 on one side surface of the support substrate 101; by adding the isolation layer, the interaction between the support substrate 101 and the optoelectronic thin film layer 103 is avoided.

[0114] Specifically, the first isolation layer 102 is formed on one side surface of the support substrate 101 by physical vapor deposition or chemical vapor deposition.

[0115] In some embodiments, the material of the first isolation layer 102 includes at least one of silicon dioxide, silicon nitride, and aluminum oxide. The above materials have good insulation and low dielectric constant, which can effectively prevent the mutual interference between different layers and reduce the loss of optical signals at the same time.

[0116] In some embodiments, the thickness range of the first isolation layer 102 is 1 - 50 μm. The thickness of the first isolation layer 102 can be any point value within the above range, and no enumeration is made here. By setting the above thickness range, not only can the microwave loss of the chip structure be reduced, but also the interaction between different layers can be avoided.

[0117] In some embodiments, before forming the optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a patterning process, the preparation method further includes: forming a second isolation layer 104 on the side of the support substrate 101 away from the first isolation layer 102. By forming the second isolation layer 104, the transmission and loss of optical signals can be further reduced.

[0118] Specifically, the second isolation layer 104 can be formed on the side of the support substrate away from the first isolation layer 102 by physical vapor deposition or chemical vapor deposition.

[0119] In some embodiments, the first isolation layer 102 and the second isolation layer 104 have the same thickness.

[0120] In some embodiments, the first isolation layer 102 and the second isolation layer 104 are made of the same material. The same material and thickness of the first isolation layer 102 and the second isolation layer 104 ensure the performance and stability of the chip structure.

[0121] Specifically, the material of the second isolation layer 104 includes at least one of silicon dioxide, silicon nitride, and aluminum oxide.

[0122] Specifically, the thickness range of the second isolation layer 104 is 1 - 50 μm. The thickness of the second isolation layer 104 can be any point value within the above range, and will not be enumerated here.

[0123] In some embodiments, as Figure 10 shown, before forming the optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a patterning process, the preparation method further includes: forming a first defect layer 105 between the first isolation layer 102 and the support substrate 101. In this embodiment, the obtained structure is like the optical chip structure a in Figure 10 . When the support substrate 101 is irradiated by incident light, electrons may be generated. The first defect layer 105 can absorb the electrons generated by the support substrate 101 to reduce the microwave loss of the device.

[0124] Specifically, the first defect layer 105 is formed between the first isolation layer 102 and the support substrate 101 by vapor deposition or ion implantation. The present application does not specifically limit the formation method of the first defect layer 105, and only needs to form the first defect layer 105 between the first isolation layer 102 and the support substrate 101.

[0125] Specifically, vapor deposition can include physical vapor deposition or chemical vapor deposition.

[0126] In some embodiments, the thickness of the first defect layer 105 ranges from 300 to 10000 μm. The thickness of the first defect layer 105 can be any point value within the above range, and no enumeration is made here. The thickness of the defect layer affects the propagation path and speed of light, thereby affecting the light propagation efficiency and the signal transmission quality. Moreover, an overly thick defect layer may increase the light scattering, resulting in the attenuation and distortion of the optical signal.

[0127] In some embodiments, the material of the first defect layer 105 includes at least one of polysilicon, polysilicon after ion implantation, amorphous silicon, and single crystal silicon.

[0128] In some embodiments, before forming the optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a patterning process, the method further includes: forming a second defect layer 106 on the surface of the support substrate 101 away from the first defect layer 105. By adding the second defect layer 106, the microwave loss of the device is further reduced.

[0129] Specifically, the second defect layer 106 is formed on the surface of the support substrate 101 away from the first defect layer 105 by means of vapor deposition or ion implantation. The present application does not specifically limit the formation method of the second defect layer 106, and it is only necessary to form the second defect layer 106 on the surface of the support substrate 101 away from the first defect layer 105.

[0130] Specifically, the vapor deposition can be physical vapor deposition or chemical vapor deposition.

[0131] In some embodiments, the first defect layer 105 and the second defect layer 106 have the same thickness.

[0132] Specifically, the thickness of the second defect layer 106 is from 300 to 10000 μm. The thickness of the second defect layer 106 can be any point value within the above range, and no enumeration is made here.

[0133] In some embodiments, the first defect layer 105 and the second defect layer 106 are made of the same material.

[0134] Specifically, the material of the second defect layer 106 includes at least one of polysilicon, polysilicon after ion implantation, amorphous silicon, and single crystal silicon.

[0135] S3: Form an optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a graphic process. The optoelectronic thin film layer 103 is provided with at least one first region 1031 and a second region 1032. A ridge waveguide structure is formed in the first region 1031, and the resistance of the first region 1031 is higher than that of the second region 1032. For the optical chip structure prepared by the above method, the low resistance of the second region of the optical chip structure can conduct the charges generated by the photorefractive effect or the photovoltaic effect of the optoelectronic thin film layer in time, avoiding the problem that the bias point of the electro-optic modulator changes with time due to the generation of a non-uniform electric field in the single crystal thin film and at the interface of the single crystal thin film. At the same time, the high resistance of the first region ensures the light transmittance of the thin film layer, reducing the loss of the optical signal of the structure. Moreover, a ridge waveguide structure is formed in the first region, which can not only effectively guide and confine the propagation of the optical signal, but also further reduce the loss of the optical signal.

[0136] In some embodiments, the material of the optoelectronic thin film layer 103 includes at least one of lithium niobate, lithium tantalate, and barium titanate. The above materials have excellent optoelectronic effects and are suitable for preparing electro-optic modulators.

[0137] In some embodiments, as Figure 10 shown, forming the optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a graphic process includes:

[0138] Form a preset optoelectronic thin film layer 113 on the surface of the first isolation layer 102 away from the support substrate 101. The preset optoelectronic thin film layer 113 includes at least one first initial region 1131 and a second initial region 1132, and the resistance of the first initial region 1131 is higher than that of the second initial region 1132;

[0139] Perform a graphic etching process on the preset optoelectronic thin film layer 113 to form a ridge waveguide structure in the first initial region 1131 to obtain the first region 1031, and thin the second initial region 1132 to obtain the second region 1032. A reduction process is used to form the first initial region 1131 and the second initial region 1132 on the optoelectronic thin film layer 103. Among them, the resistance of the first initial region 1131 is higher than that of the second initial region 1132. The second initial region 1132 can conduct the charges generated on the thin film layer in time. At the same time, the first initial region 1131 maintains a certain light transmittance, reducing the light loss. After performing a graphic etching process on the preset optoelectronic thin film layer 113, a ridge waveguide structure is formed on the first initial region 1131, effectively guiding the transmission of the optical signal, and thinning the second initial region 1132, thereby improving the light transmittance of the second initial region 1132 and reducing the light loss.

[0140] In some embodiments, the area of the first region 1031 accounts for 1%-20% of the total area of the optoelectronic thin film layer 103. With this setting, it is possible to ensure that the chip structure has good light transmittance and avoid the problem that a smaller area of the first region 1031 may lead to a decrease in the light transmittance of the chip structure and an increase in the optical loss of the crystal.

[0141] In some embodiments, the resistivity range of the first region 1031 is 3×10 10 ~3×10 18 Ω·cm. By limiting the resistivity of the first region 1031, the energy loss of the optical signal during transmission can be effectively reduced, thereby improving the transmission efficiency of the optical signal.

[0142] In some embodiments, the area of the second region 1032 accounts for 80%-99% of the total area of the optoelectronic thin film layer 103. With this setting, it is possible to ensure that the chip structure can conduct the charges generated by the photorefractive effect or the photovoltaic effect of the optoelectronic thin film layer 103 in a timely manner, and avoid the problem that the bias point of the electro-optic modulator changes with time due to the generation of a non-uniform electric field inside and at the interface of the single crystal thin film.

[0143] In some embodiments, the resistivity range of the second region 1032 is 1×10 9 ~3×10 11 Ω·cm. By setting an appropriate resistivity, it is possible to avoid the problem that the chip structure is difficult to conduct the charges generated on the optoelectronic thin film layer 103 due to too high a resistivity, resulting in the generation of a non-uniform electric field inside and at the interface of the single crystal thin film, and further resulting in the problem that the bias point of the electro-optic modulator changes with time.

[0144] In some embodiments, the thickness range of the second region 1032 is 50-600 nm. The thickness of the second region 1032 can be any point value within the above range and will not be enumerated here. When the thickness of the second region 1032 is smaller, its resistivity will increase correspondingly, but the light transmittance will also increase. In order to ensure that the second region 1032 has a low resistance and at the same time ensure a certain light transmittance, the above thickness range is thus limited.

[0145] In some embodiments, the oxygen component content of the first region 1031 is higher than that of the second region 1032. The higher the oxygen component content of the optoelectronic thin film layer 103, the higher its resistivity and the higher its transmittance. Therefore, the oxygen component content of the first region 1031 is set to be higher than that of the second region 1032.

[0146] In some embodiments, the ridge waveguide structure includes a substrate region 1033 and a ridge waveguide region 1034. The ridge waveguide region 1034 protrudes from one surface of the substrate region 1033, and the protruding height of the ridge waveguide region 1034 from the one surface of the substrate region 1033 ranges from 50 to 600 nm. The protruding height of the ridge waveguide region 1034 can be any point value within the above range, and no enumeration is made here.

[0147] In some embodiments, the width of the ridge waveguide region 1034 ranges from 0.5 to 5 μm. The width of the ridge waveguide region 1034 can be any point value within the above range, and no enumeration is made here. By limiting the above width, the problem of increased optical loss caused by too narrow a width of the waveguide region is avoided, and at the same time, the problem that the modulation efficiency of the electro-optic modulator may be reduced when the width of the waveguide region is too wide is also avoided.

[0148] In some embodiments, the thickness range of the substrate region 1033 is from 50 to 600 nm. The thickness of the substrate region 1033 can be any point value within the above range, and no enumeration is made here. By limiting the thickness range of the substrate region 1033, the light transmittance of the first region 1031 can be improved while reducing the optical loss of the first region 1031.

[0149] In some embodiments, as Figure 10 shown, a preset optoelectronic thin film layer 113 is formed on the surface of the first isolation layer 102 away from the support substrate 101, including:

[0150] An initial optoelectronic thin film layer 108 is formed on the surface of the first isolation layer 102 away from the support substrate 101;

[0151] A patterned barrier layer 112 is formed on the initial optoelectronic thin film layer 108 to obtain an optical chip structure f. The barrier layer 109 shields the thin film layer region corresponding to the first region 1031 in the initial optoelectronic thin film layer 108;

[0152] The initial optoelectronic thin film layer 108 with the patterned barrier layer 112 is subjected to a reduction process to restore the thin film layer region exposed by the barrier layer 109, obtaining an optical chip structure g, and the barrier layer 109 is removed to form a preset optoelectronic thin film layer 113, obtaining an optical chip structure h. By forming a patterned barrier layer 112 on the initial optoelectronic thin film layer 108, the optoelectronic thin film layer with the patterned barrier layer can be subjected to a reduction process at a relatively high temperature, and then the thin film layer region exposed by the barrier layer 109 can be restored. The thin film layer region exposed by the barrier layer 109 is the second initial region 1132, and at the same time, it is ensured that the thin film layer region not shielded by the barrier layer 109 is not restored. The thin film layer region not shielded by the barrier layer 109 is the first initial region 1131.

[0153] Specifically, the reduction treatment can be carried out by hydrogen annealing reduction or carbon annealing reduction. The annealing temperature used in the hydrogen annealing reduction process is 300 - 1000 °C, and the annealing time is 3 - 50 h. The annealing temperature used in the carbon annealing reduction process is 300 - 1000 °C, and the annealing time is 3 - 50 h.

[0154] Specifically, the blocking layer 109 can be removed by wet etching.

[0155] In some embodiments, as Figure 10 shown, a patterned blocking layer 112 is formed on the initial optoelectronic thin film layer 108, including:

[0156] A blocking layer 109 is formed on the initial optoelectronic thin film layer 108 to obtain an optical chip structure b;

[0157] A patterned initial photoresist layer 111 is formed on the initial optoelectronic thin film layer 108 with the blocking layer 109 to obtain an optical chip structure d;

[0158] Using the patterned initial photoresist layer 111 as a mask, the initial optoelectronic thin film layer 108 with the blocking layer 109 is etched to transfer the pattern of the initial photoresist layer 111 to the blocking layer 109, obtaining an optical chip structure e, and the initial photoresist layer 111 is removed to form a patterned blocking layer 112 on the initial optoelectronic thin film layer 108, obtaining an optical chip structure f. The reason for performing reduction after depositing the blocking layer 109 on the initial optoelectronic thin film layer 108 in the present invention is that photoresist is difficult to withstand high temperatures and is not suitable for the subsequent reduction process. Specifically, the blocking layer 109 can be etched by dry etching or wet etching.

[0159] Specifically, the blocking layer 109 can be formed on the initial optoelectronic thin film layer 108 by vapor deposition.

[0160] Specifically, the material of the blocking layer 109 can be materials such as SiO2, SiN, polysilicon, diamond-like carbon film, etc.

[0161] In some embodiments, a patterned initial photoresist layer 110 is formed on the initial optoelectronic thin film layer 108 with the blocking layer 109, including: coating a photoresist on the initial optoelectronic thin film layer 108 with the blocking layer 109 and performing a heat treatment to form an initial photoresist layer 110 on the initial optoelectronic thin film layer 108, obtaining an optical chip structure c, and exposing and developing the initial photoresist layer 110 to form a patterned initial photoresist layer 111 on the initial optoelectronic thin film layer 108 with the blocking layer 109, obtaining an optical chip structure d.

[0162] In some embodiments, as Figure 10As shown, performing a patterning etching process on the preset optoelectronic thin film layer 113 includes:

[0163] Forming a patterned photoresist layer 115 on the preset optoelectronic thin film layer 113 to obtain an optical chip structure j;

[0164] Using the patterned photoresist layer 115 as a mask, etching the preset optoelectronic thin film layer 113 to form a ridge waveguide structure in the first initial region 1131 to obtain a first region 1031, thinning the second initial region 1132 to obtain a second region 1032, obtaining an optical chip structure k, removing the patterned photoresist layer 115 to obtain an optoelectronic thin film layer 103, and obtaining an optical chip structure l. Specifically, the preset optoelectronic thin film layer 113 can be etched by dry etching or wet etching; preferably, the preset optoelectronic thin film layer 113 is etched by dry etching.

[0165] Specifically, the patterned photoresist layer 115 can be removed by dry etching or wet etching. Preferably, the patterned photoresist layer 115 is removed by wet etching.

[0166] In some embodiments, forming a patterned photoresist layer 115 on the preset optoelectronic thin film layer 113 includes: coating a photoresist on the preset optoelectronic thin film layer 113 and performing a heating treatment to form a photoresist layer 114 on the preset optoelectronic thin film layer 113 to obtain an optical chip structure i, exposing and developing the photoresist layer 114 to form a patterned photoresist layer 115 on the preset optoelectronic thin film layer 113 to obtain an optical chip structure j.

[0167] In some embodiments, after forming the optoelectronic thin film layer 103 on the surface of the first isolation layer 102 away from the support substrate 101 based on a patterning process, the preparation method further includes: forming an electrode structure 107 on the surface of the second region 1032 away from the first isolation layer 102.

[0168] The above description has fully disclosed the specific embodiments of the present application. It should be noted that any changes made by those skilled in the art to the specific embodiments of the present application do not depart from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the foregoing specific embodiments.

Claims

1. An optical chip structure, characterized in that, Comprising: A support substrate; A first isolation layer located on one surface of the support substrate; An optoelectronic thin film layer located on the surface of the first isolation layer away from the support substrate. The optoelectronic thin film layer is provided with at least one first region and a second region. A ridge waveguide structure is formed in the first region, and the resistance of the first region is higher than that of the second region.

2. The optical chip structure according to claim 1, wherein, The ridge waveguide structure includes a base region and a ridge waveguide region. The ridge waveguide region protrudes from one surface of the base region. The base region and the ridge waveguide region satisfy at least one of the following characteristics: The protruding height of the ridge waveguide region protruding from one surface of the base region ranges from 50 to 600 nm; The width of the ridge waveguide region ranges from 0.5 to 5 μm; The thickness range of the base region is 50 to 600 nm.

3. The optical chip structure according to claim 1, characterized in that The first region and the second region satisfy at least one of the following characteristics: The area of the first region accounts for 1% - 20% of the total area of the optoelectronic thin film layer; The area of the second region accounts for 80% - 99% of the total area of the optoelectronic thin film layer; The resistivity range of the first region is 3×10 10 ~3×10 18 Ω·cm; The resistivity range of the second region is 1×10 9 ~3×10 11 Ω·cm; The content of oxygen component in the first region is higher than that in the second region.

4. The optical chip structure according to claim 1, characterized in that, The optical chip structure further includes a second isolation layer located on the side of the support substrate away from the first isolation layer.

5. The optical chip structure according to claim 4, wherein, The first isolation layer and the second isolation layer satisfy at least one of the following characteristics: The first isolation layer and the second isolation layer have the same thickness; The first isolation layer and the second isolation layer are made of the same material.

6. The optical chip structure according to claim 1, wherein The optical chip structure further includes a first defect layer located between the first isolation layer and the support substrate.

7. The optical chip structure according to claim 6, characterized in that, The optical chip structure further includes a second defect layer located on the surface of the support substrate away from the first defect layer.

8. The optical chip structure according to claim 7, characterized in that, The structure satisfies at least one of the following characteristics: The thickness range of the first defect layer is 300 to 10000 μm; The material of the first defect layer includes at least one of polysilicon, ion-implanted polysilicon, amorphous silicon, and single-crystalline silicon; The first defect layer and the second defect layer have the same thickness; The first defect layer and the second defect layer are made of the same material.

9. The optical chip structure according to any one of claims 1-8, characterized in that, The structure satisfies at least one of the following characteristics: The thickness range of the first isolation layer is 1 to 50 μm; The thickness range of the second region is 50 to 600 nm; The thickness range of the support substrate is 300 to 1000 μm; The curvature range of the support substrate is -30 to 30 μm.

10. The optical chip structure according to any one of claims 1-8, characterized in that, The structure satisfies at least one of the following characteristics: The material of the first isolation layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide; The material of the optoelectronic thin film layer includes at least one of lithium niobate, lithium tantalate, and barium titanate; The support substrate includes at least one of silicon, silicon carbide, sapphire, and quartz.

11. The optical chip structure according to any one of claims 1-8, characterized in that, The structure further includes an electrode structure located on the surface of the second region away from the first isolation layer.

12. A method for preparing an optical chip structure, characterized in that, The preparation method includes: Providing a support substrate; Forming a first isolation layer on one surface of the support substrate; Forming an optoelectronic thin film layer on the surface of the first isolation layer away from the support substrate based on a patterning process; The optoelectronic thin film layer is provided with at least one first region and a second region, a ridge waveguide structure is formed in the first region, and the resistance of the first region is higher than that of the second region.

13. The preparation method according to claim 12, characterized in that, Forming the optoelectronic thin film layer on the surface of the first isolation layer away from the support substrate based on a patterning process, includes: A preset optoelectronic thin film layer is formed on the surface of the first isolation layer away from the support substrate, the preset optoelectronic thin film layer includes at least one first initial region and a second initial region, and the resistance of the first initial region is higher than that of the second initial region; Performing a patterning etching process on the preset optoelectronic thin film layer to form a ridge waveguide structure in the first initial region to obtain the first region, and thinning the second initial region to obtain the second region.

14. The preparation method according to claim 13, wherein Forming a preset optoelectronic thin film layer on the surface of the first isolation layer away from the support substrate, includes: Forming an initial optoelectronic thin film layer on the surface of the first isolation layer away from the support substrate; Forming a patterned barrier layer on the initial optoelectronic thin film layer, the barrier layer covering the thin film layer region corresponding to the first region in the initial optoelectronic thin film layer; Performing a reduction process on the initial optoelectronic thin film layer with the patterned barrier layer to reduce the thin film layer region exposed by the barrier layer, and removing the barrier layer to form the preset optoelectronic thin film layer.

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