Liquid crystal display device and driving method thereof

Abstract

The invention provides a liquid crystal display device and a driving method thereof. A liquid crystal display panel of the liquid crystal display device comprises a plurality of pixels, a plurality of grid signal lines, a plurality of data signal lines, a plurality of control signal lines and at least one shared voltage line. One pixel comprises a pixel electrode, a first transistor and a second transistor, a grid electrode of the first transistor is electrically connected with a grid signal line, a source electrode is electrically connected with a data signal line, a drain electrode is electrically connected with the pixel electrode, a grid electrode of the second transistor is electrically connected with a control signal line, a source electrode is electrically connected with the pixel electrode, and a drain electrode is electrically connected with a shared voltage line; the first transistor and the second transistor are disposed on one side of the pixel electrode. The driving method comprises the step of adjusting the on-off state of the second transistor by controlling a signal of the control signal line in a driving period of a frame of picture, so that the pixel electrode has different potentials. According to the invention, the multi-domain display effect is realized, the pixel aperture opening ratio is improved, and meanwhile, a good visual angle effect is kept.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a liquid crystal display device and a driving method thereof. Background Art

[0002] In the field of liquid crystal display technologies, liquid crystal display panels with vertical alignment (VA) mode are widely used due to their high contrast ratio and good black display effect. However, at different viewing angles, the birefringence difference of liquid crystal molecules in the liquid crystal display panel with vertical alignment mode is relatively large, resulting in relatively serious color shift and affecting the display effect.

[0003] To improve this problem, the prior art usually designs the pixels of the liquid crystal display panel into a multi-domain structure. In addition, the pixels are further divided into a main pixel part and a sub-pixel part with different rotation angles of liquid crystal molecules, that is, both the main pixel part and the sub-pixel part include 4 domains, so as to achieve the display effect of 8 domains and effectively improve the color shift problem.

[0004] In the prior art, the way to achieve the display effect of 8 domains is to control the pixels through three thin film transistors. Among them, the first thin film transistor controls the main pixel part. The gate of the first thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode of the main pixel part. The sub-pixel part is jointly controlled by the other two thin film transistors (the second thin film transistor and the third thin film transistor). The gate of the second thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode of the sub-pixel part. The gate of the third thin film transistor is electrically connected to the gate line, the source is electrically connected to the pixel electrode of the sub-pixel part, and the drain is electrically connected to the shared voltage line, so as to apply different potentials to the main pixel part and the sub-pixel part, and separately control the bias voltage of the sub-pixel part to achieve low color shift and afterimage optimization.

[0005] However, the above three thin film transistors and the gate line separate the main pixel part and the sub-pixel part (the above three thin film transistors and the gate line are arranged between the main pixel part and the sub-pixel part), which results in a lower aperture ratio of the pixels. In addition, since the main pixel part and the sub-pixel part are separated spatially, although the data refresh rate is relatively low, the pixel aperture ratio is low and the viewing angle is relatively fixed, making it difficult to meet the requirements of high transmittance and adjustable viewing angle.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0007] The purpose of the embodiments of this application is to provide a liquid crystal display device and a driving method thereof, aiming to improve the pixel aperture ratio while maintaining a good viewing angle effect.

[0008] An embodiment of the present application provides a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel, and the liquid crystal display panel includes a plurality of pixels, a plurality of gate signal lines, a plurality of data signal lines, a plurality of control signal lines, and at least one shared voltage line; each of the pixels includes: a pixel electrode; a first transistor, a gate of the first transistor is electrically connected to the gate signal line, a source of the first transistor is electrically connected to the data signal line, and a drain of the first transistor is electrically connected to the pixel electrode; and a second transistor, a gate of the second transistor is electrically connected to the control signal line, a source of the second transistor is electrically connected to the pixel electrode, and a drain of the second transistor is electrically connected to the shared voltage line; wherein, the first transistor and the second transistor are disposed on one side of the pixel electrode.

[0009] In the above liquid crystal display device, a driving period of one frame of a picture includes a first stage and a second stage; in the first stage, a first gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, a signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a first potential; in the second stage, a second gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, a signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the data signal line is used to charge the pixel electrode to a second potential; wherein, the second potential is higher than the first potential.

[0010] In the above liquid crystal display device, the driving period of one frame of the picture includes a third stage, a fourth stage, and a fifth stage; in the third stage, the third gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a second gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a third potential; in the fourth stage, the fourth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a second gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a third potential; in the fifth stage, the fifth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a first gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the data signal line is used to charge the pixel electrode to a fourth potential; wherein, the fourth potential is higher than the third potential.

[0011] In the above liquid crystal display device, within the third stage, the fourth stage, and the fifth stage, the data signal line charges the pixel electrode in sequence according to the order of the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage, and the ratio of the sum of the durations of the third stage and the fourth stage to the duration of the fifth stage is 2:1.

[0012] In the above liquid crystal display device, the driving period of one frame of the picture includes a sixth stage, a seventh stage, and an eighth stage; within the sixth stage, the sixth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, the shared voltage signal transmitted by the shared voltage line is a low-level signal, and the potential of the pixel electrode is the fifth potential; within the seventh stage, the seventh gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, the shared voltage signal transmitted by the shared voltage line is a high-level signal, and the potential of the pixel electrode is the sixth potential; within the eighth stage, the eighth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the potential of the pixel electrode is the seventh potential.

[0013] In the above liquid crystal display device, the shared voltage line is electrically connected to the common electrode line of the liquid crystal display panel.

[0014] In the above liquid crystal display device, the control signal line is electrically connected to the common electrode line of the liquid crystal display panel.

[0015] An embodiment of the present application further provides a driving method for a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel, the liquid crystal display panel includes a plurality of pixels, a plurality of gate signal lines, a plurality of data signal lines, a plurality of control signal lines, and at least one shared voltage line. Each pixel includes a pixel electrode, a first transistor, and a second transistor. The gate of the first transistor is electrically connected to the gate signal line, the source is electrically connected to the data signal line, and the drain is electrically connected to the pixel electrode. The gate of the second transistor is electrically connected to the control signal line, the source is electrically connected to the pixel electrode, and the drain is electrically connected to the shared voltage line. The driving method includes: within the driving period of one frame of the picture, by controlling the signal of the control signal line, adjusting the switching state of the second transistor, so that the pixel electrode has different potentials.

[0016] In the above driving method, the driving period of one frame of the picture includes a first stage and a second stage; in the first stage, the gate signal line provides a first gate driving signal with a high level to the first transistor to turn on the first transistor, the data signal line writes a data signal to the pixel electrode, the control signal line provides a high-level signal to the second transistor to turn on the second transistor, and the shared voltage line pulls down the potential of the pixel electrode to a first potential; in the second stage, the gate signal line provides a second gate driving signal with a high level to the first transistor to turn on the first transistor, the data signal line writes a data signal to the pixel electrode, the control signal line provides a low-level signal to the second transistor to turn off the second transistor, and the data signal line charges the pixel electrode to a second potential; wherein, the second potential is higher than the first potential.

[0017] In the above driving method, the driving period of one frame of the picture includes a third stage, a fourth stage and a fifth stage; in the third stage, the gate signal line provides a third gate driving signal with a high level to the first transistor to turn on the first transistor, the data signal line writes a data signal of a second gray-scale voltage to the pixel electrode, the control signal line provides a high-level control signal to the second transistor to turn on the second transistor, and the shared voltage line pulls down the potential of the pixel electrode to a third potential; in the fourth stage, the gate signal line provides a fourth gate driving signal with a high level to the first transistor to turn on the first transistor, the data signal line writes a data signal of a second gray-scale voltage to the pixel electrode, the control signal line provides a high-level control signal to the second transistor to turn on the second transistor, and the shared voltage line pulls down the potential of the pixel electrode to a third potential; in the fifth stage, the gate signal line provides a fifth gate driving signal with a high level to the first transistor to turn on the first transistor, the data signal line writes a data signal of a first gray-scale voltage to the pixel electrode, the control signal line provides a low-level control signal to the second transistor to turn off the second transistor, and the data signal line charges the pixel electrode to a fourth potential; wherein, the fourth potential is higher than the third potential.

[0018] In the above driving method, within the third stage, the fourth stage and the fifth stage, the data signal line charges the pixel electrode in sequence according to the order of the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage, and the ratio of the sum of the durations of the third stage and the fourth stage to the duration of the fifth stage is 2:1.

[0019] In the above driving method, the driving cycle of one frame of the picture includes a sixth stage, a seventh stage, and an eighth stage; in the sixth stage, the gate signal line provides a sixth gate driving signal with a high level to the first transistor, so that the first transistor is turned on, the data signal line writes a data signal to the pixel electrode, the control signal line provides a control signal with a high level to the second transistor, so that the second transistor is turned on, and the shared voltage line provides a shared voltage signal with a low level to the pixel electrode, so that the potential of the pixel electrode is the fifth potential; in the seventh stage, the gate signal line provides a seventh gate driving signal with a high level to the first transistor, so that the first transistor is turned on, the data signal line writes a data signal to the pixel electrode, the control signal line provides a control signal with a high level to the second transistor, so that the second transistor is turned on, and the shared voltage line provides a shared voltage signal with a high level to the pixel electrode, so that the potential of the pixel electrode is the sixth potential; in the eighth stage, the gate signal line provides an eighth gate driving signal with a high level to the first transistor, so that the first transistor is turned on, the data signal line writes a data signal to the pixel electrode, the control signal line provides a control signal with a low level to the second transistor, so that the second transistor is turned off, and the potential of the pixel electrode is the seventh potential.

[0020] The liquid crystal display device and its driving method provided by the present application set a pixel electrode, a first transistor, and a second transistor in each pixel. The gate of the first transistor is electrically connected to the gate signal line, the source is electrically connected to the data signal line, the drain is electrically connected to the pixel electrode, the gate of the second transistor is electrically connected to the control signal line, the source is electrically connected to the pixel electrode, and the drain is electrically connected to the shared voltage line. By arranging the first transistor and the second transistor on one side of the pixel electrode, the technical effect of improving the pixel aperture ratio while maintaining a good viewing angle effect is achieved.

[0021] Specifically, the technical solution of the present application realizes the multi-domain display effect through time division, rather than the spatial division method in the prior art. In the prior art, the pixel is divided into a main pixel part and a sub-pixel part, and three thin film transistors are required for control. These transistors and the gate line are arranged between the main pixel part and the sub-pixel part, occupying a large amount of non-light-transmitting area, resulting in a low pixel aperture ratio. The technical solution of the present application only uses two thin film transistors, and arranges these two transistors on one side of the pixel electrode, without dividing the pixel electrode into two parts, thereby reducing the non-light-transmitting area and increasing the pixel aperture ratio.

[0022] In addition, the technical solution of the present application controls the switching state of the second transistor through a control signal line, so that the pixel electrode has different potentials within the driving period of one frame of the picture, thereby dividing the pixel electrode into a main pixel function and a sub-pixel function in time, and achieving a display effect similar to that of an 8-domain. When the control signal provided by the control signal line makes the second transistor in the on state, the shared voltage line pulls down the potential of the pixel electrode, and the pixel electrode presents the sub-pixel function; when the control signal provided by the control signal line makes the second transistor in the off state, the data signal line charges the pixel electrode to a higher potential, and the pixel electrode presents the main pixel function. This time-division method not only maintains a good viewing angle effect but also improves the pixel aperture ratio.

[0023] The technical solution of the present application can also flexibly adjust the viewing angle and transmittance by adjusting the voltages and timings of the control signal line, the gate signal line, the data signal line, and the shared voltage line. For example, when the control signal provided by the control signal line makes the second transistor in the on state, the liquid crystal display device is in the first display mode corresponding to the viewing angle adjustment; when the control signal provided by the control signal line makes the second transistor in the off state, the liquid crystal display device is in the second display mode corresponding to the transmittance adjustment. This technical solution enables the liquid crystal display device of the present application to switch between a high viewing angle mode and a high transmittance mode according to the requirements of different application scenarios, meeting diverse display needs.

[0024] In summary, the liquid crystal display device and its driving method provided by the present application achieve a multi-domain display effect through time division, reduce the non-light-transmitting area, improve the pixel aperture ratio, maintain a good viewing angle effect, and can flexibly adjust the viewing angle and transmittance. Description of the Drawings

[0025] Figure 1 is a schematic diagram of the layout of pixels and related traces in a conventional liquid crystal display device.

[0026] Figure 2 is Figure 1 a circuit diagram of the pixels and related traces in the liquid crystal display device shown.

[0027] Figure 3 is Figure 1 a schematic diagram of the area ratio of the non-light-transmitting area in the pixels shown.

[0028] Figure 4 is a schematic diagram of the layout of pixels and related traces in the liquid crystal display device provided by the embodiment of the present application.

[0029] Figure 5 is Figure 4 a circuit diagram of the pixels and related traces in the liquid crystal display device shown.

[0030] Figure 6 is Figure 4 The waveform diagram of signals in the pixels and related traces of the first embodiment of the liquid crystal display device shown.

[0031] Figure 7 is Figure 4 The waveform diagram of signals in the pixels and related traces of the second embodiment of the liquid crystal display device shown.

[0032] Figure 8 is Figure 4 The waveform diagram of signals in the pixels and related traces of the third embodiment of the liquid crystal display device shown.

[0033] Figure 9 is Figure 4 The schematic diagram of the area ratio of the non-light-transmitting region in the pixels shown. Detailed implementation manners

[0034] The following will describe the detailed implementation manners of the present application with reference to the accompanying drawings.

[0035] Terms such as "first", "second" and similar words do not represent any order, quantity or importance, but are only used to distinguish different technical features. Terms such as "a plurality of" and similar words mean two or more, unless otherwise clearly defined.

[0036] The embodiments of the present application can be combined with each other.

[0037] The liquid crystal display device provided by the embodiments of the present application includes a liquid crystal display panel, a timing controller, a source driver circuit and a power management chip (the power management chip can be integrated with the timing controller into the same chip).

[0038] The liquid crystal display panel includes a display area and a non-display area. The display area is provided with m×n pixels arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The liquid crystal display panel further includes a plurality of gate lines GL, a plurality of data lines DL and a gate driver circuit. The plurality of gate lines GL extend along a first direction and are arranged along a second direction, and the plurality of data lines DL extend along the second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate driver circuit is arranged in the non-display area and is electrically connected to the plurality of gate lines GL. The source driver circuit is electrically connected to the plurality of data lines DL through a flexible circuit board. The timing controller is electrically connected to the gate driver circuit and the source driver circuit respectively.

[0039] The liquid crystal display panel includes a thin film transistor array substrate, a counter substrate, and a liquid crystal layer disposed between the two substrates. The thin film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes gate lines GL, gates, etc. The second metal layer includes data lines DL, sources, drains, etc. The counter substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0040] Each pixel includes at least one thin film transistor and a pixel electrode. The gate of the thin film transistor is electrically connected to the corresponding gate line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the gate line outputs a high-level scan signal, the thin film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin film transistor; when the gate line outputs a low-level scan signal, the thin film transistor is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0041] The gate driving circuit includes n cascaded gate driving sub-circuits, and each stage of the gate driving sub-circuit is electrically connected to a gate line. Under the control of the timing controller, the gate driving sub-circuits sequentially output scan signals to scan each row of pixels in the display area row by row. The source driving circuit generates and outputs data signals according to the image data under the control of the timing controller. The timing controller is used to receive and process externally input image data and clock signals, transmit the clock signal to the gate driving circuit, and transmit the image data to the source driving circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode of the liquid crystal display panel, providing a gate driving voltage for the gate driving circuit, providing a gamma voltage for the source driving circuit, etc.

[0042] Such as Figure 4 And Figure 5As shown, embodiments of the present application provide a liquid crystal display device, which includes a liquid crystal display panel, and the liquid crystal display panel is a vertically aligned mode liquid crystal display panel. The liquid crystal display panel includes a plurality of pixels, a plurality of gate signal lines GL, a plurality of data signal lines DL, a plurality of control signal lines CL, and at least one shared voltage line SB. Each pixel includes a pixel electrode PE, a first transistor T1, and a second transistor T2. The gate of the first transistor T1 is electrically connected to the gate signal line GL, the source is electrically connected to the data signal line DL, and the drain is electrically connected to the pixel electrode PE. The gate of the second transistor T2 is electrically connected to the control signal line CL, the source is electrically connected to the pixel electrode PE, and the drain is electrically connected to the shared voltage line SB. Among them, the first transistor T1 and the second transistor T2 are disposed on one side of the pixel electrode PE. The gate signal line GL, the first transistor T1, and the second transistor T2 are disposed on the same side of the pixel electrode PE.

[0043] The pixel electrode PE includes two main electrodes (TE5, TE6), and the two main electrodes (TE5, TE6) are perpendicular to each other, dividing the pixel electrode PE into four regions to form a 4-domain structure. The pixel electrode PE is a 4-domain pixel electrode, rather than an 8-domain one. The two transistors and one gate signal line GL no longer divide the pixel electrode PE into two parts (a main pixel part MPE and a sub-pixel part SPE).

[0044] In the embodiments of the present application, since there is only one pixel electrode PE in the pixel, and the pixel electrode PE has only two perpendicular main electrodes (TE5, TE6), and the liquid crystal molecules located at the main electrodes do not transmit light. Therefore, compared with the traditional 8-domain technical solution (both the main pixel part MPE and the sub-pixel part SPE include two perpendicular main electrodes (TE1, TE2, TE3, TE4), as Figure 1 shown), the occupied area of the main electrodes is reduced, thereby reducing the area of the pixel that is not light-transmitting due to the main electrodes, that is, the aperture ratio of the pixel is improved.

[0045] As Figure 6As shown, in the embodiment of the present application, the driving period P of a frame of picture includes a first stage p1 and a second stage p2. In the first stage p1, the first gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal to the pixel electrode PE, the signal transmitted by the control signal line CL is a high-level signal, the second transistor T2 is turned on, and the shared voltage line SB is used to pull down the potential of the pixel electrode PE to the first potential V1. In the second stage p2 after the first stage p1, the second gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal to the pixel electrode PE, the signal transmitted by the control signal line CL is a low-level signal, the second transistor T2 is turned off, and the data signal line DL is used to charge the pixel electrode PE to the second potential V2. Wherein, the second potential V2 is higher than the first potential V1. By first charging the pixel electrode PE to the first potential V1 and then to the second potential V2 in sequence, the charging rate of the pixel electrode PE is increased, thereby improving the brightness of the pixel.

[0046] As Figure 7 shown, in the embodiment of the present application, the driving period P of a frame of picture may also include a third stage p3, a fourth stage p4, and a fifth stage p5. In the third stage p3, the third gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal of the second gray-scale voltage to the pixel electrode PE, the control signal transmitted by the control signal line CL is a high-level signal, the second transistor T2 is turned on, and the shared voltage line SB is used to pull down the potential of the pixel electrode PE to the third potential V3. In the fourth stage p4, the fourth gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal of the second gray-scale voltage to the pixel electrode PE, the control signal transmitted by the control signal line CL is a high-level signal, the second transistor T2 is turned on, and the shared voltage line SB is used to pull down the potential of the pixel electrode PE to the third potential V3. In the fifth stage p5, the fifth gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal of the first gray-scale voltage to the pixel electrode PE, the control signal transmitted by the control signal line CL is a low-level signal, the second transistor T2 is turned off, and the data signal line DL is used to charge the pixel electrode PE to the fourth potential V4. Wherein, the fourth potential V4 is higher than the third potential V3. Within the third stage p3, the fourth stage p4, and the fifth stage p5, the data signal line DL charges the pixel electrode PE in sequence according to the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage, and the ratio of the sum of the durations of the third stage p3 and the fourth stage p4 to the duration of the fifth stage p5 is 2:1.

[0047] As Figure 8 shown, in the embodiments of the present application, the driving period P of one frame of picture may further include a sixth stage p6, a seventh stage p7, and an eighth stage p8. In the sixth stage p6, the sixth gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal to the pixel electrode PE, the control signal transmitted by the control signal line CL is a high-level signal, the second transistor T2 is turned on, the shared voltage signal transmitted by the shared voltage line SB is a low-level signal, and the potential of the pixel electrode PE is the fifth potential V5. In the seventh stage p7, the seventh gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal to the pixel electrode PE, the control signal transmitted by the control signal line CL is a high-level signal, the second transistor T2 is turned on, the shared voltage signal transmitted by the shared voltage line SB is a high-level signal, and the potential of the pixel electrode PE is the sixth potential V6. In the eighth stage p8, the eighth gate driving signal output by the gate signal line GL is a high-level signal, the first transistor T1 is turned on, the data signal line DL is used to write a data signal to the pixel electrode PE, the control signal transmitted by the control signal line CL is a low-level signal, the second transistor T2 is turned off, and the potential of the pixel electrode PE is the seventh potential V7.

[0048] In different stages within the driving period P of one frame of picture, the combinations of the voltage values of the control signal line CL and the shared voltage line SB are different. By adjusting the voltages and timings of the control signal line CL, the gate signal line GL, the data signal line DL, and the shared voltage line SB, the adjustment of the viewing angle and the transmittance is achieved. Within the driving period P of one frame of picture, the data signal line DL outputs data to the pixel electrode PE multiple times, and the multiple data includes data of different gray-scale voltages.

[0049] The shared voltage line SB is electrically connected to the common electrode line ACOM of the liquid crystal display panel. The purpose of electrically connecting the shared voltage line SB to the common electrode line ACOM of the liquid crystal display panel is to simplify the wiring structure. Since both transmit DC signals, the shared voltage line SB can obtain the required potential through electrical connection, thereby adjusting the potential of the pixel electrode PE.

[0050] Similarly, the control signal line CL can also be electrically connected to the common electrode line ACOM. The common electrode line ACOM is usually used to provide a stable reference potential, while the control signal line CL needs to switch between high and low levels to control the on-off state of the second transistor T2. When it is necessary to make the control signal line CL output a high-level signal, a high-level voltage can be provided to the common electrode line ACOM through the control circuit, so that the control signal line CL electrically connected thereto also presents a high-level state; when it is necessary to make the control signal line CL output a low-level signal, the control circuit provides a low-level voltage to the common electrode line ACOM. This electrical connection method can reduce the wiring requirements of the independent control signal line CL, simplify the circuit layout, reduce the non-transmissive area, and thus further improve the aperture ratio of the pixel. In addition, since the common electrode line ACOM usually covers the entire liquid crystal display panel, using it for signal transmission can reduce the impedance and delay of the signal line, and improve the stability and consistency of signal transmission.

[0051] When the control signal provided by the control signal line CL makes the second transistor T2 in the on state, the liquid crystal display device is in the first display mode, and the first display mode is a display mode corresponding to the viewing angle adjustment; when the control signal provided by the control signal line CL makes the second transistor T2 in the off state, the liquid crystal display device is in a second display mode different from the first display mode, and the second display mode is a display mode corresponding to the transmittance adjustment. That is to say, when the control signal provided by the control signal line CL makes the second transistor T2 in the on state, the liquid crystal display device is in the high viewing angle mode; when the control signal provided by the control signal line CL makes the second transistor T2 in the off state, the liquid crystal display device is in the high transmittance mode.

[0052] Through the control of the second transistor T2, the pixel electrode PE is divided into a sub-pixel part SPE and a main pixel part MPE in time, realizing an 8-domain / multi-domain / domain-adjustable viewing angle effect. Specifically, the four regions of the pixel electrode PE form a 4-domain structure, and by controlling the potential change of the pixel electrode PE in time, an 8-domain or multi-domain display effect is realized. The control signal line CL is used to provide a control signal to the gate of the second transistor T2 to control the on-off state of the second transistor T2.

[0053] The pixel in the embodiment of the present application only includes two thin film transistors and a pixel electrode PE. Through the control of the second transistor T2, the function of the pixel electrode PE is divided into a sub-pixel part SPE and a main pixel part MPE in the time dimension. Compared with the prior art (as Figure 2 shown), the embodiment of the present application reduces one thin film transistor (the third transistor T3 in the prior art) and one via, and at the same time reduces the main electrode area of the pixel electrode PE. This is because in the prior art, as Figure 1As shown, the main pixel portion MPE and the sub-pixel portion SPE each include two main electrodes (TE1, TE2, TE3, TE4): one main electrode (TE1, TE3) is perpendicular to the length direction of the gate signal line GL, that is, parallel to the length direction of the opening region of the pixel, and the other main electrode (TE2, TE4) is parallel to the length direction of the gate signal line GL, that is, perpendicular to the length direction of the opening region of the pixel. In the embodiment of the present application, the main pixel portion MPE and the sub-pixel portion SPE are combined into one pixel electrode PE, and only two mutually perpendicular main electrodes (TE5, TE6) are used: one main electrode TE5 perpendicular to the length direction of the gate signal line GL (equivalent to the combination of the main electrodes in the parallel direction in the original two portions), and one main electrode TE6 parallel to the length direction of the gate signal line GL (equivalent to one of the main electrodes in the perpendicular direction in the original two portions). This technical solution eliminates one main electrode parallel to the length direction of the gate signal line GL, thereby increasing the aperture ratio of the pixel (in the embodiment of the present application, as Figure 9 shown, along the direction perpendicular to the length direction of the gate signal line GL, the total length of the pixel is H1, and the length of the non-opening region of the pixel is H3. The aperture ratio of the pixel in the embodiment of the present application = (H1 - H3) / H1. In the prior art, as Figure 3 shown, along the direction perpendicular to the length direction of the gate signal line GL, the total length of the pixel is H1, and the length of the non-opening region of the pixel is H2. The aperture ratio of the pixel in the prior art = (H1 - H2) / H1, where H3 < H2), improving the transmittance of the pixel and the brightness of the liquid crystal display panel.

[0054] In the high transmittance mode, the second transistor T2 is in the cut-off state, and the voltage of the shared voltage line SB will not be written into the pixel electrode PE. In the high viewing angle mode, in the first half frame period (the first stage p1) of the driving period P of one frame of the picture, the control signal line CL is first at a high level, and in the second half frame period (the second stage p2) of the driving period P of one frame of the picture, the control signal line CL is then at a low level. The second transistor T2 is first turned on and then cut off. The potential of the pixel electrode PE in the first half frame period (the first stage p1) is relatively low, playing a role similar to that of the sub-pixel portion SPE, and the voltage of the pixel electrode PE in the second half frame period (the second stage p2) is relatively high, playing a role similar to that of the main pixel portion MPE. The voltages of the pixel electrode PE in the front and back improve the diversity of the liquid crystal state and improve the viewing angle.

[0055] The technical solution of the embodiment of the present application can achieve two modes: high penetration and high viewing angle. In the high viewing angle mode, by adjusting the voltage of the shared voltage line SB, the potential of the pixel electrode PE in the sub-pixel functional state can be adjusted, thereby adjusting the balance between the viewing angle and the transmittance. Generally, when the voltage of the shared voltage line SB is relatively high, the transmittance will increase, but the viewing angle performance will decrease slightly. In addition, by adjusting the time ratio of the pixel electrode PE in the main pixel functional state and the sub-pixel functional state (i.e., the duration of different gray-scale voltages), the balance between the viewing angle and the transmittance can also be adjusted. When the pixel electrode PE is in the main pixel functional state for a longer time, the transmittance will increase; while when the pixel electrode PE is in the sub-pixel functional state for a longer time or the voltage change is more diverse, the viewing angle performance will be better.

[0056] In the embodiment of the present application, the display effects of the pixel electrodes PE with the same area allocated to the main pixel function and the sub-pixel function in time are basically equivalent to the display effects of the main pixel part MPE and the sub-pixel part SPE with different area ratios in the prior art. In the embodiment of the present application, the time ratio of the main pixel function to the sub-pixel function is 1:2, which corresponds to the area ratio of the main pixel part MPE to the sub-pixel part SPE in the prior art.

[0057] The liquid crystal display device further includes a control circuit electrically connected to the control signal line CL, and the control circuit is used to provide a control signal to the control signal line CL. The control circuit can be a circuit independent of the gate driving circuit, the source driving circuit, and the power management chip, or can be integrated in the gate driving circuit or the power management chip. In addition, the liquid crystal display device further includes a source driving circuit electrically connected to the data signal line DL, and the source driving circuit can adjust the output frequency of the data signal line DL so that the data signal line DL outputs data signals with different gray-scale voltages multiple times within the driving period P of one frame of the picture.

[0058] The liquid crystal display device further includes a gate driving circuit electrically connected to the gate signal line GL, and the gate driving circuit is capable of outputting gate driving signals to the gate signal line GL multiple times within the driving period P of one frame of the picture. Specifically, when implementing the driving modes of the first stage p1 and the second stage p2, the gate driving circuit outputs two high-level signals to the gate signal line GL within the driving period P of one frame of the picture, namely the first gate driving signal and the second gate driving signal. When implementing the driving modes of the third stage p3, the fourth stage p4, and the fifth stage p5, the gate driving circuit outputs three high-level signals to the gate signal line GL within the driving period P of one frame of the picture, namely the third gate driving signal, the fourth gate driving signal, and the fifth gate driving signal. When implementing the driving modes of the sixth stage p6, the seventh stage p7, and the eighth stage p8, the gate driving circuit outputs three high-level signals to the gate signal line GL within the driving period P of one frame of the picture, namely the sixth gate driving signal, the seventh gate driving signal, and the eighth gate driving signal.

[0059] The coordinated operation of the gate driving circuit, the source driving circuit, and the control circuit enables the pixel electrode PE to have different potentials at different time points, and the liquid crystal molecules present different states, thereby achieving a multi-domain display effect. The gate driving circuit controls the switching state of the first transistor T1, the source driving circuit controls the gray-scale voltage of the data signal output by the data signal line DL, and the control circuit controls the switching state of the second transistor T2 and the voltage of the shared voltage line SB. The coordinated operation of these three circuits enables the pixel electrode PE to have multiple different potentials within the driving period P of one frame of the picture, thereby achieving a multi-domain display effect.

[0060] The technical solution of the embodiment of the present application realizes a multi-domain display effect by controlling the control signal line CL, has an adjustable viewing angle, and a high aperture ratio. Specifically, by controlling the voltage of the control signal line CL, the switching state of the second transistor T2 can be controlled, thereby controlling whether the shared voltage line SB is electrically connected to the pixel electrode PE. When the second transistor T2 is turned on, the shared voltage line SB is electrically connected to the pixel electrode PE, and the potential of the pixel electrode PE is affected by the shared voltage line SB and has a lower potential, acting like the sub-pixel part SPE; when the second transistor T2 is turned off, the shared voltage line SB is disconnected from the pixel electrode PE, and the potential of the pixel electrode PE is only affected by the data signal line DL and has a higher potential, acting like the main pixel part MPE.

[0061] By controlling the potential change of the pixel electrode PE over time, the embodiments of the present application achieve an 8-domain or multi-domain display effect, improving the viewing angle performance. At the same time, since the embodiments of the present application use only two thin film transistors and one pixel electrode PE, the occupied area of the main electrodes is reduced, the aperture ratio of the pixel is increased, thereby improving the transmittance of the pixel and the brightness of the liquid crystal display panel. In addition, the embodiments of the present application can also flexibly adjust the viewing angle and transmittance by adjusting the voltages and timings of the control signal line CL, gate signal line GL, data signal line DL, and shared voltage line SB to meet the requirements of different application scenarios.

[0062] The embodiments of the present application also provide a driving method for a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel, which includes a plurality of pixels, a plurality of gate signal lines GL, a plurality of data signal lines DL, a plurality of control signal lines CL, and at least one shared voltage line SB. Each pixel includes a pixel electrode PE, a first transistor T1, and a second transistor T2. The gate of the first transistor T1 is electrically connected to the gate signal line GL, the source is electrically connected to the data signal line DL, the drain is electrically connected to the pixel electrode PE, the gate of the second transistor T2 is electrically connected to the control signal line CL, the source is electrically connected to the pixel electrode PE, and the drain is electrically connected to the shared voltage line SB. The driving method includes: within the driving period P of one frame of the picture, by controlling the signal of the control signal line CL, adjusting the switching state of the second transistor T2 to make the pixel electrode PE have different potentials.

[0063] In the embodiments of the present application, the driving period P of one frame of the picture includes a first stage p1 and a second stage p2. In the first stage p1, the gate signal line GL provides a high-level first gate driving signal to the first transistor T1 to turn on the first transistor T1, the data signal line DL writes a data signal to the pixel electrode PE, the control signal line CL provides a high-level signal to the second transistor T2 to turn on the second transistor T2, and the shared voltage line SB pulls down the potential of the pixel electrode PE to the first potential V1. In the second stage p2, the gate signal line GL provides a high-level second gate driving signal to the first transistor T1 to turn on the first transistor T1, the data signal line DL writes a data signal to the pixel electrode PE, the control signal line CL provides a low-level signal to the second transistor T2 to turn off the second transistor T2, and the data signal line DL charges the pixel electrode PE to the second potential V2. Wherein, the second potential V2 is higher than the first potential V1.

[0064] In an embodiment of the present application, the driving period P of a frame of picture may also include a third stage p3, a fourth stage p4, and a fifth stage p5. In the third stage p3, the gate signal line GL provides a third gate driving signal with a high level to the first transistor T1 to turn on the first transistor T1. The data signal line DL writes a data signal of a second gray-scale voltage to the pixel electrode PE. The control signal line CL provides a control signal with a high level to the second transistor T2 to turn on the second transistor T2. The shared voltage line SB pulls down the potential of the pixel electrode PE to a third potential V3. In the fourth stage p4, the gate signal line GL provides a fourth gate driving signal with a high level to the first transistor T1 to turn on the first transistor T1. The data signal line DL writes a data signal of a second gray-scale voltage to the pixel electrode PE. The control signal line CL provides a control signal with a high level to the second transistor T2 to turn on the second transistor T2. The shared voltage line SB pulls down the potential of the pixel electrode PE to a third potential V3. In the fifth stage p5, the gate signal line GL provides a fifth gate driving signal with a high level to the first transistor T1 to turn on the first transistor T1. The data signal line DL writes a data signal of a first gray-scale voltage to the pixel electrode PE. The control signal line CL provides a control signal with a low level to the second transistor T2 to turn off the second transistor T2. The data signal line DL charges the pixel electrode PE to a fourth potential V4. Herein, the fourth potential V4 is higher than the third potential V3. Within the third stage p3, the fourth stage p4, and the fifth stage p5, the data signal line DL charges the pixel electrode PE in sequence according to the order of the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage. The ratio of the sum of the durations of the third stage p3 and the fourth stage p4 to the duration of the fifth stage p5 is 2:1.

[0065] In an embodiment of the present application, the driving period P of a frame of image may further include a sixth stage p6, a seventh stage p7, and an eighth stage p8. In the sixth stage p6, the gate signal line GL provides a sixth gate driving signal with a high level to the first transistor T1, turning on the first transistor T1. The data signal line DL writes a data signal to the pixel electrode PE, and the control signal line CL provides a control signal with a high level to the second transistor T2, turning on the second transistor T2. The shared voltage line SB provides a shared voltage signal with a low level to the pixel electrode PE, making the potential of the pixel electrode PE the fifth potential V5. In the seventh stage p7, the gate signal line GL provides a seventh gate driving signal with a high level to the first transistor T1, turning on the first transistor T1. The data signal line DL writes a data signal to the pixel electrode PE, and the control signal line CL provides a control signal with a high level to the second transistor T2, turning on the second transistor T2. The shared voltage line SB provides a shared voltage signal with a high level to the pixel electrode PE, making the potential of the pixel electrode PE the sixth potential V6. In the eighth stage p8, the gate signal line GL provides an eighth gate driving signal with a high level to the first transistor T1, turning on the first transistor T1. The data signal line DL writes a data signal to the pixel electrode PE, and the control signal line CL provides a control signal with a low level to the second transistor T2, turning off the second transistor T2, and making the potential of the pixel electrode PE the seventh potential V7.

[0066] When the control signal provided by the control signal line CL turns on the second transistor T2, the liquid crystal display device is in a first display mode, and the first display mode is a display mode corresponding to viewing angle adjustment; when the control signal provided by the control signal line CL turns off the second transistor T2, the liquid crystal display device is in a second display mode different from the first display mode, and the second display mode is a display mode corresponding to transmittance adjustment.

[0067] By adjusting the voltages and timings of the control signal line CL, the gate signal line GL, the data signal line DL, and the shared voltage line SB, the adjustment of the viewing angle and transmittance is achieved. During the driving period P of a frame of image, the data signal line DL outputs data multiple times to the pixel electrode PE, and the multiple data includes data with different gray-scale voltages. By first charging the pixel electrode PE to the first potential V1 and then to the second potential V2 in sequence, the charging rate of the pixel electrode PE is increased, thereby increasing the brightness of the pixel. Through the control of the second transistor T2, the pixel electrode PE is divided into a main pixel portion MPE and a sub-pixel portion SPE in time, achieving a multi-domain viewing angle effect.

[0068] The above has introduced the embodiments of the present application in detail. The content of this specification should not be construed as a limitation on the protection scope of the present application.

Claims

1. A liquid crystal display device, characterized in that, The liquid crystal display device includes a liquid crystal display panel, and the liquid crystal display panel includes a plurality of pixels, a plurality of gate signal lines, a plurality of data signal lines, a plurality of control signal lines, and at least one shared voltage line; Each of the pixels includes: a pixel electrode; a first transistor, the gate of the first transistor is electrically connected to the gate signal line, the source is electrically connected to the data signal line, and the drain is electrically connected to the pixel electrode; and a second transistor, the gate of the second transistor is electrically connected to the control signal line, the source is electrically connected to the pixel electrode, and the drain is electrically connected to the shared voltage line; wherein, the first transistor and the second transistor are disposed on one side of the pixel electrode.

2. The liquid crystal display device according to claim 1, wherein, The driving period of one frame of the picture includes a first stage and a second stage; In the first stage, the first gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a first potential; In the second stage, the second gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the data signal line is used to charge the pixel electrode to a second potential; wherein, the second potential is higher than the first potential.

3. The liquid crystal display device according to claim 1, characterized in that, The driving period of one frame of the picture includes a third stage, a fourth stage, and a fifth stage; In the third stage, the third gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a second gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a third potential; In the fourth stage, the fourth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a second gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, and the shared voltage line is used to pull down the potential of the pixel electrode to a third potential; In the fifth stage, the fifth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal of a first gray-scale voltage to the pixel electrode, the control signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the data signal line is used to charge the pixel electrode to a fourth potential; wherein, the fourth potential is higher than the third potential.

4. The liquid crystal display device according to claim 3, characterized in that, In the third stage, the fourth stage, and the fifth stage, the data signal line charges the pixel electrode in the order of the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage, and the ratio of the sum of the durations of the third stage and the fourth stage to the duration of the fifth stage is 2:

1.

5. The liquid crystal display device according to claim 1, characterized in that, The driving period of one frame of the picture includes a sixth stage, a seventh stage, and an eighth stage; In the sixth stage, the sixth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, the shared voltage signal transmitted by the shared voltage line is a low-level signal, and the potential of the pixel electrode is the fifth potential; In the seventh stage, the seventh gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a high-level signal, the second transistor is turned on, the shared voltage signal transmitted by the shared voltage line is a high-level signal, and the potential of the pixel electrode is the sixth potential; In the eighth stage, the eighth gate driving signal output by the gate signal line is a high-level signal, the first transistor is turned on, the data signal line is used to write a data signal to the pixel electrode, the control signal transmitted by the control signal line is a low-level signal, the second transistor is turned off, and the potential of the pixel electrode is the seventh potential.

6. The liquid crystal display device according to claim 1, characterized in that, The shared voltage line is electrically connected to the common electrode line of the liquid crystal display panel.

7. The liquid crystal display device according to claim 1, wherein The control signal line is electrically connected to the common electrode line of the liquid crystal display panel.

8. A driving method of a liquid crystal display device, characterized in that, The liquid crystal display device includes a liquid crystal display panel, the liquid crystal display panel includes a plurality of pixels, a plurality of gate signal lines, a plurality of data signal lines, a plurality of control signal lines, and at least one shared voltage line. Each pixel includes a pixel electrode, a first transistor, and a second transistor. The gate of the first transistor is electrically connected to the gate signal line, the source is electrically connected to the data signal line, the drain is electrically connected to the pixel electrode, the gate of the second transistor is electrically connected to the control signal line, the source is electrically connected to the pixel electrode, and the drain is electrically connected to the shared voltage line; The driving method includes: During the driving period of one frame of the picture, by controlling the signal of the control signal line, the switching state of the second transistor is adjusted to make the pixel electrode have different potentials.

9. The driving method according to claim 8, wherein The driving period of one frame of the picture includes a first stage and a second stage; In the first stage, the gate signal line provides a high-level first gate driving signal to the first transistor to turn on the first transistor, the data signal line writes a data signal to the pixel electrode, the control signal line provides a high-level signal to the second transistor to turn on the second transistor, and the shared voltage line pulls down the potential of the pixel electrode to the first potential; In the second stage, the gate signal line provides a second gate driving signal with a high level to the first transistor, turning on the first transistor. The data signal line writes a data signal to the pixel electrode. The control signal line provides a low-level signal to the second transistor, turning off the second transistor. The data signal line charges the pixel electrode to a second potential; wherein, the second potential is higher than the first potential.

10. The driving method according to claim 8, characterized in that, The driving period of one frame of the picture includes a third stage, a fourth stage, and a fifth stage; In the third stage, the gate signal line provides a third gate driving signal with a high level to the first transistor, turning on the first transistor. The data signal line writes a data signal of a second gray-scale voltage to the pixel electrode. The control signal line provides a high-level control signal to the second transistor, turning on the second transistor. The shared voltage line pulls down the potential of the pixel electrode to a third potential; In the fourth stage, the gate signal line provides a fourth gate driving signal with a high level to the first transistor, turning on the first transistor. The data signal line writes a data signal of a second gray-scale voltage to the pixel electrode. The control signal line provides a high-level control signal to the second transistor, turning on the second transistor. The shared voltage line pulls down the potential of the pixel electrode to a third potential; In the fifth stage, the gate signal line provides a fifth gate driving signal with a high level to the first transistor, turning on the first transistor. The data signal line writes a data signal of a first gray-scale voltage to the pixel electrode. The control signal line provides a low-level control signal to the second transistor, turning off the second transistor. The data signal line charges the pixel electrode to a fourth potential; wherein, the fourth potential is higher than the third potential.

11. The driving method according to claim 10, wherein, Within the third stage, the fourth stage, and the fifth stage, the data signal line charges the pixel electrode in sequence according to the order of the second gray-scale voltage, the second gray-scale voltage, and the first gray-scale voltage. The ratio of the sum of the durations of the third stage and the fourth stage to the duration of the fifth stage is 2:

1.

12. The driving method according to claim 8, wherein The driving period of one frame of the picture includes a sixth stage, a seventh stage, and an eighth stage; Within the sixth stage, the gate signal line provides a sixth gate driving signal with a high level to the first transistor, turning on the first transistor. The data signal line writes a data signal to the pixel electrode. The control signal line provides a high-level control signal to the second transistor, turning on the second transistor. The shared voltage line provides a low-level shared voltage signal to the pixel electrode, making the potential of the pixel electrode the fifth potential; In the seventh stage, the gate signal line provides a high-level seventh gate driving signal to the first transistor to turn on the first transistor, the data signal line writes a data signal to the pixel electrode, the control signal line provides a high-level control signal to the second transistor to turn on the second transistor, and the shared voltage line provides a high-level shared voltage signal to the pixel electrode to make the potential of the pixel electrode the sixth potential; In the eighth stage, the gate signal line provides a high-level eighth gate driving signal to the first transistor to turn on the first transistor, the data signal line writes a data signal to the pixel electrode, the control signal line provides a low-level control signal to the second transistor to turn off the second transistor, and the potential of the pixel electrode is the seventh potential.

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