server

Abstract

The present application discloses a server, which relates to the technical field of servers. By arranging a management control board vertically fixed on a main board, rather than arranging the management control board and the main board side by side on the same horizontal plane for layout, the length direction dimension of the server main board can be only the length direction dimension of the main board itself, rather than the total dimension of the main board and the management control board after they are superimposed in the length direction. Since the pluggable package is larger than the package size of the ball grid array package, by arranging a first flash memory and a second flash memory using the pluggable package, and the remaining first flash memories and second flash memories using the ball grid array package, the size of the management control board can be reduced as much as possible while ensuring that the initial debugging requirements of the board can be met, as well as the online burning requirements after the later functional development is complete, thereby achieving the purpose of reducing the overall size of the server main board in multiple directions.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a server. Background Art

[0002] With the rapid development of artificial intelligence (AI), especially the increasing application of large-scale deep learning models (such as speech recognition, image processing, and natural language processing), the demand for computing resources has increased dramatically. Modern servers, integrating high-performance CPUs and GPUs, provide powerful parallel computing capabilities, enabling them to efficiently process massive amounts of data and complex algorithms.

[0003] In the related art, a server circuit board consists of a main board and a management controller board. Figure 1 The two are placed in the same horizontal space, with the management control board connected to the motherboard via a gold finger interface. This design significantly extends the length of the server's main boards (mainboard + management control board), exceeding the dimensions of a standard chassis. This prevents the server from being properly placed within a standard chassis, limiting the server's physical deployment compatibility. Furthermore, the excessive length of the server's main boards increases the constraints on the internal PCB (printed circuit board) routing, making it prone to excessively long traces. In servers, excessively long traces can lead to signal attenuation and crosstalk, increasing the risk of signal quality issues and impacting overall server stability. Summary of the Invention

[0004] The present application provides a server to at least solve the problem in the related art that the main board of the server is too long in the length direction.

[0005] The present application provides a server, comprising a main board and a management control board;

[0006] The main board includes a first processor and a first auxiliary device; the management control board includes a second processor and a second auxiliary device; the second auxiliary device includes at least two first flash memories and at least two second flash memories, the first flash memories are used to provide storage services for the first processor, and the second flash memories are used to provide storage services for the second processor;

[0007] The management control board is vertically fixed on the main board, and the management control board is communicatively connected with the main board;

[0008] One of the first flash memory and one of the second flash memory are packaged in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged in a ball grid array and directly mounted on the management control board.

[0009] Through the present application, since the management control board is fixed vertically on the main board, rather than being arranged side by side with the main board on the same horizontal plane, the length dimension of the server main board can be made only the length dimension of the main board itself, rather than the total dimension of the main board and the management control board after being superimposed in the length direction. Therefore, the technical solution of the present application can effectively achieve the purpose of reducing the length dimension of the server main board. In addition, since the pluggable package is larger than the package size of the ball grid array package, a first flash memory and a second flash memory are provided in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged in a ball grid array and directly mounted on the management control board. The purpose is to reduce the size of the management control board as much as possible while ensuring that the initial debugging requirements of the board return and the online burning requirements after the later function development are complete can be met.

[0010] The reduced length of the server's main board and the management control board itself means they more easily fit within the internal space requirements of standard chassis, improving the server's physical deployment compatibility. Furthermore, the shortened length of the main board also reduces space constraints on the internal wiring layout of the printed circuit board (PCB) used to manufacture it, thereby reducing the possibility of excessively long wiring. This further reduces the risk of signal attenuation, crosstalk, and other signal quality issues caused by long signal transmission paths, thereby improving the overall stability and reliability of the server's operation.

[0011] The server provided by the technical solution of this application is particularly suitable for the field of artificial intelligence (AI) servers, and AI servers can be used to support the operation of large-scale deep learning models. In the current mainstream AI server architecture, the design method of directly connecting the CPU to multiple GPU nodes via PCIe at high speed is usually adopted. In order to ensure the stability and efficiency of signal transmission, the system has strict requirements on the signal transmission path between the CPU and the GPU, that is, the wiring distance should be shortened as much as possible to reduce signal delay and attenuation. The technical solution provided by this application provides greater flexibility in PCB wiring design because the size of the server main board in the length direction is shortened, which is conducive to planning a wiring layout that meets the AI ​​server's requirements for a shorter signal path between the CPU and the GPU. Therefore, the technical solution of this application can not only improve the hardware management efficiency of the AI ​​server, but also better meet its needs for high-performance computing and high-speed interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 This is a structural diagram of a server main board in the related art;

[0014] Figure 2 A schematic diagram of the structure of a server provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of a server main board provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the connection between a management control board and a main board provided in an embodiment of the present application;

[0017] Figure 5 A schematic diagram of a first surface of a management control board provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of a second surface of a management control board provided in an embodiment of the present application;

[0019] Figure 7 A schematic diagram of a partial structure of a management control board provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of the three-dimensional structure of a management control board provided in an embodiment of the present application;

[0021] Figure 9 A schematic diagram of the connection relationship between a management control board and a first connector provided in an embodiment of the present application;

[0022] Figure 10 A schematic diagram of the connection relationship between a first connector and a mainboard provided in an embodiment of the present application;

[0023] Figure 11 A schematic diagram of the SPI topology structure of a management control board provided in an embodiment of the present application;

[0024] Figure 12 A schematic diagram of the JTAG topology structure of a management control board provided in an embodiment of the present application;

[0025] Figure 13 A schematic diagram of the UART and LTPI topology structure of a management control board provided in an embodiment of the present application;

[0026] Figure 14 A schematic diagram of a management control board network topology provided in an embodiment of the present application;

[0027] Figure 15 A schematic diagram of the VGA and USB topology structure of a management control board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] The present application provides a server comprising a mainboard and a management control board; the mainboard comprising a first processor and a first auxiliary device; the management control board comprising a second processor and a second auxiliary device; the second auxiliary device comprising at least two first flash memories and at least two second flash memories, the first flash memories being used to provide storage services for the first processor, and the second flash memories being used to provide storage services for the second processor; the management control board being vertically fixed to the mainboard and communicatively connected to the mainboard. One first flash memory and one second flash memory are packaged in a pluggable manner and mounted on the management control board via a socket; the remaining first flash memories and second flash memories are packaged in a ball grid array and directly mounted on the management control board.

[0032] For example, Figure 2 A schematic diagram of the structure of a server provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a server main board provided in an embodiment of the present application; Figure 4 This is a schematic diagram of the connection between the management control board and the main board provided in the embodiment of the present application. Figure 2This server is available in either 8U or 10U form factors. The 8U server reserves 6U of space for the GPU (Graphics Processing Unit), while the 10U server reserves 8U of space for the GPU, achieving higher computing density. The PSU (Power Supply Unit) occupies 1U of space, leaving only 1U of space available for the server's mainboards, resulting in extremely compact overall space.

[0033] See also Figure 3 and Figure 4 The server includes a mainboard 1 and a management control board 2; the mainboard 1 includes a first processor and a first auxiliary device; the management control board 2 includes a second processor and a second auxiliary device; the management control board 2 is vertically fixed on the mainboard 1, and the management control board 2 is communicatively connected to the mainboard 1.

[0034] This application does not limit the specific devices referred to by the first processor and the first accessory device. For example, the first processor may be a CPU (Central Processing Unit). The first accessory device may include one or more of the following: a PDB (Power Distribution Board), a PWR-CON (Power Connector), an OCP (Open Compute Project) network card, a heat sink, a solid-state drive, a PHY (Physical Layer) device, etc.

[0035] Similarly, this application does not limit the specific devices referred to by the second processor and the second auxiliary device. For example, the second processor may be a BMC (Baseboard Management Controller). The second auxiliary device may include one or more of the following: a CPLD (Complex Programmable Logic Device), a JTAG (Joint Test Action Group) connector, a TPM (Trusted Platform Module), an EEPROM (Electrically Erasable Programmable Read-Only Memory), a voltage regulator, an EMMC (Embedded Multi-Media Card), a BIOS (Basic Input / Output System) flash memory, a BMC flash memory, a DRAM (Dynamic Random-Access Memory), and a PHY device.

[0036] The voltage regulator, also known as the VR, converts the P12V_STBY input from the motherboard via the cheat code into other voltage values ​​to power other components. The BMC is a core component for server system management. The BMC flash memory, also known as BMCFLASH, is used to store the BMC image file and determines the programs the BMC runs. The BIOS flash memory, also known as BIOSFLASH, is used to store the BIOS image file and determines the programs the CPU runs. The EMMC is a large storage medium that can store BMC operation logs or load the BMC's operating system into the EMMC to run certain top-level applications. The CPLD primarily implements power-on management and control functions on the board and interacts with the BMC, primarily through GPIO signals. The core function of the CPLD is to communicate with the motherboard. Specifically, this involves converting the parallel bus signals transmitted from the motherboard into serial bus format for transmission, decoding the serial signals internally, and forwarding relevant status information to the BMC for system monitoring and management. The PHY converts the BMC's Gigabit network signal, RGMII, to SGMII, increasing the transmission rate and extending the cable length. DRAM provides the BMC with memory, accelerating task processing. The TPM is used for security verification during BMC startup.

[0037] Optionally, when the first processor is a CPU, the first flash memory is a BIOS flash memory. When the second processor is a BMC, the second flash memory is a BMC flash memory.

[0038] The management control board is equipped with at least two first and second flash memories to achieve redundant storage functionality. By configuring multiple flash memories, even if one flash memory fails or data becomes corrupted, the remaining functioning flash memories can continue to handle data storage and retrieval, ensuring continuous system operation and data integrity. This redundant configuration effectively improves the reliability and fault tolerance of the management control board during operation.

[0039] "A first flash memory and a second flash memory are packaged in a pluggable manner and mounted on the management control board via a socket." For example, the first and second flash memories may be packaged in a SOP (Surrounding Object Programming) (SOP) format. The SOP package is a surface-mount plastic dual-inline small outline package with a standard pin pitch and a socket-compatible mechanical structure, facilitating manual replacement and suitable for use during system debugging. Accordingly, the sockets for mounting the first and second flash memories are secured to the management control board using a ball grid array (BGA) package, ensuring good electrical connection and mechanical stability between the sockets and the management control board. Thus, the first and second flash memories in the SOP package can be installed in the sockets via plug-in, achieving pluggable connection of the flash memory modules. This packaging method has a larger package size and is suitable for manual programming of the first and second flash memories during initial board commissioning, hardware verification, and firmware debugging. Alternatively, programming can be performed online after functional development is complete. The remaining flash memories not packaged in the SOP package (including the first and second flash memories) are directly soldered to the management control board using a BGA format, suitable for batch online programming after system operation stabilizes.

[0040] The technical solution of the present application is to fix the management control board vertically on the main board, rather than to arrange the management control board and the main board side by side on the same horizontal plane. This can make the length direction dimension of the server main board only the length direction dimension of the main board itself, rather than the total dimension of the main board and the management control board after they are superimposed in the length direction. Therefore, the technical solution of the present application can effectively achieve the purpose of reducing the length direction dimension of the server main board. In addition, since the pluggable package is larger than the package size of the ball grid array package, a first flash memory and a second flash memory are provided in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged in a ball grid array and directly mounted on the management control board. The purpose is to reduce the size of the management control board as much as possible while ensuring that the initial debugging requirements of the board return and the online burning requirements after the later functional development are complete can be met.

[0041] The reduced length of the server's main board and the management control board itself means they more easily fit within the internal space requirements of standard chassis, improving the server's physical deployment compatibility. Furthermore, the shortened length of the main board also reduces space constraints on the internal wiring layout of the printed circuit board (PCB) used to manufacture it, thereby reducing the possibility of excessively long wiring. This further reduces the risk of signal attenuation, crosstalk, and other signal quality issues caused by long signal transmission paths, thereby improving the overall stability and reliability of the server's operation.

[0042] The server provided by the technical solution of this application is particularly suitable for the field of artificial intelligence (AI) servers, and AI servers can be used to support the operation of large-scale deep learning models. In the current mainstream AI server architecture, the design method of directly connecting the CPU to multiple GPU nodes via PCIe at high speed is usually adopted. In order to ensure the stability and efficiency of signal transmission, the system has strict requirements on the signal transmission path between the CPU and the GPU, that is, the wiring distance should be shortened as much as possible to reduce signal delay and attenuation. The technical solution provided by this application provides greater flexibility in PCB wiring design because the size of the server main board in the length direction is shortened, which is conducive to planning a wiring layout that meets the AI ​​server's requirements for a shorter signal path between the CPU and the GPU. Therefore, the technical solution of this application can not only improve the hardware management efficiency of the AI ​​server, but also better meet its needs for high-performance computing and high-speed interconnection.

[0043] It should be noted that, in actual settings, the distance between the position on the motherboard for fixing the management control board and the position of the first processor can be set to be less than a set distance threshold, so as to shorten the distance between the second processor and the first processor, and the distance between the second processor and other devices on the motherboard, thereby reducing the probability of abnormal signal quality caused by excessive length of the signal line related to the second processor.

[0044] Furthermore, the second auxiliary device may include an EEPROM. The EEPROM may be packaged in a UDFN (Ultra-Thin Dual Flat No-Lead) package to reduce the size of the EEPROM, thereby reducing the size of the management control board.

[0045] Furthermore, the second auxiliary device may also include a resistor and / or a capacitor, and the resistor and / or the capacitor may be packaged in 0201 to reduce the size of the management control board.

[0046] On the basis of the above technical solutions, optionally, there are multiple second auxiliary devices; the multiple second auxiliary devices are respectively arranged on both sides of the management control board.

[0047] For example, Figure 5 is a schematic diagram of the first surface of a management control panel, Figure 6 This is a schematic diagram of a second surface of a management control panel. Figure 5 On the first surface of the management control board, there are two voltage regulators, VR1 and VR2, a physical layer device (PHY), an electrically erasable programmable read-only memory (EEPROM), a baseboard controller manager (BMC), a complex programmable logic device (CPLD), a joint test action group connector (JTAG CON), and a trusted platform module (TPM). Figure 6 On the second surface of the management control board, there are two voltage regulators, VR3 and VR4, an embedded multimedia card (EMMC), a temperature sensor (SENSOR), two first flash memories (BIOS flash0 and BIOS flash1), and two second flash memories (BMC flash0 and BMC flash1).

[0048] Multiple second auxiliary components are located on both sides of the management and control board, with some placed on the first surface and the remaining placed on the second surface. Distributing the second auxiliary components on both sides of the management and control board effectively utilizes circuit board space, avoiding the wiring congestion and increased board area caused by concentrating all components on a single side. This arrangement helps reduce the overall size of the management and control board while still meeting functional requirements, improving space utilization and ultimately enhancing its adaptability and integration within the server.

[0049] Furthermore, the second auxiliary device can also be provided with a plurality of stacked circuit layers, and a soldering pad is provided on the surface of the management control board, and the soldering pad is used for soldering the second processor and / or the second auxiliary device; the soldering pad is provided with a via hole passing through the management control board; the second processor and / or the second auxiliary device is electrically connected to the circuit layer in the management control board through the via hole on the soldering pad corresponding to its welding position.

[0050] Figure 7 This is a partial structural diagram of a management control panel provided by this application. Figure 7 The surface of the management control board 2 is provided with a plurality of pads 21, which are used to solder the second processor (such as the baseboard control manager) and / or the second auxiliary device (such as Figure 5 or Figure 6 Other components except the baseboard control manager, etc.). See Figure 7In the management and control board, some pads 21 are provided with vias 22 that penetrate the management and control board. The vias 22 can be blind holes or buried holes, thus forming a hole-on-plate structure.

[0051] By providing vias through the management and control board on the solder pads, the second processor and / or second accessory device can be electrically connected to one or more circuit layers within the management and control board through the vias on the solder pads corresponding to their respective soldering locations. Essentially, the vias are located directly on the solder pads and penetrate multiple dielectric layers of the management and control board (located between adjacent circuit layers), thereby establishing a reliable electrical path between the solder pads and the internal circuit layers. This design eliminates the traditional wiring practice of reserving space around soldered components for via placement and wiring connections, effectively utilizing the space beneath the solder pads. Without increasing the overall area of ​​the management and control board or the number of circuit layers, this approach enables more signal path interconnections between layers, significantly improving the density and flexibility of the management and control board's wiring. Furthermore, this approach shortens signal transmission paths, further improving signal transmission quality, reducing the potential for signal delays and interference, and enhancing the electrical performance and stability of the management and control board's wiring.

[0052] The solution of "providing vias on the pads that pass through the management and control board so that the second processor and / or the second auxiliary device can be electrically connected to the circuit layer in the management and control board through the vias on the pads corresponding to their welding positions" is particularly suitable for application scenarios where pads are formed in the form of ball grid array packaging. This is because devices using ball grid array packaging usually have a very dense pin arrangement, and the spacing between adjacent pins is extremely small, resulting in extremely limited space available for wiring and punching around them. In such high-density packaging structures, traditional peripheral wiring methods are often difficult to meet signal interconnection requirements. By providing vias on the pads, the pad body can be directly used as a signal lead-out channel, avoiding the additional occupation of peripheral wiring space, thereby effectively alleviating the problem of wiring congestion.

[0053] Optionally, in practice, low-speed GPIO signals or GND signals may be transmitted through vias on pads.

[0054] Based on the above technical solution, the server may further include a heat sink fixed to at least one side of the management control board. Specifically, the heat sink may be located near the first surface of the management control board, or near the second surface of the management control board.

[0055] The function of the heat sink is to quickly transfer heat from the heating element to the external environment. By providing a heat sink for the management and control board, the heat dissipation efficiency of the management and control board under high-load operation can be improved, thereby effectively reducing the operating temperature of key components (such as the second processor and the second auxiliary component), and avoiding problems such as performance reduction, system instability or shortened component life caused by local excessive temperature.

[0056] Furthermore, the server also includes a fixing part and a shell; the shell includes a side panel; the management control board is provided with a fixing hole that passes through the management control board; the fixing part passes through the fixing hole and the heat sink of the management control board, and is connected to the shell side panel of the server, fixing the management control board, the heat sink and the shell side panel of the server as a whole.

[0057] The server enclosure side panels are flat panels on the left and right sides of the server chassis. They are fixed to the chassis' main frame (such as the front, back, bottom, and top panels) with screws or clips, forming a closed box structure that covers and protects the internal hardware. These fixings can be, for example, screws or clips.

[0058] For example, in Figure 5 and Figure 6 In FIG. 1 , A1 and A2 represent fixing holes for passing fixing members.

[0059] Furthermore, the server may further include a limiting plate; the limiting plate is located on a side of the management control board away from the side plate of the housing, and the limiting plate is fixed to the main board and the management control board as a whole.

[0060] For example, see Figure 8 , the management and control board 2 is located between the limiting plate 4 and the heat sink 3. The limiting plate 4 is provided with three fixing holes, namely, fixing hole S1, fixing hole S2 and fixing hole S3. During installation, three fixing parts are selected for fixing. Specifically, the first fixing part passes through the fixing hole S1 on the limiting plate 4, the fixing hole A1 of the management and control board 2 and the heat sink, and is fixed as a whole with the outer shell side panel of the server. The second fixing part passes through the fixing hole S2 on the limiting plate 4, the fixing hole A2 of the management and control board 2 and the heat sink, and is fixed as a whole with the outer shell side panel of the server. The third fixing part passes through the fixing hole S3 on the limiting plate 4 and is fixed as a whole with the mainboard.

[0061] By setting the limit plate on the side of the management control board away from the side panel of the outer shell, and fixing the limit plate to the main board and the management control board as one, its essence is to use the limit plate to limit the position of the management control board in the server, to prevent the management control board from shaking during the movement of the server, and causing damage to the management control board and other adverse phenomena.

[0062] On the basis of the above technical solution, optionally, see Figure 4The server may further include a first connector 9 , which is connected between the main board 1 and the management control board 2 and is used to implement signal transmission between the main board 1 and the management control board 2 .

[0063] To achieve functional decoupling and structural independence between the management control board and the mainboard, the technical solution of this application introduces a first connector. The first connector establishes an electrical connection and signal transmission path between the management control board and the mainboard. The first connector has standardized pin definitions, allowing the management control board to interface with the mainboard as an independent functional module, independent of the specific design layout of the mainboard.

[0064] This connection method allows the management control board to be completely separated from the main board, allowing it to be developed, tested, maintained, and replaced as an independent module. In particular, if the management control board fails or requires an upgrade, it can be quickly replaced entirely by removing the first connector, eliminating the need to repair or replace the entire main board. This significantly improves the server's maintainability and scalability.

[0065] In addition, due to the standardized interface design of the first connector, the same management control board can be reused between different projects, reducing the duplication cost of hardware development and improving product iteration efficiency.

[0066] Optionally, the first connector is a 4C+ connector.

[0067] Figure 9 This is a schematic diagram of a connection between a first connector and a port on a management control board provided in an embodiment of the present application. Figure 10 This is a schematic diagram of a connection between a first connector and a port on a mainboard provided in an embodiment of the present application. Figure 9 and Figure 10 In the example, the first connector is a 4C+ connector.

[0068] See also Figure 9 and Figure 10The baseboard management controller (BMC) on the management control board establishes communication connections with the mainboard and external devices through various interfaces to perform functions such as status collection, remote control, and security management. Specifically, the BMC accesses I2C devices on the mainboard through the I2C (Inter-Integrated Circuit) interface and feeds relevant data back to the BMC, enabling real-time monitoring of the operating status of I2C devices on the mainboard. It also communicates with the mainboard's DIMMs (Dual In-line Memory Modules) through the I3C (Improved Inter-Integrated Circuit) interface to obtain and monitor system memory status information. Regarding graphics display, the BMC receives video signals from the mainboard through the PCIe EP interface and converts them into VGA (Video Graphics Array) signals for local or remote display.

[0069] Furthermore, the BMC communicates with high-speed peripherals in the server, such as PCIe switches, via the PCIe RC interface, enabling efficient management of their operating status. It obtains system startup status information via the ESPI / LPC (Enhanced Serial Peripheral Interface / Low-Pin Count) bus. This interface is a critical communication channel during system power-up, ensuring the BMC can respond promptly to system initialization events. Furthermore, the BMC accesses the BIOS image on the management control board via the SPI (Serial Peripheral Interface) and, in conjunction with the TPM (Trusted Platform Module), performs security verification of the image content to ensure system startup security.

[0070] Regarding interaction with network devices, the BMC establishes a 100M network connection with the OCP network card via NCSI (Network Controller Sideband Interface), enabling out-of-band network management. It also transmits system monitoring information to the network via SGMII (Serial Gigabit Media Independent Interface), allowing users to remotely view server operating status via a web interface. The LTPI (Low-Pin Translator Interface) is used for GPIO signal exchange between the BMC and the motherboard, using a CPLD (Complex Programmable Logic Device) for signal conversion and routing, effectively reducing pin resource utilization. In some scenarios, I2C signals and UART (Universal Asynchronous Receiver / Transmitter) signals can be multiplexed, further reducing pin resource utilization.

[0071] In addition, the BMC also includes several dedicated GPIO signals, such as HPM_EN (power-on enable), HPM_RDY (power-on ready), and HPM_RST (reset), which are used to implement power control logic interaction with the motherboard to ensure coordinated power management of the system in different operating modes. At the same time, the UART interface is used to transmit system serial port and BMC serial port signals, and the CPLD is used to select and switch the serial port channel, improving communication flexibility and system compatibility.

[0072] The following further explains the topology from five aspects: management control board and SPI topology, management control board and JTAG topology, management control board's UART and LTPI topology, management control board's network topology, and management control board's VGA and USB topology.

[0073] 1. Management Control Board and SPI Topology

[0074] Optionally, the server may be configured such that the second accessory device includes a first multiplexer and a first flash memory, the first multiplexer includes a first port, a second port, and a third port; the first port of the first multiplexer is connected to the second processor, the second port of the first multiplexer is connected to the first flash memory, and the third port of the first multiplexer is connected to the first connector; in the first multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

[0075] The first flash memory is used to provide storage services for the first processor (such as a central processing unit). The first multiplexer is used to control the on / off signal transmission between the first flash memory and the second processor, or between the first flash memory and the first processor.

[0076] The link status can be either an open state or an open state. For example, the link status between the first port and the third port of the first multiplexer is used for illustration. If the link status between the first port and the third port of the first multiplexer is an open state, it means that signals can be transmitted from the first port of the first multiplexer to the third port of the first multiplexer, or from the third port of the first multiplexer to the first port of the first multiplexer.

[0077] Optionally, when the first accessory device includes a third flash memory for providing storage services for the first processor, in the first multiplexer, the link state between the second port and the third port is a disconnected state; when the first accessory device does not include a third flash memory for providing storage services for the first processor, in the first multiplexer, the link state between the second port and the third port is a connected state.

[0078] Furthermore, the first accessory device includes a second multiplexer and a third flash memory, wherein the third flash memory is used to provide storage services for the first processor. The second multiplexer includes a first port, a second port, and a third port. The first port of the second multiplexer is connected to the first processor, the second port of the first multiplexer is connected to the third flash memory, and the third port of the first multiplexer is connected to the first connector. In the second multiplexer, the link status between the first port and the second port, as well as the link status between the second port and the third port, is adjustable. The second multiplexer is used to control signal transmission between the third flash memory and the second processor, or between the third flash memory and the first processor.

[0079] Optionally, when the server is in the boot process, the link state between the first port and the second port is a connection state; when the third flash memory is being firmwareed, the link state between the second port and the third port is a connection state.

[0080] For example, see Figure 11 , the second auxiliary device includes a first multiplexer MUX1 and a first flash memory. Figure 11 In the system, there are two first flash memories, BIOS0 and BIOS1. The purpose of having two first flash memories is to achieve redundant storage. This redundant design ensures that if one of the first flash memories fails or data is corrupted, the functioning first flash memory can continue to store and read data, thus ensuring continuous system operation and data integrity.

[0081] Continue to see Figure 11The first multiplexer MUX1 includes a first port a, a second port b, and a third port c. The first port a of the first multiplexer MUX1 is connected to the second processor (BMC), the second port b of the first multiplexer MUX1 is connected to the first flash memory (i.e., BIOS0 and BIOS1), and the third port c of the first multiplexer MUX1 is connected to the first connector (i.e., 4C+CON). In the first multiplexer MUX1, the link status between the first port a and the third port c, and the link status between the second port b and the third port c are adjustable.

[0082] The first auxiliary device includes a second multiplexer MUX2 and a third flash memory. Figure 11 In the system, there are two third flash memories, BIOS2 and BIOS3. The purpose of having two third flash memories is to achieve redundant storage. This redundant design ensures that if one of the third flash memories fails or data is corrupted, the functioning third flash memory can continue to store and read data, thus ensuring continuous system operation and data integrity.

[0083] The second multiplexer MUX2 includes a first port d, a second port e, and a third port f. The first port d of the second multiplexer MUX2 is connected to the first processor (e.g., a central processing unit on a motherboard), the second port e of the second multiplexer MUX2 is connected to the third flash memory (i.e., BIOS2 and BIOS3), and the third port f of the second multiplexer MUX2 is connected to the first connector (i.e., 4C+CON). In the second multiplexer MUX2, the link status between the first port d and the second port e, as well as the link status between the second port e and the third port f, are adjustable. Figure 11 In the embodiment, the first flash memory (ie, BIOS0 and BIOS1) and the third flash memory (ie, BIOS2 and BIOS3) are both used to provide storage services for the first processor (eg, the central processing unit on the motherboard).

[0084] Continue to see Figure 11 Because the motherboard is equipped with a third flash memory (i.e., BIOS2 and BIOS3), the link between the second port b and the third port c of the first multiplexer MUX1 is set to an open state. When the server is booting up, the link between the first port d and the second port f of the second multiplexer MUX2 is set to an open state, allowing the first processor (e.g., the motherboard's central processing unit) to access the third flash memory (i.e., BIOS2 and BIOS3). When performing a firmware upgrade on the third flash memory (i.e., BIOS2 and / or BIOS3), the link between the second port e and the third port f of the second multiplexer MUX2 is set to an open state, allowing the second processor (BMC) to access the third flash memory (i.e., BIOS2 and BIOS3) through the first connector for information updates.

[0085] If the motherboard does not have a third flash memory (i.e., BIOS2 and BIOS3), the first processor (e.g., the motherboard's central processing unit (CPU)) must read the firmware information from the first flash memory (i.e., BIOS0 and BIOS1). Therefore, when the server is booting up, the link between the third port c and the second port b of the first multiplexer MUX1 is set to be in a connected state, allowing the first processor (e.g., the motherboard's central processing unit) to access the first flash memory (i.e., BIOS0 and BIOS1). When upgrading the firmware in the first flash memory (i.e., BIOS0 and BIOS1), the link between the second port b and the first port a of the first multiplexer MUX1 is set to be in a connected state, allowing the second processor (BMC) to access the first flash memory (i.e., BIOS0 and BIOS1) for the update.

[0086] It should be noted that the bus connecting the first processor to the first flash memory (ie, BIOS0 and BIOS1) and the third flash memory (ie, BIOS2 and / or BIOS3) may be an SPI bus.

[0087] Continue to see Figure 11 , the control management board also includes a second flash memory. Figure 11 In the system, there are two secondary flash memories: BMC FLASH0 and BMC FLASH1. These secondary flash memories provide storage services for the secondary processor (such as the baseboard controller / manager). The purpose of having two secondary flash memories is to achieve storage redundancy. This redundancy ensures that if one of the secondary flash memories fails or data is corrupted, the functioning secondary flash memory can continue to store and read data, thus ensuring continuous system operation and data integrity.

[0088] 2. Management Control Board and JTAG Topology

[0089] The JTAG bus can be used to capture fault-related log information when a server fails, and to burn CPLDs (complex programmable logic devices).

[0090] Based on this, for the case where the JTAG bus is used to capture log information related to faults, in some embodiments, the first accessory device can be set to include a third multiplexer and a hardware detection tool; the third multiplexer includes a first port, a second port and a third port; the second processor is connected to the first connector through a first log collection line, the first connector is connected to the second end of the third multiplexer through a second log collection line, the first end of the third multiplexer is connected to the first processor, and the third end of the third multiplexer is connected to the hardware detection tool; in the third multiplexer, the link status between the first port and the third port, and the link status between the second port and the first port are adjustable.

[0091] Furthermore, when a server fault is detected, the link status between the second port and the first port is a path status, so that the second processor obtains log information related to the fault from the first processor; or, the link status between the first port and the third port is a path status, and the hardware detection tool obtains log information related to the fault from the first processor.

[0092] Figure 12 This is a schematic diagram of a management control board and JTAG topology provided by this application. Figure 12 The first accessory device includes a third multiplexer MUX3 and a hardware detection tool HDT. The third multiplexer MUX3 includes a first port g, a second port i, and a third port h. A second processor (e.g., a baseboard controller / manager (BMC)) is connected to a first connector (e.g., 4C+CON) via a first log collection line (which can be a JTAG bus). The first connector (e.g., 4C+CON) is connected to the second port i of the third multiplexer MUX3 via a second log collection line (which can be a JTAG bus). The first port g of the third multiplexer MUX3 is connected to the first processor (e.g., a central processing unit (CPU)). The third port h of the third multiplexer MUX3 is connected to the hardware detection tool HDT. The link status between the first port g and the third port h, as well as the link status between the second port i and the first port g, of the third multiplexer MUX3 are adjustable.

[0093] When a server failure is detected, the second processor (e.g., the baseboard controller and management system (BMC)) sends a first enable signal to the third multiplexer MUX3, causing it to switch its operating state. After the third multiplexer MUX3 switches its operating state, the link between the second port i and the first port g of the third multiplexer MUX3 becomes open. This allows the second processor (e.g., the baseboard controller and management system (BMC)) to remotely capture various information (i.e., logs) from the first processor (e.g., the central processing unit (CPU)) about the system's operation and failure process.

[0094] Alternatively, when a server failure is detected, a second enable signal is sent to the third multiplexer MUX3 via the second processor (e.g., the baseboard controller / manager BMC), causing the third multiplexer MUX3 to switch its operating state. After the operating state of the third multiplexer MUX3 switches, the link between the first port g and the third port h of the third multiplexer MUX3 becomes open. This allows the hardware detection tool HDT to capture various information (i.e., logs) from the first processor (e.g., the central processing unit (CPU)) during the system's operation and failure process.

[0095] In the case where the JTAG bus can be used to burn a CPLD (complex programmable logic device), in some embodiments, optionally, the second auxiliary device includes a fourth multiplexer, a fifth multiplexer, a first burning connector, and a first logic processing unit; the first logic processing unit is used to assist the second processor in hardware coordination and control; the first port of the fourth multiplexer is connected to the second processor, and the second port of the fourth multiplexer is connected to the first port of the fifth multiplexer; the third port of the fourth multiplexer is connected to the first connector; the second port of the fifth multiplexer is connected to the first burning connector; the third port of the fifth multiplexer is connected to the first logic processing unit; in the fourth multiplexer, the link status between the first port and the second port, and the link status between the first port and the third port are adjustable; in the fifth multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

[0096] Furthermore, the first auxiliary device includes a sixth multiplexer, a second programming connector, and a second logic processing unit; the second logic processing unit is used to assist the first processor in hardware coordination and control; the first connector is connected to the first end of the sixth multiplexer, the second end of the sixth multiplexer is connected to the second programming connector, and the third end of the sixth multiplexer is connected to the second logic processing unit; in the sixth multiplexer, the link status between the first port and the third port, as well as the link status between the second port and the third port, are adjustable.

[0097] Continue to see Figure 12The second auxiliary device includes a fourth multiplexer MUX4, a fifth multiplexer MUX5, a first programming connector JTAG HDR0, and a first logic processing unit SCM CPLD; the first logic processing unit SCM CPLD is used to assist the second processor (such as the baseboard control manager BMC) in hardware coordination and control; the first port j of the fourth multiplexer MUX4 is connected to the second processor (such as the baseboard control manager BMC), the second port m of the fourth multiplexer MUX4 is connected to the first port n of the fifth multiplexer MUX5; the third port k of the fourth multiplexer MUX4 is connected to the first connector (i.e., 4C+CON); the second port p of the fifth multiplexer MUX5 is connected to the first programming connector JTAG HDR0; the third port q of the fifth multiplexer MUX5 is connected to the first logic processing unit SCM CPLD connection; in the fourth multiplexer MUX4, the link state between the first port j and the second port m, and the link state between the first port j and the third port k are adjustable; in the fifth multiplexer MUX5, the link state between the first port n and the third port q, and the link state between the second port p and the third port q are adjustable.

[0098] Continue to see Figure 12 The first auxiliary device includes a sixth multiplexer MUX6, a second programming connector JTAG HDR1, and a second logic processing unit MB CPLD; the second logic processing unit MB CPLD is used to assist the first processor (such as a central processing unit CPU) in hardware coordination and control; the first connector (such as 4C+CON) is connected to the first end u of the sixth multiplexer MUX6, the second end v of the sixth multiplexer MUX6 is connected to the second programming connector JTAG HDR1, and the third end w of the sixth multiplexer MUX6 is connected to the second logic processing unit MB CPLD; in the sixth multiplexer MUX6, the link status between the first port u and the third port w, as well as the link status between the second port v and the third port w, are adjustable.

[0099] In the technical solution of this application, the first logic processing unit (SCM CPLD) is specifically used to control the power-on logic of the management control board and achieve cross-module collaborative control through a communication interface with the second logic processing unit (MB CPLD). Similarly, the second logic processing unit (MB CPLD) is responsible for mainboard power-on management and related logic control functions, and exchanges information with the first logic processing unit (SCM CPLD). The first logic processing unit (SCM CPLD) and the second logic processing unit (MB CPLD) together constitute the core control unit for power management, state synchronization, and remote control in the server system.

[0100] The firmware burning methods for CPLD (including the first logic processing unit SCM CPLD and the second logic processing unit MB CPLD) can include the following two methods: one is offline burning, that is, connecting a CPLD burner to a burning connector to complete program writing without connecting to the server main system; the other is online burning, that is, remote burning operation is achieved through the BMC (baseboard management controller), and firmware updates or repairs can be completed without physical contact with the device (such as the CPLD burner), thereby improving the system maintainability and deployment efficiency.

[0101] For Figure 12 The technical solution provided is as follows: when an offline burning method is used to write a CPLD program to the first logic processing unit SCM CPLD, the CPLD burner is connected to the burning connector JTAG HDR0, and the operating state of the fifth multiplexer MUX5 is adjusted so that the link state between the second port p and the third port q of the fifth multiplexer MUX5 is a pass state; and it is ensured that the burning signal is transmitted to the first logic processing unit SCM CPLD through the first burning connector JTAG HDR0 and the fifth multiplexer MUX5.

[0102] When the CPLD program is written to the second logic processing unit MB CPLD using an offline burning method, the CPLD burner is connected to the burning connector JTAG HDR1, and the operating state of the sixth multiplexer MUX6 is adjusted so that the link state between the second port v and the third port w of the sixth multiplexer MUX6 is a pass state; ensuring that the burning signal is transmitted to the second logic processing unit MB CPLD through the burning second connector JTAG HDR1 and the sixth multiplexer MUX6.

[0103] When the server is in normal operation and needs to burn the first logic processing unit SCM CPLD and / or the second logic processing unit MB CPLD online, the user can initiate a burning request by logging into the BMC web interface, and the second processor (i.e., the baseboard management controller BMC) controls the selection logic of the relevant multiplexers through its GPIO (general input and output) interface.

[0104] Specifically, when the first logic processing unit SCM CPLD is online burned, the operating states of the fifth multiplexer MUX5 and the fourth multiplexer MUX4 are adjusted so that the link state between the first port n and the third port q of the fifth multiplexer MUX5 is in the through state, and the link state between the first port j and the second port m of the fourth multiplexer MUX4 is in the through state, ensuring that the burning signal is transmitted to the first logic processing unit SCM CPLD through the second processor (i.e., the baseboard management controller BMC), the fourth multiplexer MUX4, and the fifth multiplexer MUX5.

[0105] When the second logic processing unit MB CPLD is being programmed online, the operating states of the sixth multiplexer MUX6 and the fourth multiplexer MUX4 are adjusted so that the link state between the first port u and the third port w of the sixth multiplexer MUX6 is in a pass state, and the link state between the first port j and the third port k of the fourth multiplexer MUX4 is in a pass state, ensuring that the programming signal is transmitted to the second logic processing unit MB CPLD through the second processor (i.e., the baseboard management controller BMC), the fourth multiplexer MUX4, and the sixth multiplexer MUX5.

[0106] This design supports free switching between two burning modes, providing the possibility of functional upgrade of the first logic processing unit SCM CPLD and the second logic processing unit MB CPLD, which can improve the maintainability, security and deployment flexibility of the server system.

[0107] It should be noted that in each of the above technical solutions, a second processor (i.e., a baseboard management controller (BMC)) can be configured to control the selection logic of the relevant multiplexer via a GPIO (general purpose input / output) interface. This can be used to capture fault-related log information, program a CPLD (complex programmable logic device), assist the CPU in accessing a flash memory that can provide storage services, or perform firmware upgrades on the flash memory that can provide storage services for the CPU.

[0108] 3. UART and LTPI topology of the management control board

[0109] In some embodiments, optionally, the second accessory device includes a first signal exchanger; the first signal exchanger is connected to the second processor through multiple first functional buses, and different first functional buses are used to transmit signals of different functions; the first signal exchanger is also connected to the first connector through a first serial bus.

[0110] Optionally, the first accessory device includes a second signal switch, a third connector, and a third signal switch; the second signal switch is connected to the first connector via a second serial bus; the second signal switch is also connected to the third signal switch and the third connector; the third signal switch is used to receive signals from the third processor.

[0111] Optionally, the first logic processing unit can be reused as the first signal exchanger. This configuration can reduce the number of components installed in the management control board, thereby reducing the area of ​​the management control board. Similarly, the second logic processing unit can be reused as the second signal exchanger. This configuration can also reduce the number of components installed in the main board, thereby reducing the area of ​​the main board.

[0112] For example, see Figure 13 The second auxiliary device includes a first signal exchanger (such as a first logic processing unit SCM CPLD); the first signal exchanger (ie, SCM CPLD) and the second processor (ie, baseboard management controller BMC) are connected via a plurality of first functional buses (in Figure 13 The first function buses are connected to the BMC UART, CPU UART and SMART NIC UART), and different first function buses are used to transmit signals of different functions; the first signal exchanger (i.e., the first logic processing unit SCM CPLD) is also connected to the first connector (such as 4C+CON) through a first serial bus (for example, it can be SGPIO or LTPI).

[0113] Optionally, the first accessory device includes a second signal switch (e.g., a second logic processing unit MB CPLD), a third connector (e.g., UART CON), and a third signal switch (e.g., PCIE SW); the second signal switch (e.g., the second logic processing unit MB CPLD) is connected to the first connector (e.g., 4C+CON) via a second serial bus (e.g., SGPIO or LTPI); the second signal switch (e.g., the second logic processing unit MB CPLD) is further connected to the third signal switch (e.g., PCIE SW) and the third connector (e.g., UART CON); the third signal switch (e.g., PCIE SW) is used to receive signals from a third processor (e.g., a graphics processor GPU, in Figure 13 signal not shown).

[0114] To fully monitor the operating status of the server motherboard, the BMC (baseboard management controller) needs to obtain and parse key logic control signals and serial port information from the motherboard. However, due to the limited number of interconnect interfaces between the motherboard and the SCM (system management module) board, directly transmitting all status signals through multiple independent GPIO pins leads to problems such as high wiring complexity and limited pin resources. The above technical solution is essentially a signal aggregation mechanism based on a serial bus (such as SGPIO or LTPI). Multiple GPIO signals that need to be monitored are uniformly connected to the serial bus. The motherboard transmits the relevant status information to the SCM CPLD, which then converts it into standard GPIO signals and outputs them to the BMC for collection and analysis, thereby achieving remote monitoring of the motherboard's key operating status.

[0115] Furthermore, regarding serial communication, the CPU's serial port information must be transmitted to the BMC via the LPC or eSPI bus for analysis. All serial port logs generated during system operation must be output via the serial port connector (i.e., URATCON) on the I / O panel. Furthermore, to meet remote O&M requirements, information from three key serial ports—the BMC UART, the CPU UART, and the SMART NIC UART—must also be remotely accessible and viewable via a network interface. Therefore, all three serial port signals must ultimately be connected to the BMC.

[0116] It should be noted again that, considering that the management control board and the main board are connected via a 4C+ high-speed connector, and the available pin resources of the connector are limited, it is impossible to directly transmit all serial port signals one by one to the main board. To this end, the present application further provides a multi-channel serial port multiplexing switching mechanism based on CPLD: first, all serial port signals on the management control board are aggregated and connected to the SCM CPLD, and a virtual UART Switch (serial port selection switch) is constructed inside the CPLD to achieve selective output of three signals: BMC UART, CPU UART and Smart NIC UART. Subsequently, the selected serial port signal is transmitted to the MB CPLD on the main board through the 4C+ connector.

[0117] The MB CPLD further integrates processing logic for signals related to the GPU node's PCIe switch (PCIE SW). Internal logic is used to consolidate and select multiple serial port signals. Ultimately, the selected serial port signal is output to the front panel's serial port connector, allowing users to obtain serial port information during system operation through the front panel's physical interface or remotely access the required serial port data through the BMC's network interface.

[0118] This technical solution effectively addresses the serial signal transmission issues caused by the limited pin resources of the 4C+ connector by introducing a CPLD-based serial signal aggregation and multi-path selection mechanism. It also enables the simultaneous output of critical serial port information on both the network and front panel, improving system observability, maintainability, and remote management efficiency. This solution is particularly suitable for applications such as high-density AI servers that require high spatial layout and signal integrity.

[0119] 4. Network topology of the management control panel

[0120] In some examples, optionally, the second accessory device includes a first physical layer device, the first accessory device includes a second physical layer device and a first network card; the second processor is connected to the first connector via a network card management bus; the second processor is connected to the first physical layer device via a parallel network data transmission bus, and the first physical layer device is connected to the first connector via a first serial network data transmission bus; the first connector is connected to the second physical layer device via a second serial network data transmission bus, and the second physical layer device is connected to the network interface; the second processor is also connected to the first physical layer device and the second physical layer device via a first control signal line.

[0121] Figure 14 This is a schematic diagram of the network topology of a management control board provided by this application. Figure 14 , exemplarily, the second accessory device includes a first physical layer device (PHY1), the first accessory device includes a second physical layer device (PHY2) and a first network card ( Figure 14 In the example, the first network card is an OCP network card); the second processor (ie, the baseboard management controller BMC) is connected to the first connector (eg, Figure 14 The second processor (i.e., baseboard management controller BMC) is connected to the first physical layer device (i.e., PHY1) through a parallel network data transmission bus, and the first physical layer device (i.e., PHY1) is connected to the first connector (e.g., Figure 14 4C+CON) connection; the first connector (e.g. Figure 14 4C+CON in the figure) is connected to the second physical layer device (ie, PHY2) through the second serial network data transmission bus, and the second physical layer device (ie, PHY2) is connected to the network interface (exemplarily, Figure 14 The second processor (ie, baseboard management controller BMC) is also connected to the first physical layer device (ie, PHY1) and the second physical layer device (ie, PHY2) through the first control signal line.

[0122] Here, the first physical layer device (ie, PHY1 ) and the second physical layer device (ie, PHY2 ) may be, for example, Ethernet PHY devices, high-speed SerDes PHY devices, and retimer PHY devices.

[0123] Alternatively, see Figure 14 Alternatively, the network card management bus (NIC) between the second processor (i.e., baseboard management controller (BMC)) and the first connector (e.g., 4C+CON) and the NIC management bus between the first connector (e.g., 4C+CON) and the OCP NIC can both be NCSI buses. The NCSI bus enables the BMC to remotely manage network devices.

[0124] Optionally, the parallel network data transmission bus connected between the second processor (ie, baseboard management controller BMC) and the first physical layer device (ie, PHY1) is a GRMII bus, which is connected between the first physical layer device (ie, PHY1) and the first connector (ie, Figure 14 The first serial network data transmission bus between the first and second physical layer devices (i.e., 4C+CON in the example) is the SGMII bus. The first control signal line output from the second processor (i.e., the baseboard management controller BMC) for controlling the first physical layer device (i.e., PHY1) and the second physical layer device (i.e., PHY2) is the MDIO / MDC bus.

[0125] The core concept of this application's technical solution is that the control management board and the main board are physically isolated and not built on the same circuit board. If cross-board transmission is performed using the RGMII protocol, timing matching and wiring length will be difficult to meet control requirements. Directly using the RGMII protocol for cross-board transmission may result in reduced signal integrity and inability to guarantee communication stability.

[0126] Furthermore, due to the limited space of the management and control board, the RJ45 physical interface is difficult to place on the miniaturized management and control board. Therefore, it is impossible to convert RGMII signals into MDI (Media Dependent Interface) format for long-distance transmission. To address this, the above technical solution essentially converts network signals originally based on the RGMII protocol into SGMII protocol signals for transmission based on the signal conversion mechanism of the PHY device.

[0127] As a serialized network interface protocol, SGMII offers enhanced anti-interference capabilities and more flexible routing, making it particularly suitable for long-distance, high-density PCB traces. This conversion method not only solves the timing matching challenges inherent in RGMII cross-board transmission, but also effectively improves the stability and reliability of network signal transmission.

[0128] Furthermore, the BMC connects to the PHY1 on the management control board via a set of MDC and MDIO signal lines, and uses a daisy chain to establish communication with other PHY2 on the mainboard. This structure facilitates network status monitoring and remote configuration management of the entire server system.

[0129] 5. VGA and USB topology of management control board

[0130] In some embodiments, the server casing is provided with a first external interface; the first processor is connected to the first connector via a first display signal transmission bus, the first connector is connected to the second processor via a second display signal transmission bus, the second processor is connected to the first connector via a first video transmission bus and a third serial bus; the first connector is connected to the first external interface on the server casing via a second video transmission bus and a fourth serial bus.

[0131] Furthermore, a signal converter is provided on the mainboard; the first connector is connected to the signal converter via the second video transmission bus and the fourth serial bus, and the signal converter is connected to the first external interface on the server housing via a cable.

[0132] Figure 15 This is a schematic diagram of the VGA and USB topology of a management control board provided in this application.

[0133] See also Figure 15 The server housing is provided with a first external interface; the first processor (e.g., central processing unit CPU) is connected to the first connector (e.g., 4C+CON) via a first display signal transmission bus, and the first connector (e.g., 4C+CON) is connected to the second processor (e.g., baseboard management controller BMC) via a second display signal transmission bus (e.g., PCIE bus). The second processor (e.g., baseboard management controller BMC) is connected to the first connector (e.g., 4C+CON) via a first video transmission bus (e.g., VGA) and a third serial bus (e.g., USB); the first connector (e.g., 4C+CON) is connected to the first external interface (e.g., 4C+CON) on the server housing via a second video transmission bus (e.g., VGA) and a fourth serial bus (e.g., USB). Figure 15 (not shown) connection.

[0134] Further, see Figure 10 The main board 1 is provided with a signal converter 6 ( Figure 15 The signal converter is marked as MCIO); the first connector (such as 4C+CON) is connected to the signal converter 6 through the second video transmission bus and the fourth serial bus, and the signal converter 6 is connected to the first external interface on the server housing through a cable. The first external interface is set on the front panel of the server housing. Figure 15 In the server case, FRONT PANEL is used to refer to the front panel of the server case. Figure 10 In the figure, FP is used to refer to the front panel of the server housing.

[0135] Using the technical solution of this application, the VGA (Video Graphics Array) or DP (DisplayPort) display signal required by the BMC (Baseboard Management Controller) is generated by the CPU via PCIe resources and transmitted to the BMC. To implement local or remote display control of the server system, this video signal must be converted and routed before being output to the first external interface on the server's front panel. Furthermore, the USB access function supported by the BMC must also be connected to the first external interface to facilitate operations such as peripheral access, system debugging, and firmware updates.

[0136] Those skilled in the art will understand that by setting a first connector to be connected to the signal converter through the second video transmission bus and the fourth serial bus, the signals transmitted in the second video transmission bus and the fourth serial bus can be converted two-in-one, so as to reduce the number of first external interfaces that need to be set on the server housing, and realize the intensive design of the server hardware architecture.

[0137] Furthermore, the signal converter connects to the first external interface on the server housing via a cable, rather than using motherboard wiring to achieve the electrical connection between the signal converter and the first external interface. This design reduces motherboard design complexity, avoids excessive signal cable lengths, simplifies the motherboard's internal circuit layout, and ultimately improves signal integrity.

[0138] On the basis of the above technical solutions, optionally, the operation process of the server may include a power-on process, a kernel loading process, a function enabling process, a display function activation process, an operation supervision process and a control process.

[0139] Power-on process: When the management control board is plugged into the first connector on the motherboard, the power supply unit (PSU) outputs the P12V_PSU voltage, which is transmitted to the electronic fuse (EFUSE) as the power input for the management control board. The presence detection signal (PRSNT_N) controls the EFUSE enable state. If PRSNT_N is high, the management control board is not properly inserted (not in place), the EFUSE enable signal is low, and the board cannot be powered on. If PRSNT_N is low, the board is in place, the EFUSE enable signal is high, and the power-on process begins. The P12V_PSU voltage is converted by the EFUSE to the P12V_STBY_SCM power network, which powers the voltage regulator (VR) on the management control board. The VR then generates different voltage signals in sequence according to the BMC power-on requirements to provide appropriate power to the BMC and other components on the management control board.

[0140] Kernel loading process: After the management control board is powered on, it sends the voltage signal (PWRGD) output by the last voltage regulator (VR) as the HPM enable signal (HPM_EN) to the motherboard's EFUSE module, triggering the motherboard power-on process. Simultaneously, the BMC loads firmware from its own flash memory (BMC FLASH) and starts the kernel program. Once the kernel is loaded, basic BMC functions (such as network communication and its own serial port) are enabled, preparing for subsequent interactions.

[0141] Function Enabling Process: When the kernel is loaded, the motherboard is usually powered on. After the motherboard powers on, the HPM Ready signal (HPM_RDY) signals the logic processing unit (MB CPLD) in the management control board. The BMC then resets itself and then resets the motherboard via the HPM Reset signal (HPM_RST). After the motherboard resets, the BMC loads the bootloader (uboot). At this point, most bus functions on the management control board become active and accessible. After the motherboard loads the Basic Input / Output System (BIOS), the BMC establishes communication (handshake) with the motherboard CPU via the Enhanced Serial Peripheral Interface (ESPI) or Low Pin Count (LPC) bus. It accesses slave devices via the I2C bus and memory resources via the I3C bus, while also monitoring system temperature. The SCM CPLD in the management control board and the MB CPLD in the motherboard also continuously exchange hardware status information.

[0142] Display function activation process: When the user presses the system power-on button, the system completes the power-on process according to the preset timing. After the CPU sends PCIe resources to the BMC and the PCIe reset signal (PERST) completes the reset, the BMC's display function is officially enabled, supporting external display devices. At this point, the management control board is fully functional.

[0143] Operational Monitoring and Control: From the moment the display function is activated until the system is powered off, the management control board continuously monitors the system. This monitoring includes real-time monitoring of system temperature, graphics processing unit (GPU) temperature, the operating status of key components (such as PCIe switches), and overall system power consumption. The management control board also provides control capabilities: users can access the web management interface through the BMC to view system operating parameters; support manual / automatic fan speed adjustment; and online updates and upgrades of the BIOS, BMC program, CPLD firmware, and the firmware of the PCIe switch connected to the GPU, ensuring long-term system stability and maintainability.

[0144] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0145] The above is a detailed introduction to a server provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A server, characterized in that: Including main board and management control board; The mainboard includes a first processor and a first accessory device; The first auxiliary device includes a third flash memory; and / or, The first auxiliary device includes a second multiplexer and a third flash memory; and / or, The first auxiliary device includes a third multiplexer and a hardware detection tool; and / or, The first auxiliary device includes a sixth multiplexer, a second burning connector and a second logic processing unit; and / or, The first accessory device includes a second signal switch, a third connector, and a third signal switch; and / or, The first auxiliary device includes a second physical layer device and a first network card; The management control board includes a second processor and a second auxiliary device; the second auxiliary device includes at least two first flash memories and at least two second flash memories, the first flash memories are used to provide storage services for the first processor, and the second flash memories are used to provide storage services for the second processor; The management control board is vertically fixed on the main board, and the management control board is communicatively connected with the main board; One of the first flash memory and one of the second flash memory are packaged in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged in a ball grid array and directly mounted on the management control board.

2. The server according to claim 1, wherein: There are multiple second auxiliary devices; A plurality of the second auxiliary devices are respectively arranged on both sides of the management control board.

3. The server according to claim 1, wherein: The management control board includes multiple stacked circuit layers, and a soldering pad is provided on the surface of the management control board, which is used to solder the second processor and / or the second auxiliary device; the soldering pad is provided with a via hole that passes through the management control board; the second processor and / or the second auxiliary device is electrically connected to the circuit layer in the management control board through the via hole on the soldering pad corresponding to their welding position.

4. The server according to claim 1, wherein: The server further includes a heat sink; The heat sink is fixed to at least one side of the management control board.

5. The server according to claim 4, wherein: The server further includes a fixing member and a housing; the housing includes a side panel; The management control board is provided with a fixing hole that passes through the management control board. The fixing member passes through the fixing hole of the management control board and the heat sink, and is connected to the shell side plate of the server, thereby fixing the management control board, the heat sink and the shell side plate of the server as a whole.

6. The server according to claim 5, wherein: The server further includes a limit plate; The limiting plate is located on a side of the management and control board away from the side plate of the housing, and the limiting plate is fixed to the main board and the management and control board as a whole.

7. The server according to claim 1, wherein: The server further includes a first connector, which is connected between the mainboard and the management control board and is used to implement signal transmission between the mainboard and the management control board.

8. The server according to claim 7, wherein: The second accessory device includes a first multiplexer, the first multiplexer including a first port, a second port, and a third port; The first port of the first multiplexer is connected to the second processor, the second port of the first multiplexer is connected to the first flash memory, and the third port of the first multiplexer is connected to the first connector; In the first multiplexer, a link state between the first port and the third port, and a link state between the second port and the third port are adjustable.

9. The server according to claim 8, wherein: When the first auxiliary device includes a third flash memory for providing storage services for the first processor, in the first multiplexer, the link state between the second port and the third port is a disconnected state; When the first accessory device does not include a third flash memory for providing storage services for the first processor, in the first multiplexer, the link status between the second port and the third port is a connection status.

10. The server according to claim 8, wherein: The first auxiliary device includes a second multiplexer and a third flash memory, and the third flash memory is used to provide storage services for the first processor; The second multiplexer includes a first port, a second port, and a third port; The first port of the second multiplexer is connected to the first processor, the second port of the second multiplexer is connected to the third flash memory, and the third port of the second multiplexer is connected to the first connector; In the second multiplexer, a link state between the first port and the second port and a link state between the second port and the third port are adjustable.

11. The server according to claim 10, wherein: When the server is in the boot process, the link state between the first port and the second port of the second multiplexer is a connection state; When the third flash memory is in the process of firmware upgrade, the link state between the second port and the third port of the second multiplexer is a connection state.

12. The server according to claim 7, wherein: The first auxiliary device includes a third multiplexer and a hardware detection tool; the third multiplexer includes a first port, a second port and a third port; The second processor is connected to the first connector via a first log collection line, the first connector is connected to the second end of the third multiplexer via a second log collection line, the first end of the third multiplexer is connected to the first processor, and the third end of the third multiplexer is connected to the hardware detection tool; In the third multiplexer, the link status between the first port and the third port, and the link status between the second port and the first port are adjustable.

13. The server according to claim 12, wherein: When a fault is detected in the server, the link status between the second port and the first port of the third multiplexer is a connected state, so that the second processor obtains log information related to the fault from the first processor; or the link status between the first port and the third port of the third multiplexer is a connected state, and the hardware detection tool obtains log information related to the fault from the first processor.

14. The server according to claim 7, wherein: The second auxiliary device includes a fourth multiplexer, a fifth multiplexer, a first burning connector and a first logic processing unit; The first logic processing unit is used to assist the second processor in hardware coordination and control; The first port of the fourth multiplexer is connected to the second processor, and the second port of the fourth multiplexer is connected to the first port of the fifth multiplexer; The third port of the fourth multiplexer is connected to the first connector; The second port of the fifth multiplexer is connected to the first burning connector; The third port of the fifth multiplexer is connected to the first logic processing unit; In the fourth multiplexer, the link status between the first port and the second port, and the link status between the first port and the third port are adjustable; In the fifth multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

15. The server according to claim 14, wherein: The first auxiliary device includes a sixth multiplexer, a second programming connector, and a second logic processing unit; the second logic processing unit is used to assist the first processor in hardware coordination and control; The first connector is connected to a first terminal of the sixth multiplexer, a second terminal of the sixth multiplexer is connected to the second burning connector, and a third terminal of the sixth multiplexer is connected to the second logic processing unit; In the sixth multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

16. The server according to claim 7, wherein: The second accessory device includes a first signal switch; The first signal exchanger is connected to the second processor via a plurality of first functional buses, where different first functional buses are used to transmit signals of different functions; The first signal switch is also connected to the first connector via a first serial bus.

17. The server according to claim 16, wherein: The first accessory device includes a second signal switch, a third connector, and a third signal switch; The second signal switch is connected to the first connector via a second serial bus; the second signal switch is also connected to the third signal switch and the third connector; The third signal switch is used to receive a signal from a third processor.

18. The server according to claim 7, wherein: The second auxiliary device includes a first physical layer device, and the first auxiliary device includes a second physical layer device and a first network card; The second processor is connected to the first connector via a network card management bus; The second processor is connected to the first physical layer device via a parallel network data transmission bus, and the first physical layer device is connected to the first connector via a first serial network data transmission bus; the first connector is connected to the second physical layer device via a second serial network data transmission bus, and the second physical layer device is connected to the network interface; The second processor is further connected to the first physical layer device and the second physical layer device via a first control signal line.

19. The server according to claim 7, wherein: The shell of the server is provided with a first external interface; The first processor is connected to the first connector via a first display signal transmission bus, the first connector is connected to the second processor via a second display signal transmission bus, and the second processor is connected to the first connector via a first video transmission bus and a third serial bus; The first connector is connected to the first external interface on the server housing through a second video transmission bus and a fourth serial bus.

20. The server according to claim 19, wherein: A signal converter is provided on the main board; The first connector is connected to the signal converter via a second video transmission bus and a fourth serial bus, and the signal converter is connected to the first external interface on the server housing via a cable.

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