Address remapping method, hardware online upgrading method, circuit, device and system

Abstract

The embodiment of the invention discloses an address remapping method, a hardware online upgrading method, a circuit, a device and a system. Wherein the address remapping circuit is used for detecting whether a current instruction address of the microprocessor points to an interrupt vector table of an initial program code area, and when it is detected that the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area, address offset is carried out on the current instruction address according to a target offset address; and reading the target reset vector in the code memory according to the shifted instruction address. Wherein the target offset address is an initial address of the target program code area. Therefore, the address remapping circuit is arranged to assist the microprocessor in performing program code area jumping, and the embodiment of the invention can enable the microprocessor to realize program code area jumping on the premise that the microprocessor does not have program code area jumping capability, thereby supporting deployment and operation of a multi-program code area storage architecture, and improving the program code area jumping efficiency. And thus, hardware online upgrading is supported.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware upgrade, and particularly relates to an address remapping method, a hardware over-the-air (FOTA) upgrade method, a circuit, a device and a system. Background Art

[0002] As the functions carried by the MCU (Microcontroller Unit) become more and more complex, the hardware over-the-air (FOTA) upgrade has become an essential item among the many functions of the MCU. Among them, the hardware over-the-air upgrade is used to support the MCU to upgrade its own application program version online without returning to the factory. At present, the hardware over-the-air upgrade is usually implemented by the MCU through deploying and running a multi-program code area storage architecture. However, the deployment and operation of the multi-program code area storage architecture often require the MCU itself to have the ability to jump between program code areas, which makes some MCUs that do not have the ability to jump between program code areas unable to deploy and run the multi-program code area storage architecture, and thus these MCUs cannot achieve the hardware over-the-air upgrade. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an address remapping method, a hardware over-the-air upgrade method, a circuit, a device and a system, so that the microprocessor can achieve the jump between program code areas on the premise that it does not have the ability to jump between program code areas, thereby supporting the deployment and operation of the multi-program code area storage architecture, and further supporting the hardware over-the-air upgrade.

[0004] In a first aspect, an embodiment of the present invention aims to provide an address remapping circuit, and the address remapping circuit includes:

[0005] A logic judgment circuit, configured to judge whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area;

[0006] An address offset circuit, configured to, in response to the current instruction address pointing to the interrupt vector table of the initial program code area, perform address offset on the current instruction address according to a target offset address, where the target offset address is the starting address of the target program code area;

[0007] A reading circuit, configured to read a target reset vector from a code memory according to the offset instruction address.

[0008] In a second aspect, an embodiment of the present invention aims to provide an address remapping method, which is applicable to the address remapping circuit, and the method includes:

[0009] Judge whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area;

[0010] In response to the current instruction address pointing to the interrupt vector table in the initial program code area, perform an address offset on the current instruction address according to the target offset address, where the target offset address is the starting address of the target program code area;

[0011] Read the target reset vector from the code memory according to the offset instruction address.

[0012] In a third aspect, an embodiment of the present invention aims to provide a hardware online upgrade method, and the method includes:

[0013] Set the first offset value to the starting address of the target program code area;

[0014] Initiate a system reset. During the system reset process, the current instruction address is configured to point to the interrupt vector table in the initial program code area, and the condition value is reset to a first value; the first value is used to indicate selecting the first offset value as the target offset address for output;

[0015] In response to the current instruction address pointing to the interrupt vector table in the initial program code area, perform an address offset on the current instruction address according to the target offset address;

[0016] Read the target reset vector from the code memory according to the offset instruction address;

[0017] Jump to the target program code area according to the target reset vector to execute the hardware online upgrade process.

[0018] In a fourth aspect, an embodiment of the present invention aims to provide a hardware online upgrade system, and the system includes:

[0019] A code memory;

[0020] A microprocessor; and

[0021] An address remapping circuit as described in any one of the first aspects.

[0022] The address remapping circuit in the embodiment of the present invention is used to detect whether the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area, and when it is detected that the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area, perform address offset on the current instruction address according to the target offset address, and read the target reset vector from the code memory according to the offset instruction address. Wherein, the target offset address is the starting address of the target program code area. Thus, by setting up the address remapping circuit to assist the microprocessor in jumping between program code areas, the embodiment of the present invention enables the microprocessor to achieve jumping between program code areas without its own ability to jump between program code areas, thereby supporting the deployment and operation of a multi-program code area storage architecture, and further supporting hardware in-line upgrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0024] Figure 1 is a schematic diagram of the hardware in-line upgrade system according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the code memory according to an embodiment of the present invention;

[0026] Figure 3 is a flowchart of the address remapping method according to an embodiment of the present invention;

[0027] Figure 4 is a circuit diagram of the offset address output circuit according to an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of the address remapping circuit according to an embodiment of the present invention;

[0029] Figure 6 is a flowchart of the hardware in-line upgrade method according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following is a description of the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, components and circuits are not described in detail.

[0031] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0032] Unless the context clearly requires otherwise, words such as "including" and "comprising" in the entire application document shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0033] In the description of this application, it should be understood that terms such as "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0034] For the solutions described in this specification and embodiments, if they involve personal information processing, they will be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. A user's refusal to process personal information other than the necessary information required for basic functions will not affect the user's use of basic functions.

[0035] It should be noted that the deployment of a multi-program code area storage architecture specifically refers to dividing multiple program code storage areas in a code memory and storing the program codes of different programs in the multiple program code storage areas respectively. During the hardware online upgrade process, the existence of the multi-program code area storage architecture can ensure that the microprocessor can upgrade the version of the main program by switching to run other programs. In various embodiments of the present invention, the multi-program code area storage architecture may include at least one application program code area and a bootloader code area. Among them, the application program code area is used to store the program code of the application program. The application program can be the main program of the microprocessor, which can be run by the microprocessor to enable the microprocessor to implement corresponding business logics and thus provide services or functions externally. The bootloader code area is used to store the program code of the bootloader. The bootloader can be an auxiliary program of the microprocessor, which can be run by the microprocessor to enable the microprocessor to perform initialization processing of the hardware when the system is powered on, and perform operations such as downloading and verifying a new version of the application program and replacing the old version of the application program during the hardware online upgrade process.

[0036] Optionally, during actual application, according to the different numbers of application program code areas set, relevant embodiments may adopt different hardware upgrade methods. For example, when the number of application program code areas is unique, the unique application program code area can be used to store the current latest version of the application program code. In this scenario, when the microprocessor jumps to the bootloader code area and performs hardware online upgrade by running the bootloader, it can download and verify the upgrade package of the new version of the application program, and directly replace the old version of the application program code stored in the application program code area with the new version of the application program code according to the upgrade package. Another example is when the number of application program code areas is multiple, the multiple application program code areas can be respectively used to store different versions of the application program code. In this scenario, when the microprocessor jumps to the bootloader code area and performs hardware online upgrade by running the bootloader, it can download and verify the upgrade package of the new version of the application program, and store the new version of the application program code into the corresponding application program code area according to the upgrade package on the premise of avoiding overwriting the old version of the application program code. It should be understood that the above-mentioned hardware upgrade methods are only for illustration. During actual application, the hardware upgrade method can be specifically set and adjusted by relevant personnel according to the actual situation (for example, whether the storage space of the code memory supports, the reliability requirements of the system, and the hardware upgrade flexibility requirements of users, etc.). This application does not limit the specific hardware upgrade method.

[0037] Figure 1 Schematic diagram of the hardware online upgrade system according to an embodiment of the present invention. As Figure 1 shown, the hardware online upgrade system includes a code memory 11, a microprocessor 12, and an address remapping circuit 13.

[0038] Among them, the code memory 11 is a storage unit with the ability to store code data. In this embodiment, the internal storage area of the code memory 11 can be divided into a bootloader code area and at least one application code area. Optionally, the code memory 11 can be any type of non-volatile memory, such as flash memory, and the present application does not limit this. The microprocessor 12 is a processing unit with data processing capabilities. In this embodiment, the microprocessor 12 can run a corresponding program by executing the corresponding program code stored in the corresponding program code area in the code memory 11. For example, the microprocessor 12 can run the bootloader by executing the bootloader code stored in the bootloader code area. Again, for example, the microprocessor 12 can run the application by executing the application code stored in the application code area. Optionally, the microprocessor 12 can be a microprocessor that does not have the function of jumping between program code areas by itself, such as a microprocessor based on the Cortex-M0 kernel. The address remapping circuit 13 is disposed between the code memory 11 and the microprocessor 12. In this embodiment, the address remapping circuit 13 can be used to assist the microprocessor 12 in jumping between program code areas while reading the required code content from the code memory 11 for the microprocessor 12. Optionally, in this embodiment, the hardware online upgrade system may further include a bus 14. The address remapping circuit 13 can be connected to the code memory 11 through the bus 14 to achieve data interaction between each other.

[0039] It should be noted that, in this embodiment, the address remapping circuit 13 assisting the microprocessor 12 in jumping between program code areas specifically means that when the microprocessor wishes to perform a code area jump and actively triggers a system reset, the address remapping circuit 13 assists the microprocessor in jumping from the currently executing program code area to another program code area, or it means that when the microprocessor is affected by the system and a system interruption occurs, the address remapping circuit 13 assists the microprocessor in re-jumping to the program code area where it was executing before the system interruption occurred.

[0040] For the convenience of understanding, the following will take the address remapping circuit 13 assisting the microprocessor 12 in jumping to the target program code area as an example for illustration. It should be understood that the target program code area can be the bootloader code area or the application code area, and the present application does not limit this.

[0041] For the first case described above, the target program code area may specifically refer to the program code area that the microprocessor wishes to jump to. Specifically, when the microprocessor 12 needs to jump from the currently executing program code area to the target program code area, the microprocessor 12 can actively trigger a system reset. The system reset will reset the instruction address of the microprocessor 12 to point to the interrupt vector table of the initial program code area. When it is detected that the current instruction address of the microprocessor 12 points to the interrupt vector table of the initial program code area, the address remapping circuit 13 can perform an address offset on the current instruction address according to the target offset address, and read the target reset vector from the code memory 11 according to the offset instruction address. Furthermore, after obtaining the target reset vector, the microprocessor 12 can jump to the target program code area according to the target reset vector to execute the corresponding hardware in - line upgrade process by running the target program. Among them, the target offset address can be the storage address offset between the interrupt vector table of the target program code area and the interrupt vector table of the initial program code area.

[0042] For the second case described above, the target program code area may specifically refer to the program code area that the microprocessor was executing before the system interrupt occurred. Specifically, when the microprocessor is affected by the system and a system interrupt occurs, the system interrupt will also reset the instruction address of the microprocessor 12 to point to the interrupt vector table of the initial program code area. When it is detected that the current instruction address of the microprocessor 12 points to the interrupt vector table of the initial program code area, the address remapping circuit 13 can perform an address offset on the current instruction address according to the target offset address, and read the target reset vector from the code memory 11 according to the offset instruction address. Furthermore, after obtaining the target reset vector, the microprocessor 12 can jump to the target program code area according to the target reset vector to execute the corresponding hardware in - line upgrade process by running the target program. Among them, the target offset address can be the storage address offset between the interrupt vector table of the target program code area and the interrupt vector table of the initial program code area.

[0043] It should be understood that under normal circumstances, the storage address of the interrupt vector table of the initial program code area is usually the starting address of the code memory 11, that is, the address 0x00000000, and the interrupt vector table is usually located at the starting part of its corresponding code area. Therefore, the target offset address can also be understood as the starting address of the target program code area.

[0044] It should be understood that in this embodiment, when it is detected that the current instruction address of the microprocessor 12 does not point to the interrupt vector table of the initial program code area, the address remapping circuit 13 can directly read the required code content from the code memory 11 for the microprocessor 12 according to the current instruction address.

[0045] It should be noted that the initial program code area may refer to the program code area that the microprocessor 12 defaults to enter after a system exception occurs (i.e., including system reset actively triggered by the microprocessor and system interrupts caused by the microprocessor being affected by the system) and is restored. In the prior art, due to the lack of the ability to jump between program code areas, the microprocessor will enter this initial program code area every time a system exception occurs and is restored, which also causes the microprocessor in the prior art to be unable to run a multi-program code area storage architecture. Compared with the prior art, by setting up the address remapping circuit 13 to assist the microprocessor 12 in jumping between program code areas, the embodiments of the present invention can enable the microprocessor to achieve program code area jumping on the premise that it does not have the ability to jump between program code areas by itself, thereby supporting the deployment and operation of a multi-program code area storage architecture, and further supporting hardware online upgrade.

[0046] Figure 2 FIG. is a schematic diagram of the code memory according to an embodiment of the present invention. As Figure 2 shown, the code memory 21 is set to include a bootloader code area 211 and an application program code area 212 (here, for the convenience of distinction, Figure 2 the bootloader code area 211 is marked by using the shaded covering method). It should be understood that although Figure 2 only a certain number of application program code areas are shown, it does not mean restricting the number of application program code areas set. For example, when the storage space permits, the code memory can also be set to include multiple application program code areas. At the same time, in the Figure 2 code memory, the initial program code area is set at the starting part of the code memory 21, that is, the initial program code area is set as the bootloader code area 211, but in actual application, the initial program code area can also be set as the corresponding application program code area, and the present application does not limit this. Among them, the bootloader code area 211 and the application program code area 212 can be respectively used to store the program code of the corresponding program. Further, each program code area can include its own interrupt vector table (as shown by the interrupt vector table 2111 of the bootloader code area 211 and the interrupt vector table 2121 of the application program code area 212). This interrupt vector table can be used to store the reset vector. The reset vector can be used to indicate the code execution address of the microprocessor after recovery.

[0047] Optionally, for the convenience of further understanding the operation logic of the multi-program code area storage architecture when the system is powered on and during the hardware online upgrade process, here, the Figure 2 code memory in is taken as an example for description.

[0048] Specifically, when the system is powered on, the microprocessor can first jump to the bootloader code area 211 and initialize the relevant hardware by running the bootloader. Furthermore, the microprocessor can jump to the application code area 212 and execute the corresponding business logic by running the application, thereby providing services or functions externally. Thus, the microprocessor can operate in a normal working state after the system is powered on based on the multi-program code area storage architecture.

[0049] During hardware over-the-air (OTA) upgrade, the instructions executed by the microprocessor need to jump between different program code areas. As the first scenario: when the device is powered on, the bootloader starts and completes hardware initialization. When it detects a need for FOTA update, the microprocessor will cause the bootloader to establish a connection with the server, download the upgrade package of the new version application to the storage area of the old version application code, and then verify the integrity and legality of the new version upgrade package. After the verification passes, the execution instructions of the microprocessor can jump from the bootloader code area 211 to the application code area 212 to run the new version of the application. As the second scenario: when the microprocessor is running a program in the application code area and wants to upgrade the code in the application code area (FOTA), the microprocessor can first run the old version application in the application code area 212 to confirm before the update. When the update confirmation is completed, the microprocessor can jump to the bootloader code area 211, cause the bootloader to establish a connection with the server, download the upgrade package of the new version application to the storage area of the old version application code, and then verify the integrity and legality of the new version upgrade package. After the verification passes, the microprocessor can jump to the application code area 212 and perform post-update confirmation by running the new version application. Thus, the microprocessor can complete the hardware OTA upgrade process based on the multi-program code area storage architecture.

[0050] It should be understood that the above-described operation logics of the multi-program code area storage architecture when the system is powered on and during the hardware OTA upgrade process are only for illustrating the functions that the multi-program code area storage architecture can play when the system is powered on and during the hardware OTA upgrade process. In the actual application process, the operation logics of the multi-program code area storage architecture when the system is powered on and during the hardware OTA upgrade process can be specifically set and adjusted by relevant personnel, and this application does not limit this.

[0051] Figure 3The flowchart of the address remapping method according to the embodiment of the present invention is shown. It should be understood that the execution subject of the address remapping method may be the address remapping circuit in the above embodiment. The address remapping circuit may implement the address remapping method in a hardware or software or a combination of hardware and software manner. By implementing the address remapping method, the address remapping circuit can assist the microprocessor in performing a program code area jump. As Figure 3 shown, the address remapping method may specifically include the following steps:

[0052] Step S100, determine whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area.

[0053] Specifically, whether it is actively triggering a system reset or a system interrupt occurs, the microprocessor will generate a corresponding instruction address according to the interrupt number after recovery. However, due to the lack of code jump ability, the instruction address generated by the microprocessor usually only points to the interrupt vector table of the initial program code area, rather than the interrupt vector table of the target program code area. For example, whether the target program code area is program code area A or program code area B, the microprocessor will only generate an instruction address that points to the interrupt vector table of the initial program code area according to the interrupt number. In this embodiment, in order to ensure that the microprocessor can correctly jump to the target program code area after recovery, it is necessary to perform an address offset on the instruction address generated by the microprocessor after recovery. In this step, this embodiment can continuously determine whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area to confirm whether it is necessary to perform an address offset on the current instruction address. Among them, the target program code area may be the code area that the microprocessor needs to jump to. Optionally, the target program code area may be a bootloader code area or an application program code area, and the present application does not limit this. It should be understood that when the microprocessor actively triggers a system reset due to the desire to perform a code area jump, the target program code area may specifically refer to the program code area that the microprocessor hopes to jump to. When the microprocessor has a system interrupt due to being affected by the system, the target program code area may specifically refer to the program code area that the microprocessor was executing before the system interrupt occurred.

[0054] Optionally, in step S100, as an implementation, in this embodiment, the current instruction address can be compared with a preset address range to determine whether the current instruction address points to the interrupt vector table in the initial program code area. The preset address range can be used to represent the memory size of the interrupt vector table in the initial program code area. Specifically, under normal circumstances, the starting address of the interrupt vector table in the initial program code area is usually the starting address of the code memory, that is, the address 0x00000000. On this premise, after setting the memory size of the interrupt vector table in each program code area to be equal to the memory size of the interrupt vector table in the initial program code area, in this embodiment, when it is detected that the current instruction address is less than or equal to the preset address range, it can be confirmed that the current instruction address points to the interrupt vector table in the initial program code area. And, in this embodiment, when it is detected that the current instruction address is greater than the preset address range, it can be confirmed that the current instruction address does not point to the interrupt vector table in the initial program code area. It should be noted that in this embodiment, it is only necessary to ensure that the memory size of the interrupt vector table in each program code area is the same as that of the interrupt vector table in the initial program code area, and the specific reset vector content stored in each program code area is not restricted. That is, the specific reset vector content stored in each program code area can be the same or different.

[0055] Step S200, in response to the current instruction address pointing to the interrupt vector table in the initial program code area, perform an address offset on the current instruction address according to the target offset address.

[0056] Specifically, when it is determined that the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area, in this embodiment, it can be confirmed that an address offset needs to be performed on the current instruction address. Furthermore, in this embodiment, the current instruction address can be offset according to the target offset address. It should be understood that under normal circumstances, the storage address of the interrupt vector table in the initial program code area is usually the starting address of the code memory, that is, the address 0x00000000, and the interrupt vector table is usually located at the starting part of its corresponding code area. Therefore, the target offset address can also be understood as the starting address of the target program code area.

[0057] Optionally, before performing an address offset on the current instruction address according to the target offset address in this embodiment, the first offset value or the second offset value can be selected as the target offset address for output according to the condition value, so as to obtain the target offset address.

[0058] Further, the condition value may include a first numerical value. The condition value may be reset to the first numerical value when a system exception occurs. The first numerical value may be used to indicate selecting a first offset value as the target offset address for output. The first offset value may be set to the starting address of the target program code area before the system exception occurs, and the first offset value may not be affected by the system exception. Specifically, before the system exception occurs, in this embodiment, the first offset value may be set to the starting address of the target program code area under the instruction of the microprocessor. When a system exception occurs, the condition value is reset to the first numerical value. In this embodiment, the first offset value, that is, the starting address of the target program code area set in advance, may be selected as the target offset address for output according to the first numerical value. Furthermore, in this embodiment, the current instruction address may be offset according to the target offset address.

[0059] Further optionally, when implementing the above process in a hardware manner, the condition value may be set to the numerical value stored in a condition register. The condition register may be a register whose internal stored numerical value can be read and modified and whose internal stored numerical value can be reset after a system exception occurs. More specifically, the condition register may be set to reset the internal stored numerical value to the first numerical value after a system exception occurs. The first offset value may be set to the numerical value stored in a first address register. The first address register may be a register whose internal stored numerical value can be read and modified and whose internal stored numerical value is not affected by the system exception.

[0060] It should be understood that in this embodiment, the system exception may specifically refer to a system reset actively triggered by the microprocessor, or a system interruption that occurs when the microprocessor is affected by the system, but does not include system power-on.

[0061] Further, the condition value may further include a second numerical value. The condition value may be set to the second numerical value when no system exception occurs. The second numerical value may be used to indicate selecting a second offset value as the target offset address for output. The second offset value may be set to the starting address of the code area currently being run by the microprocessor when no system exception occurs, and the second offset value may be reset to the initial address when a system exception occurs. Specifically, after the microprocessor resumes, in this embodiment, the second offset value may be set to the starting address of the code area currently being run by the microprocessor under the instruction of the microprocessor. And, in this embodiment, the condition value may be set to the second numerical value under the instruction of the microprocessor. Furthermore, in this embodiment, the second offset value, that is, the starting address of the code area currently being run by the microprocessor, may be selected as the target offset address for output according to the second numerical value. Thus, in this embodiment, while not affecting the microprocessor's normal access to data in the interrupt vector table, it is possible to avoid timing chaos.

[0062] Further optionally, when the above process is implemented in a hardware manner, the second offset value may be set to the value stored in the second address register. The second address register may be a register that stores internal values for reading and modification and can reset the internal stored values after a system exception or system power-on.

[0063] Further, when the system is powered on, the microprocessor generally needs to first jump to the bootloader code area and initialize the relevant hardware by running the bootloader, and then jump to the application code area to provide services to the user by running the application. Among them, when the initial program code area is set to the bootloader code area, in order to enable the microprocessor to first jump to the initial program code area after the system is powered on, the first offset value may be reset to 0x00000000, that is, the starting address of the initial program code area, when the system is powered on, and the condition value may be reset to the first value when the system is powered on.

[0064] Further optionally, when the above process is implemented in a hardware manner, the first address register also needs to be able to reset the internal stored value after the system is powered on. More specifically, the first address register may be set to reset the internal stored value to 0x00000000, that is, the starting address of the initial program code area, after the system is powered on. The condition register also needs to be able to reset the internal stored value after the system is powered on. More specifically, the first address register may be set to reset the internal stored value to the first value after the system is powered on.

[0065] Further, in order to ensure that after a system interrupt occurs, the microprocessor can correctly jump to the program code area it was executing before the system interrupt occurred, in this embodiment, it can be set so that the first offset value remains unchanged when no system reset occurs, that is, the first offset value is maintained as the starting address of the code area where the microprocessor is currently running when the microprocessor does not actively trigger a reset. Thus, when the microprocessor is interrupted by the system, the condition value is reset to the first value, and in this embodiment, the first offset value, that is, the starting address of the program code area where the microprocessor was executing before the system interrupt occurred, can be selected as the target offset address for output according to the first value. Furthermore, in this embodiment, the current instruction address can be offset according to the target offset address.

[0066] Step S300, read the target reset vector from the code memory according to the offset instruction address.

[0067] Specifically, after performing an address offset on the current instruction address, in this embodiment, the target reset vector can be read from the code memory according to the offset instruction address, and the target reset vector is sent to the microprocessor, so that the microprocessor jumps to the target program code area according to the target reset vector.

[0068] Figure 4 It is the circuit diagram of the offset address output circuit according to the embodiment of the present invention. It should be understood that Figure 4 The offset address output circuit shown can be a hardware circuit for implementing the above-mentioned target offset address determination process. As Figure 4 shown, the offset address output circuit includes a first address register 41, a second address register 42, a condition register 43, and a selector 44.

[0069] Among them, the first address register 41 is a register for storing a first offset value. Specifically, the first address register 41 can be a register whose internal stored value can be read and modified, and the internal stored value is not affected by system exceptions, but the internal stored value can be reset after the system is powered on. The second address register 42 is a register for storing a second offset value. Specifically, the second address register 42 can be a register whose internal stored value can be read and modified, and the internal stored value can be reset when a system exception occurs and when the system is powered on. The condition register 43 is a register for storing a condition value. Specifically, the condition register 43 can be a register whose internal stored value can be read and modified, and the internal stored value can be reset when a system exception occurs and when the system is powered on. The selector 44 can be used to select the first offset value stored in the first address register 41 or the second offset value stored in the second address register 42 as the target offset address for output according to the condition value stored in the condition register 43.

[0070] Specifically, before a system exception occurs, the value stored in the first address register 41 can be first modified by the microprocessor to the start address of the target program code area. When a system exception occurs, the condition register 43 can reset the internal stored value to a first value. The selector 44 can select the first offset value stored in the first address register 41 as the target offset address for output according to the first value. Thus, this embodiment can ensure that the microprocessor can jump to the target program code area after a system exception occurs and is restored.

[0071] Further, when no system exception occurs, the value stored in the second address register 42 can be modified by the microprocessor to the starting address of the code region where it is currently running. The value stored in the condition register 43 can be modified by the microprocessor to a second value. The selector 44 can select, according to the second value, the second offset value stored in the second address register 42 as the target offset address for output. Thus, this embodiment can avoid timing chaos while not affecting the microprocessor's normal access to the data in the interrupt vector table.

[0072] Further, when the system is powered on, the first address register 41 can reset the value stored internally to the starting address of the initial program code region, and the condition register 43 can reset the value stored internally to the first value. The selector 44 can select, according to the first value, the first offset value stored in the first address register 41 as the target offset address for output. Thus, this embodiment can ensure that when the initial program code region is the bootloader code region, the microprocessor can first jump to the bootloader code region after power-on, so as to initialize the relevant hardware by running the bootloader.

[0073] It should be understood that in this embodiment, the value stored internally in the first address register 41 can also be set to be maintained as the starting address of the code region where the microprocessor is currently running when no system reset occurs, that is, when the microprocessor does not actively trigger a reset. Thus, this embodiment can ensure that after a system interrupt occurs, the microprocessor can correctly jump to the program code region where it was executing before the system interrupt occurred.

[0074] Figure 5 is a schematic diagram of the address remapping circuit according to an embodiment of the present invention. As Figure 5 shown, the address remapping circuit 51 includes a logic judgment circuit 511, an address offset circuit 512, and a reading circuit 513.

[0075] Among them, the logic judgment circuit 511 can be used to judge whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code region.

[0076] Optionally, in this embodiment, as an implementation manner, the logic judgment circuit may compare the current instruction address with a preset address range to determine whether the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area. Among them, the preset address range can be used to represent the memory size of the interrupt vector table in the initial program code area. Specifically, when it is detected that the current instruction address is less than or equal to the preset address range, the logic judgment circuit 511 can confirm that the current instruction address points to the interrupt vector table in the initial program code area. When it is detected that the current instruction address is greater than the preset address range, the logic judgment circuit 51 can confirm that the current instruction address does not point to the interrupt vector table in the initial program code area.

[0077] The address offset circuit 512 can be used to, in response to the current instruction address pointing to the interrupt vector table in the initial program code area, perform an address offset on the current instruction address according to the target offset address. Among them, the target offset address is the starting address of the target program code area.

[0078] The reading circuit 513 can be used to read the target reset vector from the code memory according to the offset instruction address.

[0079] Furthermore, the address remapping circuit in this embodiment may further include an offset address output circuit. The offset address output circuit can be used to select a first offset value or a second offset value as the target offset address for output according to a condition value.

[0080] Furthermore, the condition value may include a first value. The condition value can be reset to the first value when a system exception occurs. The first value can be used to indicate selecting the first offset value as the target offset address for output. The first offset value can be set as the starting address of the target program code area before a system exception occurs, and the first offset value is not affected by the system exception.

[0081] Furthermore, the condition value may further include a second value. The condition value can be set to the second value when no system exception occurs. The second value can be used to indicate selecting the second offset value as the target offset address for output. The second offset value can be set as the starting address of the code area currently running by the microprocessor when no system exception occurs, and the second offset value can be reset to the initial address when a system exception occurs.

[0082] Furthermore, when the initial program code area is set as the bootloader code area, in order to enable the microprocessor to jump to the initial program code area first when the system is powered on, the first offset value can be reset to the starting address of the initial program code area when the system is powered on.

[0083] Further, to ensure that after a system interruption occurs, the microprocessor can correctly jump to the program code area where it was executing before the system interruption occurred, the first offset value can remain unchanged when a system reset does not occur (i.e., when the microprocessor does not actively trigger a reset).

[0084] Figure 6 The flowchart of the hardware online upgrade method according to an embodiment of the present invention is shown. It should be understood that the execution subject of the address remapping method may be the hardware upgrade system in the above embodiment. More specifically, each step in the hardware online upgrade method may be executed by the microprocessor and the address remapping circuit in the hardware upgrade system. As Figure 6 shown, the hardware online upgrade method may specifically include the following steps:

[0085] Step S100': Set the first offset value to the starting address of the target program code area.

[0086] Specifically, when it is necessary to jump from the currently executing program code area to the target program code area, the microprocessor may first set the first offset value of the address remapping circuit to the starting address of the target program code area.

[0087] Optionally, before setting the first offset value to the starting address of the target program code area, the microprocessor may first perform a security verification, and then set the first offset value to the starting address of the target program code area when it detects that the security verification passes.

[0088] Optionally, before setting the first offset value to the starting address of the target program code area, the microprocessor may also turn off other interrupts except for the non-maskable interrupt and the hard fault interrupt to ensure the stability of code execution during the process of jumping the instruction address to the target program code area.

[0089] Step S200': Initiate a system reset.

[0090] Specifically, after setting the first offset value to the starting address of the target program code area, the microprocessor may initiate a system reset. During the system reset process, the current instruction address is configured to point to the interrupt vector table of the initial program code area, and the condition value is reset to a first value. The first value is used to indicate that the first offset value is selected as the target offset address for output.

[0091] Step S300': In response to the current instruction address pointing to the interrupt vector table of the initial program code area, perform an address offset on the current instruction address according to the target offset address.

[0092] Specifically, when the address remapping circuit detects that the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area, it can offset the current instruction address according to the target offset address.

[0093] Step S400': Read the target reset vector from the code memory according to the offset instruction address.

[0094] Specifically, after offsetting the current instruction address, the address remapping circuit can read the target reset vector from the code memory according to the offset instruction address.

[0095] Step S500': Jump to the target program code area according to the target reset vector to execute the hardware online upgrade process.

[0096] Specifically, after the address remapping circuit reads the target reset vector, the microprocessor can jump to the target program code area according to the target reset vector to execute the hardware online upgrade process.

[0097] Optionally, before step S100', when no system exception occurs, the microprocessor can also assign the first offset value to the second offset value and update the condition value to the second numerical value. The first offset value is maintained as the starting address of the program code area where the microprocessor is currently executing when the microprocessor does not actively trigger a reset. That is, it is equivalent to the microprocessor setting the second offset value to the starting address of the program code area where the microprocessor is currently executing. The second numerical value can be used to indicate that the address remapping circuit selects the second offset value as the target offset address for output. Thus, this embodiment can avoid timing chaos while not affecting the microprocessor's normal access to the data in the interrupt vector table.

[0098] Optionally, when a system interrupt occurs, the current instruction address is also configured to point to the interrupt vector table in the initial program code area. In this scenario, the address remapping circuit can also offset the current instruction address according to the target offset address when it detects that the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area, so that the current instruction address jumps to the target program code area. It should be understood that when a system interrupt occurs, the target program code area is the code area that was running before the system interrupt occurred, and the target offset address is the starting address of the code area where the target program code area is running.

[0099] Taking the FOTA architecture with the total size of the code memory being 128 KB, the bootloader code area being divided into 32 KB, the starting address of the bootloader code area being set to 0x00000000, the application code area being divided into 96 KB, and the starting address of the application code area being set to 0x00008000 as an example, the process of FOTA and the jump of instructions between the bootloader code area and the application code area will be described.

[0100] When the system is powered on, both the first offset value and the second offset value are reset and set to the starting address of the bootloader code area, that is, 0x00000000. It should be noted that since the initial program code area is set to the bootloader code area, it can also be understood here that both the first offset value and the second offset value are reset and set to the starting address of the initial program code area, that is, 0x00000000. Also, the condition register resets the internally stored value to the first value, and the selector selects the first offset value stored in the first address register as the target offset address for output according to the first value. At this time, the current instruction address of the microprocessor will point to the interrupt vector table of the initial program code area (that is, the bootloader code area) before and after the offset. Thus, the instructions of the microprocessor can be executed in the loader code area to start the bootloader code area and perform hardware initialization.

[0101] When a FOTA update requirement is detected, the bootloader code area will establish a connection with the server, download the new firmware to the application code area, and then verify the integrity and legality of the new firmware. After the verification passes, it is necessary to jump from the bootloader code to the application code area. The jump process is as follows:

[0102] Disable other interrupts except non-maskable interrupt and hard fault interrupt to ensure the stability of code execution during the jump of the instruction address to the target program code area;

[0103] Assign the first offset value to the second offset value. Since the first offset value is 0x00000000, the second offset value is 0x00000000, and update the condition value to the second value, so as to select the second offset value as the target offset address for output according to the second value, and the current instruction address continues to point to the initial program code area, so that the program continues to run normally in the loader code area;

[0104] Set the first offset value to the starting address of the target program code area. At this time, the target program code area is the application code area, so set the first offset value to 0x00008000;

[0105] Initiate a system reset; during the system reset process, the current instruction address is configured to point to the interrupt vector table in the initial program code area, the condition value is reset to a first value, the first value is used to indicate selecting the first offset value 0x00008000 as the target offset address for output, and the current instruction address starts to point to the interrupt vector table in the application code area, so that the program runs in the application code area.

[0106] When the instruction runs in the application code area, if a system interrupt occurs, the condition value is reset to the first value, and the current instruction address is set to point to the interrupt vector table in the initial program code area (at this time, the bootloader code area); in response to the current instruction address pointing to the interrupt vector table in the initial program code area, the current instruction address is offset according to the target offset address; the first value is used to indicate selecting the first offset value 0x00008000 as the target offset address for output, so that the current instruction address is offset according to the first offset value 0x00008000, and the program continues to run the application code area before the interruption.

[0107] When the instruction runs in the application code area, if it is desired to upgrade the code in the application code area (FOTA), after completing the upgrade confirmation in the application (such as authenticating the identity of the Host initiating the upgrade), then jump to the loader code area, and the execution of the upgrade process jump is as follows:

[0108] Disable other interrupts except non-maskable interrupts and hard fault interrupts to ensure the stability of code execution during the jump of the instruction address to the target program code area;

[0109] Assign the first offset value to the second offset value. Since the first offset value is only reset when the system is powered on, the first offset value remains 0x00008000. After the assignment, the second offset value remains 0x00008000; and update the condition value to the second value, so that the second offset value 0x00008000 is selected as the target offset address for output according to the second value, and the current instruction address continues to point to the application code area, so that the program continues to run normally in the application code area;

[0110] Set the first offset value to the starting address of the target program code area. At this time, the target program code area is the loader program code area, so set the first offset value to 0x00000000; initiate a system reset. During the system reset process, the current instruction address is configured to point to the interrupt vector table of the initial program code area, and the condition value is reset to a first value. The first value is used to indicate selecting the first offset value 0x00000000 as the target offset address for output. The current instruction address starts to point to the interrupt vector table of the bootloader program code area, so that the program runs in the loader program code area.

[0111] When the instruction is running in the bootloader program code area, if a system interrupt occurs, the condition value is reset to the first value, and the current instruction address is set to point to the interrupt vector table of the initial program code area (which is the bootloader program code area at this time); in response to the current instruction address pointing to the interrupt vector table of the initial program code area, perform an address offset on the current instruction address according to the target offset address; the first value is used to indicate selecting the first offset value 0x00000000 as the target offset address for output, so that the current instruction address is offset according to the first offset value 0x00000000, that is, the current instruction address is not offset, and the program continues to run in the bootloader program code area before the interrupt occurred.

[0112] The address remapping circuit in the embodiments of the present invention is used to detect whether the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area, and when it is detected that the current instruction address of the microprocessor points to the interrupt vector table of the initial program code area, perform an address offset on the current instruction address according to the target offset address, and read the target reset vector from the code memory according to the offset instruction address. The target offset address is the starting address of the target program code area. Thus, by setting up the address remapping circuit to assist the microprocessor in performing program code area jumps, the embodiments of the present invention can enable the microprocessor to achieve program code area jumps without having the ability to perform program code area jumps itself, thereby supporting the deployment and operation of a multi-program code area storage architecture, and further supporting hardware online upgrade.

[0113] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. An address remapping circuit, characterized in that, The address remapping circuit includes: A logic judgment circuit, configured to judge whether the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area; An address offset circuit, configured to, in response to the current instruction address pointing to the interrupt vector table in the initial program code area, perform address offset on the current instruction address according to a target offset address, where the target offset address is the starting address of a target program code area; A reading circuit, configured to read a target reset vector from a code memory according to the offset instruction address.

2. The circuit according to claim 1, wherein The logic judgment circuit is specifically configured to compare the current instruction address with a preset address range to judge whether the current instruction address points to the interrupt vector table in the initial program code area, and the preset address range is used to represent the memory size of the interrupt vector table in the initial program code area.

3. The circuit according to claim 1, wherein The address remapping circuit is arranged between the microprocessor and the code memory, and the code memory includes a plurality of program code areas, and each program code area includes its own interrupt vector table.

4. The circuit according to claim 3, wherein The address remapping circuit further includes: An offset address output circuit, configured to select a first offset value or a second offset value as the target offset address for output according to a condition value, where the condition value includes a first value, and the condition value is reset to the first value when a system exception occurs, and the first value is used to indicate selecting the first offset value as the target offset address for output.

5. The circuit according to claim 4, wherein Before the system exception occurs, the first offset value is set to the starting address of the target program code area, and the first offset value is not affected by the system exception, and the system exception includes a system interrupt and / or a system reset.

6. The circuit according to claim 4, characterized in that, The condition value further includes a second value, and the condition value is set to the second value when the system exception does not occur, and the second value is used to indicate selecting the second offset value as the target offset address for output.

7. The circuit according to claim 6, characterized in that, Before the system exception occurs, the second offset value is set to the starting address of the code area currently running by the microprocessor, and the second offset value is reset to an initial address when a system exception occurs.

8. The circuit according to claim 5, wherein When the system is powered on, the first offset value is reset to the starting address of the initial program code area.

9. The circuit according to claim 5, wherein When the system reset does not occur, the first offset value remains unchanged.

10. An address remapping method, applicable to an address remapping circuit, characterized in that, The method includes: Judging whether the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area; In response to the current instruction address pointing to the interrupt vector table in the initial program code area, performing address offset on the current instruction address according to a target offset address, where the target offset address is the starting address of a target program code area; Reading a target reset vector from a code memory according to the offset instruction address.

11. The method according to claim 10, wherein The judging whether the current instruction address of the microprocessor points to the interrupt vector table in the initial program code area includes: Compare the current instruction address with a preset address range to determine whether the current instruction address points to the interrupt vector table of the initial program code area, where the preset address range is used to represent the memory size of the interrupt vector table of the initial program code area.

12. The method according to claim 10, wherein The address remapping circuit is arranged between the microprocessor and the code memory, and the code memory includes multiple program code areas, and each program code area includes its own interrupt vector table.

13. The method according to claim 12, wherein The method further includes: Select a first offset value or a second offset value as the target offset address for output according to a condition value, where the condition value includes a first value, and the condition value is reset to the first value when a system exception occurs, and the first value is used to indicate selecting the first offset value as the target offset address for output.

14. The method according to claim 13, wherein The first offset value is set as the starting address of the target program code area before the system exception occurs, and the first offset value is not affected by the system exception, and the system exception includes a system interrupt and / or a system reset.

15. The method according to claim 13, wherein The condition value further includes a second value, and the condition value is set to the second value when the system exception does not occur, and the second value is used to indicate selecting the second offset value as the target offset address for output.

16. The method according to claim 15, wherein The second offset value is set as the starting address of the code area currently run by the microprocessor when the system exception does not occur, and the second offset value is reset to the initial address when the system exception occurs.

17. The method according to claim 14, wherein The first offset value is reset to the starting address of the initial program code area when the system is powered on.

18. The method according to claim 14, wherein The first offset value remains unchanged when the system reset does not occur.

19. A hardware online upgrade method, characterized in that, The method includes: Set a first offset value as the starting address of the target program code area; Initiate a system reset, where during the system reset process, the current instruction address is configured to point to the interrupt vector table of the initial program code area, and the condition value is reset to the first value; the first value is used to indicate selecting the first offset value as the target offset address for output; In response to the current instruction address pointing to the interrupt vector table of the initial program code area, perform an address offset on the current instruction address according to the target offset address; Read a target reset vector from the code memory according to the offset instruction address; Jump to the target program code area according to the target reset vector to execute the hardware online upgrade process.

20. The online upgrade method according to claim 19, characterized in that, The method further includes: When a system interrupt occurs, the current instruction address is configured to point to the interrupt vector table of the initial program code area. In response to the current instruction address pointing to the interrupt vector table of the initial program code area, perform an address offset on the current instruction address according to the target offset address, so that the current instruction address jumps to the target program code area; Wherein, when a system interrupt occurs, the target program code area is the code area run before the system interrupt occurs; the target offset address is the starting address of the code area where the target program code area runs.

21. The online upgrade method according to claim 19, characterized in that, Before setting the first offset value to the starting address of the target program code area, the method further includes: Performing security verification; In response to detecting that the security verification passes, setting the first offset value to the starting address of the target program code area.

22. The online upgrade method according to claim 19, wherein, Before setting the first offset value to the starting address of the target program code area, the method further includes: Turning off other interrupts except the non-maskable interrupt and the hard fault interrupt to ensure the stability of code execution during the instruction address jump to the target program code area.

23. The online upgrade method according to claim 19, wherein When the system exception does not occur, the method further includes: Assigning the first offset value to the second offset value; Updating the condition value to a second numerical value; Wherein, the second numerical value is used to indicate that the second offset value is selected as the target offset address for output.

24. A hardware online upgrade system, characterized in that, The system includes: A code memory; A microprocessor; and An address remapping circuit as claimed in any one of claims 1-9.

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