Link anomaly detection method and computing device

Abstract

The embodiment of the invention provides a link anomaly detection method and computing equipment. The method is applied to a baseboard management controller in computing equipment, and comprises the following steps: acquiring a target PCIe link topology tree; the target PCIe link topology tree comprises a plurality of PCIe ports and a link connection relationship among the plurality of PCIe ports; each PCIe port is associated with respective device address information and respective component information; for a first PCIe port in the plurality of PCIe ports, determining actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port; when the actual PCIe link data of the first PCIe port is not matched with the expected PCIe link data of the first PCIe port, determining that a first link where the first PCIe port is located is abnormal; and reporting a link anomaly based on the component information associated with the PCIe ports at the two ends of the first link. According to the method provided by the embodiment of the invention, the link anomaly detection efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of computing devices, and in particular, to a method for detecting link anomalies and a computing device. Background Art

[0002] With the continuous iteration of the Peripheral Component Interconnect Express (PCIe) technology, while the transmission speed of the PCIe link has been significantly improved, higher requirements are put forward for signal quality. Therefore, it is crucial to accurately detect link anomalies.

[0003] In the related art, it is necessary to rely on the Basic Input Output System (BIOS) chip to determine the slot number and device address information corresponding to the endpoint (EP) component, establish the correspondence between the slot number and the device address information, and report the correspondence to the Baseboard Management Controller (BMC). When a PCIe link fails (such as the link failure between the central processing unit and the PCIe switch), the BMC can detect that a certain endpoint (EP) component reports an abnormal state, and based on the correspondence, determine the corresponding target slot number. Maintenance personnel need to manually detect link anomalies based on the target slot number and the actual connection situation of the PCIe link.

[0004] However, the method in the related art has the problem of low detection efficiency of link anomalies. Summary of the Invention

[0005] Embodiments of this application provide a method for detecting link anomalies and a computing device, which can improve the detection efficiency of link anomalies.

[0006] In a first aspect, embodiments of this application provide a method for detecting link anomalies, which is applied to a baseboard management controller in a computing device. The method includes:

[0007] Obtain a target PCIe link topology tree; the target PCIe link topology tree includes multiple PCIe ports and the link connection relationships between the multiple PCIe ports; each PCIe port is associated with its own device address information and its own component information;

[0008] For a first PCIe port among the multiple PCIe ports, determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port;

[0009] When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, determine that the first link where the first PCIe port is located is abnormal;

[0010] Report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link.

[0011] In this solution, the baseboard management controller of the computing device can obtain the target PCIe link topology tree; the target PCIe link topology tree includes multiple PCIe ports and the link connection relationships between multiple PCIe ports; each PCIe port is associated with its own device address information and its own component information. For the first PCIe port among the multiple PCIe ports, the baseboard management controller can determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port. When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, the baseboard management controller can determine that the first link where the first PCIe port is located is abnormal, and report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link. On the one hand, the method of the embodiment of the present application can directly and accurately determine the component information of the PCIe ports at both ends of the abnormal link, that is, locate the components at both ends of the abnormal link, improving the detection efficiency and accuracy of link abnormalities. On the other hand, the method of the embodiment of the present application does not require the baseboard management controller to interact with the BIOS chip. The baseboard management controller can directly obtain the target PCIe link topology tree that records the device address information and component information of the PCIe ports, and then detect link abnormalities based on the device address information and component information of the PCIe ports, realizing the decoupling of the baseboard management controller and the BIOS, and improving the performance of the baseboard management controller.

[0012] In one implementation, the method further includes:

[0013] Obtain the device address information tree; the device address information tree includes multiple PCIe ports and the link connection relationships between multiple PCIe ports; each PCIe port is associated with its own device address information;

[0014] Obtain the component information tree; the component information tree includes multiple PCIe ports and the link connection relationships between multiple PCIe ports; each PCIe port is associated with its own component information;

[0015] Determine the target PCIe link topology tree based on the device address information tree and the component information tree.

[0016] In this solution, the baseboard management controller can obtain the device address information tree and the component information tree, and determine the target PCIe link topology tree based on the device address information tree and the component information tree. In this way, without relying on the BIOS chip, the baseboard management controller can quickly construct the target PCIe link topology tree in the baseboard management controller, so that the baseboard management controller can monitor the link status based on the target PCIe link topology tree. When it is identified that the actual PCIe link data of the PCIe port on the target PCIe link topology tree does not match the expected PCIe link data, it is determined that the first link where the first PCIe port is located is abnormal, and then based on the component information associated with the PCIe ports at both ends of the first link, the link abnormality is reported. In this way, the detection efficiency and accuracy of link abnormalities are improved.

[0017] In one implementation, obtaining the device address information tree includes:

[0018] Obtain the bus information of the root port;

[0019] According to the bus information of the root port, obtain the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports;

[0020] Construct a device address information tree according to the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports.

[0021] In this solution, the baseboard management controller can obtain the bus information of the root port, and according to the bus information of the root port, obtain the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports. The baseboard management controller can construct a device address information tree according to the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports. In this way, the baseboard management controller can use the dynamic scanning mechanism to quickly construct the device address information tree, improve the construction rate of the device address information tree, and then improve the construction rate of the target PCIe link topology tree.

[0022] In one implementation, according to the bus information of the root port, obtaining the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports includes:

[0023] For any first PCIe port, obtain the device type according to the device address information of the first PCIe port; the device address information of the first PCIe port is determined according to the bus information of the root port, or the device address information of the first PCIe port is determined according to the next-level bus information corresponding to the device address information of the third PCIe port;

[0024] When the device type is the target device type, obtain the next-level bus information corresponding to the device address information of the first PCIe port;

[0025] Determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port;

[0026] Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0027] In this solution, for any first PCIe port, the baseboard management controller can obtain the device type according to the device address information of the first PCIe port. When the device type is the target device type, the baseboard management controller can obtain the next-level bus information corresponding to the device address information of the first PCIe port. The baseboard management controller can determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port, and determine that there is a link connection relationship between the first PCIe port and the second PCIe port. In the above manner, the baseboard management controller can obtain the device address information of each PCIe port and the link connection relationship between PCIe ports without relying on the BIOS, improving the acquisition efficiency of the device address information of PCIe ports and the link connection relationship between PCIe ports, thereby improving the construction rate of the device address information tree and further improving the construction rate of the target PCIe link topology tree.

[0028] In one implementation, the target device type is the PCIe port or the root port of a bridging device.

[0029] In this solution, the target device type can be the PCIe port or the root port of a bridging device. When the device type of the first PCIe port is the PCIe port or the root port of a bridging device, the baseboard management controller can further obtain the next-level bus information to use the next-level bus information to determine the device address information of the second PCIe port. The accuracy and efficiency of determining the downstream PCIe port (the second PCIe port) of the first PCIe port are improved.

[0030] In one implementation, obtaining the component information tree includes:

[0031] Obtain the configuration files of multiple components; the configuration file includes the component information of at least one PCIe port, or the configuration file includes the component information of at least one PCIe port and the component information of the downstream ports of the PCIe port;

[0032] Obtain the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components;

[0033] Construct a component information tree according to the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports.

[0034] In this solution, the baseboard management controller can obtain the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components, and construct a component information tree according to the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports. In the above way, without relying on the BIOS chip, the baseboard management controller can quickly construct a component information tree, improving the construction rate and accuracy of the component information tree, and further improving the construction rate and accuracy of the target PCIe link topology tree, and improving the performance of the baseboard management controller.

[0035] In one implementation, obtaining the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components includes:

[0036] For any first PCIe port, when the configuration file includes the component information of the first PCIe port and the component information of the downstream port of the first PCIe port, according to the component information of the downstream port of the first PCIe port, search multiple configuration files to determine the component information of the second PCIe port; the component information of the second PCIe port matches the component information of the downstream port of the first PCIe port;

[0037] Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0038] In this solution, for any first PCIe port, when the configuration file includes the component information of the first PCIe port and the component information of the downstream port of the first PCIe port, the baseboard management controller can search multiple configuration files according to the component information of the downstream port of the first PCIe port to determine the component information of the second PCIe port. The baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port. In the above way, without relying on the BIOS chip, the baseboard management controller can obtain the component information of PCIe ports and the link connection relationship between PCIe ports by using the configuration files of components, improving the acquisition efficiency of the component information of PCIe ports and the link connection relationship between PCIe ports, thereby improving the construction rate and accuracy of the component information tree, and further improving the construction rate and accuracy of the target PCIe link topology tree, and improving the performance of the baseboard management controller.

[0039] In one implementation, the method further includes:

[0040] Based on the device address information of the PCIe ports at both ends of the first link, determine the maximum PCIe link data of the PCIe ports at both ends of the first link;

[0041] Determine the smaller of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port.

[0042] In this solution, the baseboard management controller can determine the maximum PCIe link data of the PCIe ports at both ends of the first link based on the device address information of the PCIe ports at both ends of the first link, and determine the smaller of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port. Through the above method, the expected PCIe link data of the PCIe ports at both ends of the first link can be accurately determined.

[0043] In one implementation,

[0044] The component information includes component type, component identifier, and PCIe port identifier;

[0045] The device address information includes bus information, device information, and function information.

[0046] In this solution, the component information can include component type, component identifier, and PCIe port identifier, and the device address information can include bus information, device information, and function information. Through the above method, the target PCIe link topology tree obtained by the baseboard management controller can accurately reflect the information related to the PCIe ports, and further enable the baseboard management controller to accurately determine the abnormal link based on the target PCIe link topology tree.

[0047] In a second aspect, an embodiment of the present application provides a detection device for link abnormality, which is applied to a baseboard management controller in a computing device, and includes:

[0048] An acquisition module, configured to acquire a target PCIe link topology tree; the target PCIe link topology tree includes multiple PCIe ports and link connection relationships between multiple PCIe ports; each PCIe port is associated with its own device address information and its own component information;

[0049] A processing module, configured to, for a first PCIe port among the multiple PCIe ports, determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port;

[0050] The processing module is further configured to determine that the first link where the first PCIe port is located is abnormal when the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port;

[0051] The processing module is further configured to report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link.

[0052] The link abnormality detection device provided in this embodiment may execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0053] In one implementation, the processing module is further configured to:

[0054] Obtain a device address information tree; the device address information tree includes a plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports; each PCIe port is associated with its own device address information;

[0055] Obtain a component information tree; the component information tree includes a plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports; each PCIe port is associated with its own component information;

[0056] Based on the device address information tree and the component information tree, determine a target PCIe link topology tree.

[0057] The link abnormality detection device provided in this embodiment may execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0058] In one implementation, the processing module is specifically configured to:

[0059] Obtain the bus information of the root port;

[0060] According to the bus information of the root port, obtain the device address information of a plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports;

[0061] Construct a device address information tree according to the device address information of a plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports.

[0062] The link abnormality detection device provided in this embodiment may execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0063] In one implementation, the processing module is specifically configured to:

[0064] For any first PCIe port, obtain the device type according to the device address information of the first PCIe port; the device address information of the first PCIe port is determined according to the bus information of the root port, or the device address information of the first PCIe port is determined according to the next-level bus information corresponding to the device address information of the third PCIe port;

[0065] When the device type is the target device type, obtain the next-level bus information corresponding to the device address information of the first PCIe port;

[0066] Determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port;

[0067] Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0068] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0069] In one implementation, the target device type is the PCIe port or the root port of a bridging device.

[0070] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0071] In one implementation, the processing module is specifically configured to:

[0072] Obtain the configuration files of multiple components; the configuration file includes the component information of at least one PCIe port, or the configuration file includes the component information of at least one PCIe port and the component information of the downstream ports of the PCIe port;

[0073] According to the configuration files of multiple components, obtain the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports;

[0074] Construct a component information tree according to the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports.

[0075] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0076] In one implementation, the processing module is specifically configured to:

[0077] For any first PCIe port, when the configuration file includes the component information of the first PCIe port and the component information of the downstream port components of the first PCIe port, multiple configuration files are searched according to the component information of the downstream port components of the first PCIe port to determine the component information of the second PCIe port; the component information of the second PCIe port matches the component information of the downstream port components of the first PCIe port;

[0078] It is determined that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0079] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0080] In one implementation, the processing module is further configured to:

[0081] Based on the device address information of the PCIe ports at both ends of the first link, determine the maximum PCIe link data of the PCIe ports at both ends of the first link;

[0082] Determine the smaller of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port.

[0083] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0084] In one implementation,

[0085] The component information includes the component type, component identifier, and PCIe port identifier;

[0086] The device address information includes bus information, device information, and function information.

[0087] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0088] In a third aspect, an embodiment of the present application provides a computing device, including:

[0089] A baseboard management controller;

[0090] The baseboard management controller is used to execute the method in the first aspect.

[0091] The baseboard management controller in the computing device provided in the embodiment of the present application can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0092] Fourthly, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method of the first aspect.

[0093] The computer-readable storage medium provided by the embodiment of the present application can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described here again.

[0094] Fifthly, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it is used to implement the method of the first aspect.

[0095] The computer program product provided by the embodiment of the present application can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described here again. Description of the Drawings

[0096] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0097] Figure 1 It is a schematic diagram of the architecture of a computing device provided by an embodiment of the present application;

[0098] Figure 2a It is a schematic flowchart of the first embodiment of a method for detecting link anomalies provided by an embodiment of the present application;

[0099] Figure 2b It is a schematic diagram of a target PCIe link topology tree provided by an embodiment of the present application;

[0100] Figure 2c It is a schematic diagram of a search process provided by an embodiment of the present application;

[0101] Figure 3a It is a schematic flowchart of the second embodiment of a method for detecting link anomalies provided by an embodiment of the present application;

[0102] Figure 3b It is a schematic diagram of a device address information tree provided by an embodiment of the present application;

[0103] Figure 3c It is a schematic diagram of another device address information tree provided by an embodiment of the present application;

[0104] Figure 3dSchematic diagram of another target PCIe link topology tree provided by an embodiment of the present application;

[0105] Figure 4 Schematic flowchart of Embodiment 3 of a method for detecting link anomalies provided by an embodiment of the present application;

[0106] Figure 5a Schematic flowchart of Embodiment 4 of a method for detecting link anomalies provided by an embodiment of the present application;

[0107] Figure 5b Schematic diagram of the structure of a computing device provided by an embodiment of the present application;

[0108] Figure 5c Schematic diagram of a scenario where a PCIe switch is not in place provided by an embodiment of the present application;

[0109] Figure 5d Schematic diagram of a scenario where a hard disk is not in place provided by an embodiment of the present application;

[0110] Figure 6 Schematic diagram of the structure of a device for detecting link anomalies provided by an embodiment of the present application. Detailed implementation manners

[0111] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art under the inspiration of this embodiment fall within the scope of protection of the present application.

[0112] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and accompanying drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0113] For ease of understanding, first, in combination with Figure 1 the architecture of the computing device will be described.

[0114] Figure 1 Schematic diagram of the architecture of a computing device provided by an embodiment of the present application.

[0115] As Figure 1 shown, the computing device 10 may include a Central Processing Unit (CPU) 101, a Baseboard Management Controller (BMC) 102, a Basic Input Output System (BIOS) chip 103, and at least one peripheral component. It should be noted that both the peripheral component and the CPU 101 can be understood as components included in the computing device 10 (Field-replaceable Unit (FRU)).

[0116] Exemplarily, Figure 1 four peripheral components are shown, namely a PCIe switch 104, a Graphics Processing Unit (GPU) 105, a hard disk 106, and a Peripheral Component Interconnect Express (PCIe) card 107.

[0117] The CPU 101 is electrically connected to the BMC 102, the BIOS chip 103, and the PCIe switch 104 respectively.

[0118] The PCIe switch 104 can be electrically connected to the GPU 105, the hard disk 106, and the PCIe card 107. It should be noted that the GPU 105, the hard disk 106, and the PCIe card 107 are terminal components in the computing device 10.

[0119] Central Processing Unit (CPU): As the operation and control core of the computing device 10, it is the final execution unit for information processing and program running. The CPU is a very large-scale integrated circuit composed of an arithmetic unit, a controller, registers, etc., and its main task is to process and handle various data. The CPU may include multiple root ports. Exemplarily, the CPU may include three root ports.

[0120] Baseboard Management Controller (BMC): As an independent processor embedded in computing device 10, it can be used to monitor the software and hardware information, health status, and operating status of the server. It should be noted that computing devices 10 from different companies may have different names for BMC. For example, some companies call it BMC, some call it Integrated Lights-Out (iLO for short), and some call it Integrated Dell RemoteAccess Controller (iDRAC for short). Whether it is called BMC, iLO, or iDRAC, it can be understood as the BMC in the embodiments of this application.

[0121] Graphics Processing Unit (GPU): Also known as the display core, visual processor, and display chip, it is a microprocessor used to perform image and graphics-related operations.

[0122] Basic Input Output System (BIOS) chip: It is a specific ROM chip used to store the BIOS program. The main function of the BIOS chip is to provide the most basic and direct hardware settings and controls for the computing device. It should be noted that the BIOS program on the BIOS chip runs prior to the operating system (OS) after the computing device is powered on.

[0123] Hard disk: It is the main storage device of computing device 10. The hard disk can be a hard disk using the Non-Volatile Memory Express (NVME) specification or a hard disk using other specifications. The embodiments of this application do not limit this.

[0124] PCIe switch: It provides expansion capabilities. A PCIe switch can expand multiple PCIe ports through internal logic, and each PCIe port can be electrically connected to a PCIe device (terminal component or other PCIe switch).

[0125] PCIe card: It refers to hardware with a PCIe port (such as a network card) that can be inserted into a PCIe slot and communicate with the motherboard through the PCIe bus to increase the storage capacity, network function, or other hardware performance of computing device 10.

[0126] It should be noted that Figure 1 This is only a structural diagram of a computing device provided by the embodiments of this application. The embodiments of this application do not Figure 1neither defines the actual forms of various components included therein, nor Figure 1 defines the interaction manner between components therein. In the application of the solution, it can be set according to actual requirements.

[0127] An embodiment of the present application proposes a method for detecting a link anomaly. A baseboard management controller of a computing device can obtain a target PCIe link topology tree. The target PCIe link topology tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports. Among them, each PCIe port is associated with its own device address information and its own component information. For a first PCIe port among the plurality of PCIe ports, the baseboard management controller can determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port. When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, the baseboard management controller can determine a first link anomaly where the first PCIe port is located, and report the link anomaly based on the component information associated with the PCIe ports at both ends of the first link.

[0128] Through the above method, the detection efficiency and accuracy of link anomalies can be improved.

[0129] The following details the method for detecting a link anomaly in an embodiment of the present application. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0130] Figure 2a is a schematic flowchart of Embodiment 1 of a method for detecting a link anomaly provided by an embodiment of the present application. Refer to Figure 2a and the method specifically includes the following steps:

[0131] S201: Obtain a target PCIe link topology tree.

[0132] In this embodiment, the baseboard management controller of the computing device can obtain a target PCIe link topology tree. Exemplarily, Figure 2b is a schematic diagram of a target PCIe link topology tree provided by an embodiment of the present application.

[0133] Among them, the target PCIe link topology tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports.

[0134] Each PCIe port is associated with its own device address information and its own component information.

[0135] In one implementation,

[0136] The device address information includes bus information, device information, and function information. Exemplarily, as Figure 2b shown, the device address information of a PCIe port can be 3d:01.0. Among them, 3d is the bus information, 01 is the device information, and 0 is the function information.

[0137] In addition, it should be noted that the device address information is assigned by the BIOS chip of the computing device to the PCIe port when the operating system starts. Each time the operating system starts, the device address information assigned by the BIOS chip to the PCIe port can be the same or different. The device address information can be used to indicate the operating information of the PCIe port.

[0138] In one implementation,

[0139] The component information includes the component type, component identifier, and PCIe port identifier.

[0140] In one implementation, the component identifier can be the component number, and can also be other information reflecting the identity of the component. The PCIe port identifier can be the PCIe port number, and can also be other information that can reflect the identity of the PCIe port. Exemplarily, as Figure 2b shown, the component information of a PCIe port can be: CPU ID = 1 Port = 1. Among them, CPU is the component type, ID = 1 indicates that the component identifier is 1, and Port = 1 indicates that the PCIe port identifier is 1.

[0141] In addition, it can be understood that based on the component information including the component type, component identifier, and PCIe port identifier, the component information can be used to indicate the information of the PCIe device corresponding to the PCIe port.

[0142] Next, the process by which the baseboard management controller obtains the target PCIe link topology tree will be described.

[0143] In one implementation,

[0144] The baseboard management controller can obtain the target PCIe link topology tree stored in the storage space of the baseboard management controller. Among them, the target PCIe link topology tree is pre-constructed by the baseboard management controller and stored in the storage space of the baseboard management controller.

[0145] It should be noted that the storage space of the baseboard management controller refers to the storage space provided by the storage chip on the baseboard management controller.

[0146] Next, the process by which the baseboard management controller pre-constructs the target PCIe link topology tree will be described.

[0147] In one implementation,

[0148] The baseboard management controller can obtain the device address information tree. Among them, the device address information tree includes multiple PCIe ports and the link connection relationships between the multiple PCIe ports. It should be noted that each PCIe port is associated with its own device address information.

[0149] The baseboard management controller can obtain the component information tree. Among them, the component information tree includes multiple PCIe ports and the link connection relationships between the multiple PCIe ports. It should be noted that each PCIe port is associated with its own component information.

[0150] The baseboard management controller can determine the target PCIe link topology tree based on the device address information tree and the component information tree.

[0151] S202: For the first PCIe port among the multiple PCIe ports, determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port.

[0152] In this embodiment, for the first PCIe port among the multiple PCIe ports, the first PCIe port is associated with the device address information of the first PCIe port and the component information of the first PCIe port.

[0153] The baseboard management controller can determine the actual PCIe link data of the first PCIe port according to the device address information of the first PCIe port. In one implementation, the actual PCIe link data includes the actual speed and / or the actual bandwidth.

[0154] Next, the process of the baseboard management controller determining the actual PCIe link data of the first PCIe port according to the device address information of the first PCIe port will be described.

[0155] In one implementation,

[0156] The PCIe device (component) includes multiple configuration spaces, and each device address information corresponds to a configuration space. It should be noted that the configuration space is the storage space used by the PCIe device to store data. The configuration space can include multiple registers.

[0157] The baseboard management controller can perform at least one search process according to the device address information and the initial offset until the offset of the target register is found. Figure 2c A schematic diagram of a search process provided for an embodiment of the present application is as Figure 2c shown, and the baseboard management controller can find the offset of the target register.

[0158] It should be noted that the register corresponding to the initial offset is used to store the starting address of the PCIe Capability List. Exemplarily, as Figure 2c shown, the initial offset can be 0x34. It should also be noted that the PCIe Capability List is a linked list structure used to record the functions supported by the PCIe device.

[0159] In addition, it should be noted that the target register is the register for storing the target register value. Exemplarily, as Figure 2c shown, the target register value can be 0x10.

[0160] The baseboard management controller can send an actual PCIe link data acquisition command to the CPU after finding the offset of the target register. Among them, the actual PCIe link data acquisition command includes the first offset and the offset of the target register. Exemplarily, the first offset can be 0x12.

[0161] The CPU can determine the first register according to the offset of the target register and the first offset. It should be noted that the first register starts from the target register and is the register offset downward by the first offset.

[0162] The CPU can read the actual PCIe link data from the first register. Among them, the actual PCIe link data includes the actual speed and / or actual bandwidth.

[0163] The baseboard management controller can obtain the actual PCIe link data sent by the CPU.

[0164] Next, the process of the baseboard management controller performing at least one search process according to the device address information and the initial offset will be described.

[0165] In one implementation,

[0166] In the i-th search process, the baseboard management controller can generate the i-th acquisition command according to the device address information and the i-th offset. Among them, the i-th acquisition command includes the device address information and the i-th offset. It should be noted that when i is 1, the i-th offset is the initial offset. Exemplarily, the initial offset can be 0x34.

[0167] The baseboard management controller can send the i-th acquisition command to the CPU. It should be noted that the baseboard management controller sends the i-th acquisition command to the CPU through the Platform Environment Control Interface (PECI for short). The i-th acquisition command is a PECI command.

[0168] The CPU can, according to the device address information in the i-th acquisition command, determine the configuration space corresponding to the device address information, and determine that the register matching the i-th offset in the configuration space is the i-th register.

[0169] The CPU can perform a read process on the i-th register to obtain the i-th register value.

[0170] The CPU can send the i-th register value to the baseboard management controller.

[0171] The baseboard management controller can determine whether the i-th register value is the target register value. Exemplarily, the target register value can be 0x10.

[0172] If so, the baseboard management controller can determine the offset of the i-th register as the offset of the target register.

[0173] If not, the baseboard management controller can use the i-th register value as the (i + 1)-th offset.

[0174] Through the above method, the baseboard management controller can find the offset of the target register.

[0175] S203: When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, determine that the first link where the first PCIe port is located is abnormal.

[0176] In this embodiment, the baseboard management controller can determine whether the actual PCIe link data of the first PCIe port matches the expected PCIe link data of the first PCIe port after obtaining the actual PCIe link data of the first PCIe port.

[0177] If so, the baseboard management controller can determine that the first link where the first PCIe port is located is abnormal.

[0178] For example, as Figure 2b shown, for a first PCIe port (PCIe port 2 of the PCIe switch), the baseboard management controller can obtain the actual PCIe link data of the first PCIe port according to the device address information (3f:00.0) of the first PCIe port. The baseboard management controller can determine that the first link where the first PCIe port is located is abnormal when the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port.

[0179] It should be noted that in one implementation, in the target PCIe link topology tree, there can be one link between two PCIe ports. In one implementation, there can be one link between a PCIe port on an odd layer and a PCIe port on an even layer. Among them, the PCIe port on the odd layer is the upstream port of the PCIe port on the even layer.

[0180] It can be understood that there are no other PCIe ports between the PCIe ports at both ends of a PCIe link.

[0181] Next, the process of the baseboard management controller determining whether the actual PCIe link data of the first PCIe port matches the expected PCIe link data of the first PCIe port will be described.

[0182] In one implementation,

[0183] The baseboard management controller can determine whether the actual PCIe link data of the first PCIe port is less than the expected PCIe link data of the first PCIe port.

[0184] If so, the baseboard management controller can determine that the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port.

[0185] If not, the baseboard management controller can determine that the actual PCIe link data of the first PCIe port matches the expected PCIe link data of the first PCIe port.

[0186] Next, the process of the baseboard management controller pre-obtaining the expected PCIe link data of the first PCIe port will be described.

[0187] In one implementation,

[0188] The baseboard management controller can determine the maximum PCIe link data of the PCIe ports at both ends of the first link based on the device address information of the PCIe ports at both ends of the first link. It should be noted that the maximum PCIe link data of the PCIe ports at both ends of the first link includes the maximum PCIe link data of the PCIe port at one end of the first link and the maximum PCIe link data of the PCIe port at the other end of the first link. It should also be noted that the maximum PCIe link data includes the maximum speed and / or the maximum bandwidth.

[0189] The baseboard management controller can determine the smaller of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port. In one implementation, the expected PCIe link data includes the expected speed and / or the expected bandwidth.

[0190] Next, a process of the baseboard management controller determining the maximum PCIe link data of the first PCIe port (the PCIe port at one end of the first link) based on the device address information of the first PCIe port will be described.

[0191] In one implementation,

[0192] The baseboard management controller can perform at least one search process according to the device address information and the initial offset until the offset of the target register is found. It should be noted that the process of the baseboard management controller searching for the offset of the target register has been described above and will not be elaborated here.

[0193] After finding the offset of the target register, the baseboard management controller can send a maximum PCIe link data acquisition command to the CPU. The maximum PCIe link data acquisition command includes a second offset and the offset of the target register. Exemplarily, the second offset can be 0x0c.

[0194] The CPU can determine a second register according to the offset of the target register and the second offset. It should be noted that the second register is a register that starts from the target register and is offset downward by the second offset.

[0195] The CPU can read the maximum PCIe link data from the second register. In one implementation, the maximum PCIe link data includes the maximum speed and / or the maximum bandwidth.

[0196] The baseboard management controller can obtain the maximum PCIe link data sent by the CPU.

[0197] It should be noted that the process of the baseboard management controller determining another maximum PCIe link data (the maximum PCIe link data of the PCIe port at the other end of the first link) is similar to the process of the baseboard management controller determining the maximum PCIe link data of the first PCIe port based on the device address information of the first PCIe port and will not be elaborated here.

[0198] S204: Report a link exception based on the component information associated with the PCIe ports at both ends of the first link.

[0199] In this embodiment, when determining that the first link is abnormal, the baseboard management controller can determine the PCIe ports at both ends of the first link.

[0200] In one implementation, when the first PCIe port belongs to an even layer of the target PCIe link topology tree, the PCIe ports at both ends of the first link (the first link where the first PCIe port is located) can be the first PCIe port and the upstream port of the first PCIe port respectively. It should be noted that in one implementation, when the target PCIe link topology tree includes a root node, the root node does not participate in the calculation of the number of layers.

[0201] In one implementation, when the first PCIe port belongs to an odd layer of the target PCIe link topology tree, the PCIe ports at both ends of the first link (the first link where the first PCIe port is located) can be the first PCIe port and the downstream port of the first PCIe port respectively.

[0202] The baseboard management controller can report a link exception based on the component information associated with the PCIe ports at both ends of the first link.

[0203] Among them, the component information includes component type, component identifier, and PCIe port identifier.

[0204] In one implementation, the baseboard management controller can report a link exception by means of sensor alarm based on the component information associated with the PCIe ports at both ends of the first link.

[0205] In one implementation, the baseboard management controller can use the Simple Network Management Protocol (SNMP) Trap mechanism to report a link exception based on the component information associated with the PCIe ports at both ends of the first link.

[0206] In one implementation, the baseboard management controller can record the component information associated with the PCIe ports at both ends of the first link in the system log to report a link exception.

[0207] In addition, in one implementation, after determining the component information associated with the PCIe ports at both ends of the first link, the baseboard management controller can perform a self-healing operation according to the component information associated with the PCIe ports at both ends of the first link. Exemplarily, the self-healing operation can be a restart operation.

[0208] Beneficial effects of this embodiment: In this embodiment, the baseboard management controller of the computing device can obtain the target PCIe link topology tree; the target PCIe link topology tree includes multiple PCIe ports and the link connection relationships between the multiple PCIe ports; each PCIe port is associated with its own device address information and its own component information. For the first PCIe port among the multiple PCIe ports, the baseboard management controller can determine the actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port. When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, the baseboard management controller can determine that the first link where the first PCIe port is located is abnormal, and report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link. On the one hand, the method of this application embodiment can directly and accurately determine the component information of the PCIe ports at both ends of the abnormal link, that is, locate the components at both ends of the abnormal link, improving the detection efficiency and accuracy of the link abnormality. On the other hand, the method of this application embodiment does not require the baseboard management controller to interact with the BIOS chip. The baseboard management controller can directly obtain the target PCIe link topology tree that records the device address information and component information of the PCIe ports, and then detect the link abnormality based on the device address information and component information of the PCIe ports, realizing the decoupling of the baseboard management controller and the BIOS, and improving the performance of the baseboard management controller.

[0209] Next, through Method Embodiment 2, the process of the baseboard management controller pre-obtaining the target PCIe link topology tree will be described.

[0210] Figure 3a It is a schematic flowchart of Method Embodiment 2 for detecting a link abnormality provided by an embodiment of this application. Refer to Figure 3a The method specifically includes the following steps:

[0211] S301: Obtain the bus information of the root port.

[0212] In this embodiment, the baseboard management controller can obtain the bus information of the root port. In one implementation, the baseboard management controller can obtain the bus information of the root port when the operating system starts. It should be noted that the root port can be the PCIe port of the CPU.

[0213] In one implementation,

[0214] For any root port, the baseboard management controller can send a first command to the CPU through the PECI channel. The first command may include preset device address information and the offset of the third register. The preset device address information corresponds to a root port and is pre-obtained by the baseboard management controller. Additionally, in one implementation, the first command may be the RdPCIConfigLocal command. It should be noted that the RdPCIConfigLocal command is a PECI command.

[0215] After receiving the first command, the CPU can determine the configuration space corresponding to the preset device address information. The configuration space includes multiple registers.

[0216] Based on the offset of the third register, the CPU can determine the third register in the configuration space corresponding to the preset device address information and read the bus information of the root port stored in the third register.

[0217] The baseboard management controller can obtain the bus information of the root port sent by the CPU.

[0218] S302: Obtain the device address information of multiple PCIe ports and the link connection relationship between the multiple PCIe ports according to the bus information of the root port.

[0219] In this embodiment, the baseboard management controller can obtain the device address information of multiple PCIe ports and the link connection relationship between the multiple PCIe ports according to the bus information of the root port. It should be noted that in one implementation, the device address information of each PCIe port is assigned by the BIOS chip to each PCIe port when the operating system starts. In other words, the device address information can be used to indicate the operating information of the PCIe port.

[0220] In one implementation,

[0221] For any first PCIe port, the baseboard management controller can obtain the device type according to the device address information of the first PCIe port. The device address information of the first PCIe port is determined by the baseboard management controller according to the bus information of the root port, or the device address information of the first PCIe port is determined by the baseboard management controller according to the next-level bus information corresponding to the device address information of the third PCIe port.

[0222] When the device type is the target device type, the baseboard management controller can obtain the next-level bus information corresponding to the device address information of the first PCIe port. In one implementation, the target device type is the PCIe port or root port of a bridging device.

[0223] The baseboard management controller can determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port.

[0224] The baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port. In one implementation, the baseboard management controller can determine that the first PCIe port and the second PCIe port are the PCIe ports at both ends of a link.

[0225] S303: Construct a device address information tree according to the device address information of multiple PCIe ports and the link connection relationships between multiple PCIe ports.

[0226] In this embodiment, the baseboard management controller can construct a device address information tree according to the device address information of multiple PCIe ports and the link connection relationships between multiple PCIe ports. Exemplarily, Figure 3b FIG. is a schematic diagram of a device address information tree provided by an embodiment of the present application.

[0227] Among them, the device address information tree includes multiple PCIe ports and the link connection relationships between multiple PCIe ports, and each PCIe port is associated with its own device address information.

[0228] In addition, in one implementation, Figure 3c FIG. is a schematic diagram of another device address information tree provided by an embodiment of the present application. As Figure 3c shown, when the CPU of the computing device includes multiple root ports, the device address information tree may further include a root node (a virtual root node), and there may be a link connection relationship between the root node and each root port. It should be noted that between the root node and the root port, it is not a single link.

[0229] S304: Obtain configuration files of multiple components.

[0230] In this embodiment, the baseboard management controller can obtain configuration files of multiple components. In one implementation, the baseboard management controller can obtain configuration files of multiple components when the operating system is started.

[0231] In one implementation, the baseboard management controller can store configuration files of multiple components. The memory of each component (such as an Electrically Erasable Programmable Read-Only Memory (EEPROM)) can store the component code of the component. For any component, the baseboard management controller can obtain the component code of the component from the memory of the component. The baseboard management controller can determine the configuration file of the component from the configuration files of multiple components according to the component code and the corresponding relationship between the component code and the configuration file.

[0232] The configuration file can include component information of at least one PCIe port, or the configuration file can include component information of at least one PCIe port and component information of the downstream port of the PCIe port.

[0233] In one implementation, the component information can include component type, component identification, and port identification.

[0234] In addition, it should be noted that, in one implementation, the configuration file can also include component basic information (such as manufacturer, model, etc.), functions provided by the component (such as supported protocols, etc.), and the heat dissipation strategy of the component (such as required cooling method and power consumption, etc.).

[0235] S305: Obtain component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components.

[0236] In this embodiment, the baseboard management controller can obtain component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components.

[0237] In one implementation,

[0238] Taking any PCIe port as the first PCIe port as an example.

[0239] The configuration file includes component information of the first PCIe port, or the configuration file includes component information of the first PCIe port and component information of the downstream port of the first PCIe port.

[0240] For any first PCIe port, when the configuration file includes component information of the first PCIe port and component information of the downstream port of the first PCIe port, the baseboard management controller can search multiple configuration files according to the component information of the downstream port of the first PCIe port to determine the component information of the second PCIe port. Among them, the component information of the second PCIe port matches the component information of the downstream port of the first PCIe port.

[0241] The baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0242] In addition, it should be noted that when the configuration file does not include the component information of the downstream port of the first PCIe port, the baseboard management controller can end the analysis process of the first PCIe port.

[0243] In one implementation,

[0244] Taking any port as the second PCIe port as an example.

[0245] The configuration file includes the component information of the second PCIe port, or the configuration file includes the component information of the second PCIe port and the component information of the downstream port of the second PCIe port.

[0246] The baseboard management controller can search for multiple configuration files according to the component information of the second PCIe port and determine the component information of the first PCIe port. Among them, the component information of the second PCIe port matches the component information of the downstream port of the first PCIe port.

[0247] The baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0248] S306: Construct a component information tree according to the component information of multiple PCIe ports and the link connection relationships between multiple PCIe ports.

[0249] In this embodiment, the baseboard management controller can construct a component information tree according to the component information of multiple PCIe ports and the link connection relationships between multiple PCIe ports.

[0250] Among them, the component information tree includes multiple PCIe ports and the link connection relationships between multiple PCIe ports; each PCIe port is associated with its own component information.

[0251] It should be noted that the baseboard management controller can first execute S301 - S303 and then execute S304 - S306; the baseboard management controller can also first execute S304 - S306 and then execute S301 - S303; the baseboard management controller can also execute S304 - S306 while executing S301 - S303. The embodiments of the present application do not limit this.

[0252] S307: Determine the target PCIe link topology tree based on the device address information tree and the component information tree.

[0253] In this embodiment, the baseboard management controller may determine a target PCIe link topology tree based on the device address information tree and the component information tree.

[0254] Among them, the target PCIe link topology tree includes multiple PCIe ports and the link connection relationships between the multiple PCIe ports. Each PCIe port is associated with its own device address information and its own component information.

[0255] In addition, in one implementation Figure 3d is a schematic diagram of another target PCIe link topology tree provided by the embodiments of the present application. As Figure 3d shown, in the case where the CPU of the computing device includes multiple root ports, the target PCIe link topology tree may include a root node, and the root node may have link connection relationships with each root port. It should be noted that between the root node and the root port, there is not one link.

[0256] In addition, in one implementation, after constructing the target PCIe link topology tree, the baseboard management controller may store the target PCIe link topology tree in the storage space of the baseboard management controller.

[0257] Advantages of this embodiment: In this embodiment, the baseboard management controller can obtain the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the bus information of the root port, and construct a device address information tree according to the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports. The baseboard management controller can obtain the configuration files of multiple components; the configuration file includes the component information of at least one PCIe port, or the configuration file includes the component information of at least one PCIe port and the component information of the downstream port of the PCIe port. The baseboard management controller can obtain the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components, and construct a component information tree according to the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports. The baseboard management controller can determine the target PCIe link topology tree based on the device address information tree and the component information tree. In the above manner, without relying on the BIOS chip, the baseboard management controller can quickly construct the target PCIe link topology tree in the baseboard management controller based on the dynamic scanning mechanism and the component configuration file loading mechanism, so that the baseboard management controller can monitor the link status based on the target PCIe link topology tree, and when it is recognized that the actual PCIe link data of the PCIe port on the target PCIe link topology tree does not match the expected PCIe link data, determine that the first link where the first PCIe port is located is abnormal, and then report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link. In the above manner, the detection efficiency and accuracy of link abnormalities are improved.

[0258] Next, through Method Embodiment 3, the process of S302 in Embodiment 2, "obtain the device address information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the bus information of the root port", will be described.

[0259] Figure 4 It is a schematic flowchart of Method Embodiment 3 for detecting link abnormalities provided by an embodiment of the present application. Refer to Figure 4 , and the method specifically includes the following steps:

[0260] S401: For any first PCIe port, obtain the device type according to the device address information of the first PCIe port.

[0261] In this embodiment, the baseboard management controller can obtain the device address information of any first PCIe port.

[0262] In one implementation, the device address information of the first PCIe port can be determined by the baseboard management controller according to the bus information of the root port.

[0263] In one implementation, the device address information of the first PCIe port can be determined by the baseboard management controller according to the next-level bus information corresponding to the device address information of the third port. It should be noted that the process of the baseboard management controller determining the device address information of the first PCIe port according to the next-level bus information corresponding to the device address information of the third port is similar to the process of the baseboard management controller determining the device address information of the first PCIe port according to the bus information of the root port, and will not be elaborated here.

[0264] Next, the process of the baseboard management controller determining the device address information of the first PCIe port according to the bus information of the root port will be described.

[0265] In one implementation,

[0266] The baseboard management controller can obtain multiple first candidate device address information according to the bus information of the root port. Among them, the bus information in each first candidate device address information is the same as the bus information of the root port.

[0267] For each first candidate device address information, the baseboard management controller can generate an access command according to the first candidate device address information.

[0268] The baseboard management controller can send the access command to the CPU to access the configuration space corresponding to the first candidate device address information.

[0269] The baseboard management controller can obtain the PECI completion code sent by the CPU. It should be noted that when the first candidate device address information is valid device address information, the PECI completion code indicates successful access; when the first candidate device address information is invalid device address information, the PECI completion code indicates failed access.

[0270] The baseboard management controller can determine that the first candidate device address information is the device address information of the first PCIe port when the PECI completion code indicates successful access.

[0271] In addition, the baseboard management controller can also determine that there is a link connection relationship between the root port and the first PCIe port after obtaining the device address information of the first PCIe port. In addition, it should be noted that the root port and the first PCIe port can be the PCIe ports at both ends of a link.

[0272] After obtaining the device address information of the first PCIe port, the baseboard management controller can obtain the device type according to the device address information of the first PCIe port. In one implementation, the device type can be any one of the PCIe ports of a bridge device, a root port (the root port of the CPU), and the PCIe ports of terminal components.

[0273] Next, the process by which the baseboard management controller obtains the device type according to the device address information of the first PCIe port will be described.

[0274] In one implementation,

[0275] The PECI channel is the channel for the baseboard management controller to communicate with the CPU.

[0276] The baseboard management controller can send a second command to the CPU through the PECI channel. The second command can include the device address information of the first PCIe port and the offset of the fourth register. It should be noted that the fourth register is used to store the device type. Exemplarily, the offset of the fourth register can be 0x0c. Additionally, in one implementation, the second command can be the RdEndPointConfig command. It should be noted that the RdEndPointConfig command is a PECI command.

[0277] The CPU can, after receiving the second command, determine the configuration space corresponding to the device address information. The configuration space includes multiple registers.

[0278] The CPU can, according to the offset of the fourth register, determine the fourth register in the configuration space corresponding to the device address information and read the device type stored in the fourth register.

[0279] The baseboard management controller can obtain the device type sent by the CPU.

[0280] S402: When the device type is the target device type, obtain the next-level bus information corresponding to the device address information of the first PCIe port.

[0281] In this embodiment, the baseboard management controller can determine whether the device type is the target device type. The target device type is the PCIe port of a bridge device or a root port.

[0282] The baseboard management controller can, when the device type is the target device type, obtain the next-level bus information corresponding to the device address information of the first PCIe port.

[0283] In one implementation,

[0284] The baseboard management controller can send a third command to the CPU through the PECI channel. The third command can include the device address information of the first PCIe port and the offset of the fifth register. It should be noted that the fifth register is a register for storing the information of the next-level bus. Exemplarily, the offset of the fifth register can be 0x19. Additionally, in one implementation, the third command can be the RdEndPointConfig command.

[0285] The CPU can, after receiving the third command, determine the configuration space corresponding to the device address information. The configuration space includes multiple registers.

[0286] The CPU can, according to the offset of the fifth register, determine the fifth register in the configuration space corresponding to the device address information, and read the information of the next-level bus (secbus) stored in the fifth register.

[0287] The baseboard management controller can obtain the information of the next-level bus sent by the CPU.

[0288] S403: Determine the device address information of at least one second PCIe port according to the information of the next-level bus corresponding to the device address information of the first PCIe port.

[0289] In this embodiment, the baseboard management controller can determine the device address information of at least one second PCIe port according to the information of the next-level bus corresponding to the device address information of the first PCIe port.

[0290] In one implementation,

[0291] The baseboard management controller can obtain multiple second candidate device address information according to the information of the next-level bus corresponding to the device address information of the first PCIe port. The bus information in each second candidate device address information is the same as the information of the next-level bus corresponding to the device address information of the first PCIe port.

[0292] For each second candidate device address information, the baseboard management controller can generate an access command according to the second candidate device address information.

[0293] The baseboard management controller can send the access command to the CPU to access the configuration space corresponding to the second candidate device address information.

[0294] The baseboard management controller can obtain the PECI completion code sent by the CPU. It should be noted that when the second candidate device address information is valid device address information, the PECI completion code indicates successful access; when the second candidate device address information is invalid device address information, the PECI completion code indicates failed access.

[0295] The baseboard management controller can determine that the second candidate device address information is the device address information of the second PCIe port when the PECI completion code indicates successful access.

[0296] S404: Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0297] In this embodiment, the baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port after determining the device address information of the second PCIe port.

[0298] In other words, the baseboard management controller can determine that the first PCIe port is the upstream port of the second PCIe port.

[0299] In other words again, the baseboard management controller can determine that the first PCIe port is connected to the second PCIe port.

[0300] Advantageous effects of this embodiment: For any first PCIe port, the baseboard management controller can obtain the device type according to the device address information of the first PCIe port. The baseboard management controller can obtain the next-level bus information corresponding to the device address information of the first PCIe port when the device type is the target device type. The baseboard management controller can determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port, and determine that there is a link connection relationship between the first PCIe port and the second PCIe port. In the above manner, the baseboard management controller can obtain the device address information of each PCIe port and the link connection relationship between PCIe ports without relying on the BIOS, improving the acquisition efficiency of the device address information of PCIe ports and the link connection relationship between PCIe ports, thereby improving the construction rate of the device address information tree, and further improving the construction rate of the target PCIe link topology tree.

[0301] Next, through Method Embodiment 4, the process of S305 in Embodiment 2, "Obtain the component information of multiple PCIe ports and the link connection relationship between multiple PCIe ports according to the configuration files of multiple components", will be described.

[0302] Figure 5a It is a schematic flowchart of Method Embodiment 4 for detecting link anomalies provided by an embodiment of the present application. Refer to Figure 5a , and the method specifically includes the following steps:

[0303] S501: For any first PCIe port, when the configuration file includes component information of the first PCIe port and component information of a downstream port of the first PCIe port, search multiple configuration files according to the component information of the downstream port of the first PCIe port to determine component information of a second PCIe port.

[0304] In this embodiment, the configuration file includes component information of at least one PCIe port, or the configuration file includes component information of at least one PCIe port and component information of a downstream port of the PCIe port.

[0305] The component information includes component type, component ID, and port ID.

[0306] Figure 5b A schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0307] Next, combine Figure 5b , the configuration file of the component is explained through specific examples.

[0308] like Figure 5b As shown, the computing device 10 includes a CPU 101 , a PCIe switch 104 , a GPU 105 , a hard disk 106 , and a PCIe card 107 .

[0309] The CPU includes root port 0. For root port 0, the CPU configuration file includes component information of root port 0 and component information of downstream ports of root port 0. The component information of downstream ports of root port 0 may match the component information of PCIe port 1 of the PCIe switch.

[0310] The PCIe switch includes PCIe port 1, PCIe port 2, PCIe port 3, and PCIe port 4. A configuration file of the PCIe switch includes component information of PCIe port 1, component information of PCIe port 2, component information of a downstream port of PCIe port 2, component information of PCIe port 3, component information of a downstream port of PCIe port 3, component information of PCIe port 4, and component information of a downstream port of PCIe port 4.

[0311] The downstream port component information of the PCIe port 2 may match the component information of the PCIe port of the GPU.

[0312] The downstream port component information of PCIe port 3 may match the component information of the PCIe port of the hard disk.

[0313] The downstream port component information of the PCIe port 4 may match the component information of the PCIe port of the PCIe card.

[0314] It should be noted that, in one implementation, Figure 5c FIG. is a schematic diagram of a scenario where a PCIe switch is not in place provided by an embodiment of the present application. As Figure 5c shown, in the case where the PCIe switch is not in place, the configuration file of the CPU includes the downstream port component information of root port 0, and the downstream port component information of root port 0 matches the component information of PCIe port 1 of the PCIe switch. Exemplarily, the downstream port component information of root port 0 included in the configuration file of the CPU may be (PCIe Switch ID = 1 Port = 1).

[0315] In one implementation, Figure 5d FIG. is a schematic diagram of a scenario where a hard disk is not in place provided by an embodiment of the present application. As Figure 5d shown, in the case where the hard disk is not in place, the configuration file of the PCIe switch includes the downstream port component information of PCIe port 3 of the PCIe switch, and the downstream port component information of PCIe port 3 of the PCIe switch matches the component information of the PCIe port of the hard disk. Exemplarily, the downstream port component information of PCIe port 3 included in the configuration file of the PCIe switch may be (hard disk, ID = 2, Port = *). It should be noted that for a component with multiple functions, "Port = *" indicates that the component is matched.

[0316] In this embodiment, any PCIe port is taken as the first PCIe port as an example.

[0317] When the configuration file includes the component information of the first PCIe port and the downstream port component information of the first PCIe port, the baseboard management controller may search multiple configuration files according to the downstream port component information of the first PCIe port to determine the component information of the second PCIe port.

[0318] Among them, the component information of the second PCIe port matches the downstream port component information of the first PCIe port.

[0319] It should be noted that, in one implementation,

[0320] The fact that the component information of the second PCIe port matches the downstream port component information of the first PCIe port means that:

[0321] The component information of the second PCIe port is the same as the downstream port component information of the first PCIe port; or,

[0322] The component type and component identifier in the component information of the second PCIe port are the same as those in the component information of the downstream port of the first PCIe port, and the port identifier in the component information of the downstream port of the first PCIe port is "Port=*".

[0323] S502: Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0324] In this embodiment, the baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port when determining that there is component information of the second PCIe port.

[0325] In other words, the baseboard management controller can determine that the first PCIe port is the upstream port of the second PCIe port.

[0326] In yet other words, the baseboard management controller can determine that the first PCIe port is connected to the second PCIe port.

[0327] Advantageous effects of this embodiment: In this embodiment, for any first PCIe port, when the configuration file includes the component information of the first PCIe port and the component information of the downstream port of the first PCIe port, the baseboard management controller can, according to the component information of the downstream port of the first PCIe port, search for multiple configuration files to determine the component information of the second PCIe port. The baseboard management controller can determine that there is a link connection relationship between the first PCIe port and the second PCIe port. By the above method, the baseboard management controller does not need to rely on the BIOS chip, and can obtain the component information of the PCIe port and the link connection relationship between the PCIe ports by using the configuration file of the component, improving the acquisition efficiency of the component information of the PCIe port and the link connection relationship between the PCIe ports, thereby improving the construction speed and accuracy of the component information tree, and further improving the construction speed and accuracy of the target PCIe link topology tree, and improving the performance of the baseboard management controller.

[0328] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the method embodiment of the present application.

[0329] Figure 6 It is a schematic structural diagram of a link anomaly detection apparatus provided in an embodiment of the present application. As Figure 6 shown, the link anomaly detection apparatus 60 includes an acquisition module 61 and a processing module 62. Among them,

[0330] An acquisition module 61, configured to acquire a target PCIe link topology tree; the target PCIe link topology tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each PCIe port is associated with its own device address information and its own component information;

[0331] A processing module 62, configured to, for a first PCIe port among the plurality of PCIe ports, determine actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port;

[0332] The processing module 62 is further configured to, when the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, determine that a first link where the first PCIe port is located is abnormal;

[0333] The processing module 62 is further configured to report the link abnormality based on the component information associated with the PCIe ports at both ends of the first link.

[0334] The link abnormality detection device provided in this embodiment may execute the technical solutions in the above method embodiments, and the beneficial effects are similar, and will not be elaborated here.

[0335] In one implementation, the processing module 62 is further configured to:

[0336] Acquire a device address information tree; the device address information tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each PCIe port is associated with its own device address information;

[0337] Acquire a component information tree; the component information tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each PCIe port is associated with its own component information;

[0338] Determine the target PCIe link topology tree based on the device address information tree and the component information tree.

[0339] The link abnormality detection device provided in this embodiment may execute the technical solutions in the above method embodiments, and the beneficial effects are similar, and will not be elaborated here.

[0340] In one implementation, the processing module 62 is specifically configured to:

[0341] Acquire bus information of a root port;

[0342] According to the bus information of the root port, acquire the device address information of a plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports;

[0343] Construct a device address information tree based on the device address information of multiple PCIe ports and the link connection relationships between the multiple PCIe ports.

[0344] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0345] In one implementation, the processing module 62 is specifically configured to:

[0346] For any first PCIe port, obtain the device type according to the device address information of the first PCIe port; the device address information of the first PCIe port is determined according to the bus information of the root port, or the device address information of the first PCIe port is determined according to the next-level bus information corresponding to the device address information of the third PCIe port;

[0347] When the device type is the target device type, obtain the next-level bus information corresponding to the device address information of the first PCIe port;

[0348] Determine the device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port;

[0349] Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0350] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0351] In one implementation, the target device type is the PCIe port or the root port of a bridging device.

[0352] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details are not described herein again.

[0353] In one implementation, the processing module 62 is specifically configured to:

[0354] Obtain the configuration files of multiple components; the configuration file includes the component information of at least one PCIe port, or the configuration file includes the component information of at least one PCIe port and the component information of the downstream ports of the PCIe port;

[0355] Obtain the component information of multiple PCIe ports and the link connection relationships between the multiple PCIe ports according to the configuration files of the multiple components;

[0356] Construct a component information tree based on the component information of multiple PCIe ports and the link connection relationships between the multiple PCIe ports.

[0357] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described herein again.

[0358] In one implementation, the processing module 62 is specifically configured to:

[0359] For any first PCIe port, when the configuration file includes the component information of the first PCIe port and the component information of the downstream port of the first PCIe port, according to the component information of the downstream port of the first PCIe port, search for multiple configuration files to determine the component information of the second PCIe port; the component information of the second PCIe port matches the component information of the downstream port of the first PCIe port;

[0360] Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

[0361] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described herein again.

[0362] In one implementation, the processing module 62 is further configured to:

[0363] Based on the device address information of the PCIe ports at both ends of the first link, determine the maximum PCIe link data of the PCIe ports at both ends of the first link;

[0364] Determine the smaller value of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port.

[0365] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described herein again.

[0366] In one implementation,

[0367] The component information includes component type, component identifier, and PCIe port identifier;

[0368] The device address information includes bus information, device information, and function information.

[0369] The link anomaly detection device provided in this embodiment can execute the technical solutions in the above method embodiments, and the beneficial effects are similar, so details will not be described herein again.

[0370] An embodiment of the present application provides a computing device, including:

[0371] A baseboard management controller;

[0372] The baseboard management controller is used to execute the technical solutions in the foregoing method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here.

[0373] An embodiment of the present application further provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the technical solutions provided by the foregoing method embodiments.

[0374] An embodiment of the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, it is used to implement the technical solutions provided by the foregoing method embodiments.

[0375] Those of ordinary skill in the art can understand that all or part of the steps of implementing the foregoing method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the foregoing method embodiments; and the foregoing storage medium includes: various media such as ROM, RAM, magnetic disk, or optical disc that can store program codes.

[0376] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting link anomalies, characterized in that, A baseboard management controller applied to a computing device, the method comprising: Obtaining a target PCIe link topology tree; the target PCIe link topology tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each of the PCIe ports is associated with respective device address information and respective component information; For a first PCIe port among the plurality of PCIe ports, determining actual PCIe link data of the first PCIe port based on the device address information of the first PCIe port; When the actual PCIe link data of the first PCIe port does not match the expected PCIe link data of the first PCIe port, determining a first link anomaly where the first PCIe port is located; Reporting the link anomaly based on component information associated with PCIe ports at both ends of the first link.

2. The method according to claim 1, characterized in that, The method further comprises: Obtaining a device address information tree; the device address information tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each of the PCIe ports is associated with respective device address information; Obtaining a component information tree; the component information tree includes a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; each of the PCIe ports is associated with respective component information; Determining the target PCIe link topology tree based on the device address information tree and the component information tree.

3. The method according to claim 2, wherein The obtaining the device address information tree includes: Obtaining bus information of a root port; According to the bus information of the root port, obtaining device address information of a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports; Constructing the device address information tree according to the device address information of the plurality of PCIe ports and the link connection relationships between the plurality of PCIe ports.

4. The method according to claim 3, wherein The according to the bus information of the root port, obtaining device address information of a plurality of PCIe ports and link connection relationships between the plurality of PCIe ports, includes: For any first PCIe port, obtaining a device type according to the device address information of the first PCIe port; the device address information of the first PCIe port is determined according to the bus information of the root port, or the device address information of the first PCIe port is determined according to the next-level bus information corresponding to the device address information of a third PCIe port; When the device type is a target device type, obtaining the next-level bus information corresponding to the device address information of the first PCIe port; Determining device address information of at least one second PCIe port according to the next-level bus information corresponding to the device address information of the first PCIe port; Determining that there is a link connection relationship between the first PCIe port and the second PCIe port.

5. The method according to claim 4, characterized in that, The target device type is a PCIe port or a root port of a bridging device.

6. The method according to claim 2, wherein The obtaining the component information tree includes: Obtain the configuration files of multiple components; the configuration file includes component information of at least one PCIe port, or the configuration file includes component information of at least one of the PCIe ports and component information of the downstream port components of the PCIe port; According to the configuration files of the multiple components, obtain component information of multiple PCIe ports and the link connection relationship between the multiple PCIe ports; Construct the component information tree according to the component information of the multiple PCIe ports and the link connection relationship between the multiple PCIe ports; 7. The method according to claim 6, wherein The obtaining component information of multiple PCIe ports and the link connection relationship between the multiple PCIe ports according to the configuration files of the multiple components includes: For any first PCIe port, when the configuration file includes component information of the first PCIe port and component information of the downstream port components of the first PCIe port, according to the component information of the downstream port components of the first PCIe port, search multiple of the configuration files to determine component information of a second PCIe port; the component information of the second PCIe port matches the component information of the downstream port components of the first PCIe port; Determine that there is a link connection relationship between the first PCIe port and the second PCIe port.

8. The method according to any one of claims 1 to 7, characterized in that The method further includes: Based on the device address information of the PCIe ports at both ends of the first link, determine the maximum PCIe link data of the PCIe ports at both ends of the first link; Determine the smaller of the maximum PCIe link data of the PCIe ports at both ends of the first link as the expected PCIe link data of the first PCIe port.

9. The method according to any one of claims 1-8, wherein The component information includes component type, component identifier, and PCIe port identifier; The device address information includes bus information, device information, and function information.

10. A computing device, characterized in that, Includes: Baseboard Management Controller; The baseboard management controller is used to execute the method according to any one of claims 1-9.

Images