A functional safety design method for a read data path of an eFLASH controller and a read cache
By setting up three Datapath+Cache sets within the eFLASH controller, and combining triple redundancy, hierarchical redundancy, and heterogeneous redundancy design, the problem of unstable data reading by the eFLASH controller under complex operating conditions is solved. This achieves an efficient, flexible, and reliable functional safety design, ensuring timely and accurate data acquisition.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2026-03-31
AI Technical Summary
The existing eFLASH controller's read data path and read cache design cannot guarantee stability and security under complex vehicle operating conditions, especially in the event of a fault, it cannot provide critical data in a timely and accurate manner.
A design approach combining triple redundancy, hierarchical redundancy, and heterogeneous redundancy is adopted. Composite redundancy is achieved by setting up three sets of Datapath+Cache in the eFLASH controller, and hierarchical redundancy and circuit recombination are performed through the Cross module. The CPU implements module configuration through APB, supporting redundant and non-redundant modes. ECC and CRC are used to protect data, and an error injection path is designed to improve reliability.
It achieves an efficient, flexible, and reliable functional safety design for the eFLASH controller's data read path and read cache, ensuring timely and accurate data acquisition under complex vehicle operating conditions and meeting automotive-grade functional safety requirements.
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Figure CN120386748B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of embedded flash memory data reading, in particular to a functional safety design method for a read data path and read cache of an eFLASH controller. BACKGROUND
[0002] In automotive electronic systems, eFLASH (embedded flash memory) as an important storage component, the reliability of its data reading is crucial for the safe operation of the vehicle. In order to improve the stability and safety of the read operation of the eFLASH controller, the read Cache redundancy architecture and functional safety design method emerge as the times require.
[0003] The read Cache redundancy architecture is divided into:
[0004] (1) Double read Cache redundancy structure, by constructing the architecture of main read Cache and standby read Cache working at the same time. When the eFLASH controller receives a read request, data will be loaded from the eFLASH memory into the main and standby Cache at the same time. This double Cache structure is like giving the data reading "double insurance", even if one Cache fails, the other Cache can still provide data normally, ensuring uninterrupted operation of the system. For example, in the engine control unit of the vehicle, the reading of the engine control parameters stored in the eFLASH, the double read Cache redundancy structure can ensure that the engine control unit can obtain the required parameters in time and accurately under various complex working conditions, and maintain the stable operation of the engine.
[0005] Distributed read Cache redundancy mode, using distributed design, dividing the read Cache into multiple sub Cache modules and distributing them in different physical locations. This layout effectively improves the fault tolerance of the system. When a certain area is affected by local hardware failure, such as failure of a sub Cache module due to vehicle vibration, electromagnetic interference, other sub Cache modules can still work normally. For example, in the core computing module of the autonomous vehicle, the reading of the map data, decision algorithm and other key information stored in the eFLASH, the distributed read Cache redundancy architecture can ensure that even if part of the sub Cache modules appear abnormal due to the surrounding environmental factors during the vehicle driving, the autonomous driving system can still obtain data from other normal sub Cache modules, and maintain the stable operation of the autonomous driving function.
[0006] To realize composite redundancy design for the read data path and read pre-fetch Cache of the eFlash controller, to realize more reliable, more efficient and more flexible functional safety design, the present application provides a functional safety design method for a read data path and read Cache of an eFLASH controller. SUMMARY
[0007] (a) Technical problems to be solved
[0008] To address the shortcomings of existing technologies, this invention provides a functional safety design method for the read data path and read cache of an eFLASH controller. As a functional safety design method, this method can flexibly improve eFLASH read efficiency and meet automotive-grade functional safety requirements.
[0009] (II) Technical Solution
[0010] To achieve the above objectives, the present invention provides the following technical solution: a functional safety design method for the read data path and read cache of an eFLASH controller, which realizes triple redundancy and heterogeneous redundancy by setting three sets of Datapath+Cache in the FLASH controller, and realizes hierarchical redundancy and circuit reconfiguration through the Cross module; the CPU implements module configuration through APB, and the CPU or other Master accesses Flash Memory through AXI via Cache and Data_path.
[0011] Preferably, the working mechanism of the triple-modular redundancy circuit is as follows:
[0012] Input data is compared and voted on in FENC_Poll0 after passing through DataPath0, DataPath1, and DataPath2; data is compared and voted on in FENC_Poll1 after passing through Cache0, Cache1, and Cache2.
[0013] The circuit's operating mechanism supports two modes: redundant mode or non-redundant mode.
[0014] Preferably, in the redundancy mode:
[0015] Compare the output of DataPath0 with the output of DataPath1. If they match, the result output to Cross is considered correct.
[0016] Otherwise, compare the output of DataPath1 with the output of DataPath2. If they match, then the result output to Cross is considered correct.
[0017] Otherwise, compare the output of DataPath0 with the output of DataPath2. If they match, then the result output to Cross is considered correct.
[0018] Otherwise, this circuit segment is determined to be faulty;
[0019] Compare the output of Cache0 with the output of Cache1. If they match, the output is considered correct.
[0020] Otherwise, compare the output of Cache1 with the output of Cache2. If they match, the output is considered correct.
[0021] Otherwise, compare the output of Cache0 with the output of Cache2. If they match, the output is considered correct.
[0022] Otherwise, this circuit segment is determined to be faulty;
[0023] DataPathX can be used in combination with CacheY.
[0024] Preferably, in the non-redundant mode:
[0025] The three sets of DataPath and Cache work simultaneously, supporting data caching in three different address ranges, and DataPathX can be combined with CacheY in a cross-functional manner.
[0026] Preferably, the heterogeneous redundancy circuit operation mechanism is as follows: Cache0 uses ECC to protect data, and Cache1 and Cache2 use CRC to protect data;
[0027] The working mechanism of the layered redundancy circuit is as follows: the data read path is divided into two layers, DataPath and Cache, which perform redundancy and comparison respectively.
[0028] Preferably, DataPathX and CacheY are combined to form a complete data path through the Cross configuration.
[0029] Preferably, the cache structure and mechanism are as follows:
[0030] It contains one address unit and eight data units. The address stored in the address unit corresponds to the data in the first data unit. After the data at address ADDR is read, the data at ADDR+1 is sequentially shifted to the first data unit. After shifting sequentially, the last data unit is pre-read from FLASH.
[0031] In redundancy mode:
[0032] The three caches store the same memory address, which is equivalent to only one cache existing.
[0033] Non-redundant mode:
[0034] Three caches can work simultaneously, supporting data caching of three different address ranges;
[0035] When access from address A arrives, the data is cached in Cache0;
[0036] When address B is accessed, check if B falls within [A+1, A+8]. If it does, cache the data in Cache0; otherwise, cache the data and address in Cache1.
[0037] When address C is accessed, it is determined whether C falls within [A+1, A+8] or [B+1, B+8]. If it does, the data is still cached using Cache0 / Cache1; otherwise, the data and address are cached in Cache2.
[0038] When address D arrives, determine whether D falls within [A+1, A+8], [B+1, B+8], or [C+1, C+8]. If it does, continue to use Cache0 / Cache1 / Cache2 to cache the data; otherwise, update the oldest Cache0 and cache the data and address in Cache0.
[0039] Preferably, the DataPath and Cache are designed with separate error injection paths to support the injection of error 0 or error 1.
[0040] Preferably, the circuit data path of the method includes:
[0041] In redundant mode, DataPath0 is in Front mode, and DataPath1 / 2 are in Back mode;
[0042] In redundant mode, DataPath1 is in Front mode, and DataPath0 / 2 are in Back mode;
[0043] In redundant mode, DataPath2 is in Front mode, and DataPath0 / 1 is in Back mode.
[0044] In redundant mode, Cache0 is in Front mode, and Cache1 / 2 is in Back mode;
[0045] In redundant mode, Cache1 is in Front mode, and Cache0 / 2 is in Back mode;
[0046] In redundant mode, Cache2 is in Front mode, and Cache0 / 1 is in Back mode;
[0047] Non-redundant mode.
[0048] (III) Beneficial Effects
[0049] Compared with the prior art, the present invention provides a functional safety design method for the read data path and read cache of an eFLASH controller, which has the following advantages:
[0050] This method combines triple redundancy, hierarchical redundancy, and heterogeneous redundancy, along with hierarchical circuit reconfiguration design and a functional safety design using four-stage registers and inverters. This allows for flexible configuration of the data path, enabling a composite redundancy design for the eFlash controller's read data path and read prefetch cache. The entire solution is more reliable, efficient, and flexible, effectively improving eFLASH read efficiency while meeting automotive-grade functional safety requirements. Attached Figure Description
[0051] Figure 1 This is a schematic diagram of the solution architecture of the present invention;
[0052] Figure 2 This is a circuit diagram illustrating redundancy and comparison in this invention;
[0053] Figure 3 This is a schematic diagram of the internal structure of the cache in this invention;
[0054] Figure 4 This is a schematic diagram of the data path for redundancy and comparison in this invention. Detailed Implementation
[0055] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0056] Please see Figure 1 To achieve a more reliable, efficient, and flexible functional safety design, this invention proposes a functional safety design method for the read data path and read cache of an eFlash controller. This method achieves triple-modal redundancy and heterogeneous redundancy by setting up three sets of Datapath+Cache within the FLASH controller, and hierarchical redundancy and circuit recombination through Cross modules. The CPU configures the modules through APB, and the CPU or other Master accesses the Flash Memory through AXI via Cache and Data_path.
[0057] Circuit working mechanism as follows Figure 2 As shown, it includes three-mode redundancy mechanism, hierarchical redundancy mechanism, cross-switch mechanism, heterogeneous redundancy mechanism, cache structure and mechanism, and error injection mechanism.
[0058] The working mechanism of the triple-modular redundancy circuit is as follows:
[0059] Input data is compared and voted on in FENC_Poll0 after passing through DataPath0, DataPath1, and DataPath2; data is compared and voted on in FENC_Poll1 after passing through Cache0, Cache1, and Cache2.
[0060] The circuit operating mechanism supports two modes: redundant mode or non-redundant mode.
[0061] In redundancy mode:
[0062] Compare the output of DataPath0 with the output of DataPath1. If they match, the result output to Cross is considered correct.
[0063] Otherwise, compare the output of DataPath1 with the output of DataPath2. If they match, then the result output to Cross is considered correct.
[0064] Otherwise, compare the output of DataPath0 with the output of DataPath2. If they match, then the result output to Cross is considered correct.
[0065] Otherwise, this circuit segment is determined to be faulty;
[0066] Compare the output of Cache0 with the output of Cache1. If they match, the output is considered correct.
[0067] Otherwise, compare the output of Cache1 with the output of Cache2. If they match, the output is considered correct.
[0068] Otherwise, compare the output of Cache0 with the output of Cache2. If they match, the output is considered correct.
[0069] Otherwise, this circuit segment is determined to be faulty;
[0070] DataPathX can be used in combination with CacheY.
[0071] In non-redundant mode:
[0072] The three DataPath and Cache sets work simultaneously, supporting data caching for three different address ranges, and DataPathX can be combined with CacheY in a cross-functional manner.
[0073] The heterogeneous redundancy circuit working mechanism is as follows: Cache0 uses ECC to protect data, while Cache1 and Cache2 use CRC to protect data.
[0074] The working mechanism of the layered redundancy circuit is as follows: the data read path is divided into two layers, DataPath and Cache, which perform redundancy and comparison respectively.
[0075] The cross-switch mechanism combines DataPathX and CacheY into a complete data path through Cross configuration.
[0076] In addition, cache structure and mechanisms such as Figure 3 As shown, it contains one address unit and eight data units. The address stored in the address unit corresponds to the data in the first data unit. After the data at address ADDR is read, the data at ADDR+1 is sequentially shifted to the first data unit. After shifting sequentially, the last data unit is pre-read from the FLASH.
[0077] In redundancy mode:
[0078] The three caches store the same memory address, which is equivalent to only one cache existing.
[0079] Non-redundant mode:
[0080] Three caches can work simultaneously, supporting data caching of three different address ranges;
[0081] When access from address A arrives, the data is cached in Cache0;
[0082] When address B is accessed, check if B falls within [A+1, A+8]. If it does, cache the data in Cache0; otherwise, cache the data and address in Cache1.
[0083] When address C is accessed, it is determined whether C falls within [A+1, A+8] or [B+1, B+8]. If it does, the data is still cached using Cache0 / Cache1; otherwise, the data and address are cached in Cache2.
[0084] When address D arrives, determine whether D falls within [A+1, A+8], [B+1, B+8], or [C+1, C+8]. If it does, continue to use Cache0 / Cache1 / Cache2 to cache the data; otherwise, update the oldest Cache0 and cache the data and address in Cache0.
[0085] The error injection mechanism has designed separate error injection paths for DataPath and Cache, supporting the injection of error 0 or error 1.
[0086] Circuit data path as follows Figure 4 As shown, the circuit data path includes:
[0087] In redundant mode, DataPath0 is in Front mode, and DataPath1 / 2 are in Back mode.
[0088] The input is sent from path0 through MUX to DataPath0, and then through Path6 to the Cross module;
[0089] The input is sent from path0 to DataPath0 via the MUX, then XORed with the error injection signal from Fault_Inject0 via Path7. The result is then XORed with the output from DataPath1 via an inverter. This result is fed into FENC_Poll0 for decoding and polling decisions.
[0090] The input is sent from path2 through MUX to DataPath1, and then through path9 to the Cross module;
[0091] The input is sent from path2 to DataPath1 via the MUX, and then XORed with the error injection signal from Fault_Inject2 via Path9a. This result is then XORed with the output from DataPath2. The result is fed into FENC_Poll0 for decoding and polling decisions.
[0092] The input is sent from path4 through MUX to DataPath2, and then through Path10 to the Cross module;
[0093] The input is sent from path4 through the MUX to DataPath2, and then XORed with the fault injection signal from Fault_Inject0 via Path10a. This result is then XORed with the output from DataPath0. Finally, this result is fed into FENC_Poll0 for decoding and polling decisions.
[0094] In redundant mode, DataPath1 is in Front mode, and DataPath0 / 2 is in Back mode.
[0095] The input is sent from path1 through MUX to DataPath0, and then through Path6 to the Cross module;
[0096] The input is sent from path1 to DataPath0 via the MUX, then XORed with the fault injection signal from Fault_Inject0 via Path6a. The result is then XORed with the output from DataPath1 via an inverter. This result is fed into FENC_Poll0 for decoding and poll decision.
[0097] The input is sent from path3 through MUX to DataPath1, and then through path9 to the Cross module;
[0098] The input is sent from path3 through the MUX to DataPath1, and then XORed with the error injection signal from Fault_Inject2 via path8. This result is then XORed with the output from DataPath2. The result is then fed into FENC_Poll0 for decoding and polling decisions.
[0099] The input is sent from path4 through MUX to DataPath2, and then through Path10 to the Cross module;
[0100] The input is sent from path4 through the MUX to DataPath2, and then XORed with the fault injection signal from Fault_Inject0 via Path10a. This result is then XORed with the output from DataPath0. Finally, this result is fed into FENC_Poll0 for decoding and polling decisions.
[0101] In redundant mode, DataPath2 is in Front mode, and DataPath0 / 1 is in Back mode.
[0102] The input is sent from path1 through MUX to DataPath0, and then through Path6 to the Cross module;
[0103] The input is sent from path1 to DataPath0 via the MUX, then XORed with the fault injection signal from Fault_Inject0 via Path6a. The result is then XORed with the output from DataPath1 via an inverter. This result is fed into FENC_Poll0 for decoding and poll decision.
[0104] The input is sent from path2 through MUX to DataPath1, and then through path9 to the Cross module;
[0105] The input is sent from path2 to DataPath1 via the MUX, and then XORed with the error injection signal from Fault_Inject2 via Path9a. This result is then XORed with the output from DataPath2. The result is fed into FENC_Poll0 for decoding and polling decisions.
[0106] The input is sent from path5 through MUX to DataPath2, and then through path10 to the Cross module;
[0107] The input is sent from path5 through the MUX to DataPath2, then XORed with the fault injection signal from Fault_Inject0 via path11. This result is then XORed with the output from DataPath0. Finally, this result is fed into FENC_Poll0 for decoding and polling decisions.
[0108] In redundant mode, Cache0 is in Front mode, and Cache1 / 2 are in Back mode.
[0109] The input from Cross is sent to Cache0 via MUX through path12, and then sent out via Path18;
[0110] The input from Cross is sent to Cache0 via MUX through path12, and then XORed with the fault injection signal from Fault_Inject1 through Path18a. The result is then XORed with the output from Cache1 after passing through an inverter. This result is then fed into FENC_Poll1 for decoding and poll decision.
[0111] The input from Cross is sent to Cache1 via MUX through path14, and then sent out via Path21;
[0112] The input from Cross is sent to Cache1 via MUX through path14, and then XORed with the fault injection signal from Fault_Inject1 via Path21a. This result is XORed with the output from Cache2. The result is then fed into FENC_Poll1 for decoding and polling decisions.
[0113] The input from Cross is sent to Cache2 via MUX through path16, and then sent out via Path22;
[0114] The input from Cross is sent to Cache2 via MUX through path16, and then XORed with the fault injection signal from Fault_Inject1 via Path22a. This result is then XORed with the output from Cache0. Finally, this result is fed into FENC_Poll1 for decoding and polling decisions.
[0115] In redundant mode, Cache1 is in Front mode, and Cache0 / 2 are in Back mode.
[0116] The input from Cross is sent to Cache1 via MUX through path15, and then sent out via Path21;
[0117] The input from Cross is sent to Cache1 via MUX through path15, and then XORed with the fault injection signal from Fault_Inject1 via path20. This result is then XORed with the output from Cache0. Finally, this result is fed into FENC_Poll1 for decoding and polling decisions.
[0118] The input from Cross is sent to Cache0 via MUX through path13, and then sent out via Path18;
[0119] The input from Cross is sent to Cache0 via MUX through path13, and then XORed with the fault injection signal from Fault_Inject1 via Path18a. This result is XORed with the output from Cache1. The result is then fed into FENC_Poll1 for decoding and polling decisions.
[0120] The input from Cross is sent to Cache2 via MUX through path16, and then sent out via Path22;
[0121] The input from Cross is sent to Cache2 via MUX through path16, and then XORed with the fault injection signal from Fault_Inject1 via Path22a. This result is then XORed with the output from Cache0. Finally, this result is fed into FENC_Poll1 for decoding and polling decisions.
[0122] In redundant mode, Cache2 is in Front mode, and Cache0 / 1 is in Back mode.
[0123] The input from Cross is sent to Cache2 via MUX through path17, and then sent out via Path22;
[0124] The input from Cross is sent to Cache2 via MUX through path17, and then XORed with the fault injection signal from Fault_Inject1 via path23. This result is then XORed with the output from Cache0. Finally, this result is fed into FENC_Poll1 for decoding and polling decisions.
[0125] The input from Cross is sent to Cache0 via MUX through path13, and then sent out via Path18;
[0126] The input from Cross is sent to Cache0 via MUX through path13, and then XORed with the fault injection signal from Fault_Inject1 via Path18a. This result is then XORed with the output from Cache2. Finally, this result is fed into FENC_Poll1 for decoding and polling decisions.
[0127] The input from Cross is sent to Cache1 via MUX through path14, and then sent out via Path21;
[0128] The input from Cross is sent to Cache1 via MUX through path14, and then XORed with the fault injection signal from Fault_Inject1 via Path21a. This result is XORed with the output from Cache2. The result is then fed into FENC_Poll1 for decoding and polling decisions.
[0129] Non-redundant mode:
[0130] The input is sent from path0 through MUX to DataPath0, and then through Path6 to the Cross module;
[0131] The input is sent from path3 through MUX to DataPath1, and then through path9 to the Cross module;
[0132] The input is sent from path5 through MUX to DataPath2, and then through path10 to the Cross module;
[0133] The input from Cross is sent to Cache0 via MUX through path12, and then sent out via Path18;
[0134] The input from Cross is sent to Cache1 via MUX through path15, and then sent out via Path21;
[0135] The input from Cross is sent to Cache2 via MUX through path17, and then sent out through Path22.
[0136] This method combines triple redundancy, hierarchical redundancy, and heterogeneous redundancy, along with hierarchical circuit reconfiguration design and a functional safety design using four-stage registers and inverters. This allows for flexible configuration of the data path, enabling a composite redundancy design for the eFlash controller's read data path and read prefetch cache. The entire solution is more reliable, efficient, and flexible, effectively improving eFLASH read efficiency while meeting automotive-grade functional safety requirements.
[0137] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A functional safety design method for a read data path of an eFLASH controller and a read Cache, characterized in that, Three sets of Datapath+Cache are set in the FLASH controller to realize three-module redundancy and heterogeneous redundancy, and Cross module is used to realize hierarchical redundancy and circuit recombination; a CPU is connected with configuration registers of the FLASH controller through an APB bus to realize configuration of the module, and the CPU or other Master accesses the Flash Memory through AXI, Cache and Data_path; The circuit working mechanism of the three-module redundancy is as follows: After input data passes through DataPath0, DataPath1 and DataPath2, comparison and voting are performed at FENC_Poll0; after the data passes through Cache0, Cache1 and Cache2, comparison and voting are performed at FENC_Poll1; The circuit working mechanism supports two modes: redundancy mode or non-redundancy mode; The circuit working mechanism of the heterogeneous redundancy is that Cache0 uses ECC to protect data, and Cache1 and Cache2 use CRC to protect data; The hierarchical redundancy circuit working mechanism is that a read data path is divided into two layers of DataPath and Cache, and redundancy and comparison are performed respectively; The Cross configures DataPathX and CacheY to form a complete data path, and circuit recombination is realized.
2. The functional safety design method of a read data path and a read Cache of an eFLASH controller according to claim 1, wherein, In the redundancy mode: The output of DataPath0 and the output of DataPath1 are compared, and if they are consistent, it is determined that the result output to the Cross is correct; Otherwise, the output of DataPath1 and the output of DataPath2 are compared, and if they are consistent, it is determined that the result output to the Cross is correct; Otherwise, the output of DataPath0 and the output of DataPath2 are compared, and if they are consistent, it is determined that the result output to the Cross is correct; Otherwise, it is determined that the data comparison and voting circuit composed of the two Datapath modules currently compared is incorrect; The output of Cache0 and the output of Cache1 are compared, and if they are consistent, it is determined that the output is correct; Otherwise, the output of Cache1 and the output of Cache2 are compared, and if they are consistent, it is determined that the output is correct; Otherwise, the output of Cache0 and the output of Cache2 are compared, and if they are consistent, it is determined that the output is correct; Otherwise, it is determined that the data comparison and voting circuit composed of the two Cache modules currently compared is incorrect; DataPathX can work in cross combination with CacheY.
3. The functional safety design method of a read data path and a read Cache of an eFLASH controller according to claim 1, wherein, In the non-redundancy mode: The three sets of DataPath and Cache work simultaneously, support data caching of three different address segments, and DataPathX can work in cross combination with CacheY.
4. The functional safety design method of a read data path and a read Cache of an eFLASH controller according to claim 1, wherein, The Cache structure and mechanism are as follows: The data path includes one address unit and eight data units, the address unit stores the address corresponding to the data of the first data unit; when the data of address ADDR is read, the data of ADDR+1 is sequentially shifted to the first data unit, and the last data unit is pre-read from the FLASH; In the redundancy mode: The address units of the three caches store the same address, which is equivalent to only one cache existing; In the non-redundancy mode: The three caches work simultaneously, supporting the data caching of three different address segments; When the address A access comes, the data is cached to Cache0; When the address B access comes, it is judged whether B falls within [A+1, A+8], if yes, the data is still cached to Cache0, otherwise the data and address are cached to Cache1; When the address C access comes, it is judged whether C falls within [A+1, A+8] or [B+1, B+8], if yes, the data is still cached to Cache0 / Cache1, otherwise the data and address are cached to Cache2; When the address D access comes, it is judged whether D falls within [A+1, A+8] or [B+1, B+8] or [C+1, C+8], if yes, the data is still cached to Cache0 / Cache1 / Cache2, otherwise the oldest Cache0 is updated, and the data and address are cached to Cache0.
5. The functional safety design method of a read data path and a read Cache of an eFLASH controller according to claim 4, wherein, The DataPath and Cache are respectively designed with separate error injection paths, supporting the injection of error 0 or error 1.
6. The functional safety design method of a read data path and a read Cache of an eFLASH controller according to claim 5, wherein, The circuit data path of the method includes: In the redundancy mode, DataPath0 is Front mode, and DataPath1 / 2 is Back mode; In the redundancy mode, DataPath1 is Front mode, and DataPath0 / 2 is Back mode; In the redundancy mode, DataPath2 is Front mode, and DataPath0 / 1 is Back mode; In the redundancy mode, Cache0 is Front mode, and Cache1 / 2 is Back mode; In the redundancy mode, Cache1 is Front mode, and Cache0 / 2 is Back mode; In the redundancy mode, Cache2 is Front mode, and Cache0 / 1 is Back mode; In the non-redundancy mode.
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