Limit aperture ratio pixel circuit and preparation method thereof

Abstract

The invention discloses a limit aperture ratio pixel circuit and a preparation method, the limit aperture ratio pixel circuit comprises a first sub-pixel circuit and a second sub-pixel circuit, and the first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; and the first sub-pixel circuit and the second sub-pixel circuit share a pre-storage capacitor. The pixel circuit has the beneficial effect that the aperture opening ratio of the pixel circuit can be improved through the overlapping design of the pre-storage capacitors of the first sub-pixel circuit and the second sub-pixel circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel display, and in particular to an ultimate aperture ratio pixel circuit and a preparation method thereof. Background Art

[0002] The field sequential or color sequential display driving technology directly uses the RGB three-color light source to mix colors through the visual persistence residual effect of humans to achieve a full-color display effect. Without a color filter, on the one hand, the light source utilization rate is improved, and on the other hand, the power consumption of the light source is also reduced. After all the picture data is written, the backlight can only be turned on after the liquid crystal deflects to a stable state. Otherwise, there will be a phenomenon of picture chaos. Therefore, a large amount of time needs to be reserved for the liquid crystal to deflect before turning on the backlight. This makes it difficult to achieve high brightness and high-frequency display within an average time, and at the same time increases the requirements for the backlight brightness specification and lifespan, increasing the cost.

[0003] While achieving high refresh rate and high brightness, it is also necessary to ensure the aperture ratio of the pixel circuit. Therefore, the present invention proposes an ultimate aperture ratio pixel circuit and a preparation method thereof to improve the aperture ratio of the pixel circuit. Summary of the Invention

[0004] The purpose of the present invention is to propose an ultimate aperture ratio pixel circuit and a preparation method thereof, which realizes the improvement of the aperture ratio.

[0005] The purpose of the present invention is achieved through the following technical solutions. An ultimate aperture ratio pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit, and the circuit structures of the first sub-pixel circuit and the second sub-pixel circuit are the same; The first sub-pixel circuit and the second sub-pixel circuit share a pre-storage capacitor.

[0006] Further, the first sub-pixel circuit includes a first transistor, a pre-storage capacitor, a second transistor, a storage capacitor, and a pixel electrode. The first source-drain of the first transistor of the first sub-pixel circuit is coupled to the second data signal line, the gate of the first transistor of the first sub-pixel circuit is coupled to the row gate signal line, and the second source-drain of the first transistor of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor; the other end of the pre-storage capacitor is coupled to the second sub-pixel circuit; The first source-drain of the second transistor of the first sub-pixel circuit is coupled to the second source-drain of the first transistor of the first sub-pixel circuit. The gate of the second transistor of the first sub-pixel circuit is coupled to the transfer signal line. The second source-drain of the second transistor of the first sub-pixel circuit is coupled to one end of the pixel electrode. The other end of the pixel electrode is coupled to the common signal line. One end of the storage capacitor is coupled to the second source-drain of the second transistor. The other end of the storage capacitor is coupled to the common signal line.

[0007] Further, the second sub-pixel circuit includes a first transistor of the second sub-pixel circuit, a pre-storage capacitor, a second transistor, a second storage capacitor, and a second pixel electrode. The first source-drain of the first transistor of the second sub-pixel circuit is coupled to the first data signal line. The gate of the first transistor of the second sub-pixel circuit is coupled to the row gate signal line. The second source-drain of the first transistor of the second sub-pixel circuit is coupled to one end of the pre-storage capacitor. The other end of the pre-storage capacitor is coupled to the first sub-pixel circuit. The first source-drain of the second transistor of the second sub-pixel circuit is coupled to the second source-drain of the first transistor of the second sub-pixel circuit. The gate of the second transistor of the second sub-pixel circuit is coupled to the transfer signal line. The second source-drain of the second transistor of the second sub-pixel circuit is coupled to one end of the second pixel electrode. The other end of the second pixel electrode is coupled to the common signal line. One end of the second storage capacitor is coupled to the second source-drain of the second transistor of the second sub-pixel circuit. The other end of the second storage capacitor is coupled to the common signal line.

[0008] Further, the row gate signal line includes a first row gate signal line and a second row gate signal line. The gate of the first transistor of the first sub-pixel circuit is coupled to the first row gate signal line. The gate of the first transistor of the second sub-pixel circuit is coupled to the second row gate signal line. The first row gate signal line and the second row gate signal line overlap in the vertical direction.

[0009] Further, the first sub-pixel circuit further includes a third transistor. The gate of the third transistor is coupled to the reset signal line. The first source-drain of the third transistor is coupled to one end of the pixel electrode. The second source-drain of the third transistor is coupled to the first data signal line. The second sub-pixel circuit further includes a third transistor. The gate of the third transistor is coupled to the reset signal line. The first source-drain of the third transistor is coupled to one end of the second pixel electrode. The second source-drain of the third transistor is coupled to the second data signal line.

[0010] The present invention also provides a method for manufacturing an extreme aperture ratio pixel circuit, including: Provide a substrate; sequentially form a light-shielding layer pattern on the substrate, and form a whole-surface barrier layer; Form a buffer layer on the whole surface of the barrier layer; Arrange an active layer on the buffer layer, and form the channel region, the first end, and the second end of the first transistor of the first sub-pixel circuit by using a heavily doped process. At the same time, form the channel region, the first end, and the second end of the second transistor and the channel region, the first end, and the second end of the third transistor; at the same time, also form the channel region, the first end, and the second end of the first transistor of the second sub-pixel circuit, and at the same time, also form the channel region, the first end, and the second end of the second transistor and the channel region, the first end, and the second end of the third transistor; Arrange a gate insulating layer on the whole surface of the active layer; Form a gate metal pattern and row gate signal lines on the gate insulating layer. The gate metal pattern constitutes the gates of the first transistor, the second transistor, and the third transistor of the first sub-pixel circuit; at the same time, also form the gates of the first transistor, the second transistor, and the third transistor of the second sub-pixel circuit; Arrange a second insulating layer on the whole surface of the gate metal pattern; Form a second metal layer on the second insulating layer, form a common signal line on the second metal layer, and form the upper plate of the first pre-storage capacitor and the lower plate of the second pre-storage capacitor; Form a third insulating layer on the second metal layer, form a third metal layer on the third insulating layer, and the third metal layer serves as the upper plate of the second pre-storage capacitor; The pre-storage capacitors overlap to form a pre-storage capacitor; Form a fourth insulating layer on the third metal layer, form a fourth metal layer on the fourth insulating layer, and form a reference signal line on the fourth metal layer; Form a fifth insulating layer on the fourth metal layer, form a fifth metal layer on the fifth insulating layer, and form a first data signal line and a second data signal line on the fifth metal layer; Form a sixth insulating layer on the whole surface of the fifth metal layer, and form a first transparent conductive layer on the sixth insulating layer as the storage capacitor of the first sub-pixel circuit and the second storage capacitor of the second sub-pixel circuit; Form a seventh insulating layer on the first transparent conductive layer, and form a second transparent conductive layer on the seventh insulating layer as the pixel electrode of the first sub-pixel circuit and the second pixel electrode of the second sub-pixel circuit.

[0011] The present invention has the following advantages: By overlapping the pre-storage capacitor of the first sub-pixel circuit and the pre-storage capacitor of the second sub-pixel circuit, the first sub-pixel circuit and the second sub-pixel circuit share a pre-storage capacitor, and the pre-storage capacitor is arranged in the non-display area of the circuit, so that the capacitors overlap partially in the vertical direction, achieving the situation where the capacitance value of the pre-storage capacitor remains unchanged, but the area of the entire pre-storage capacitor can be reduced, thereby improving the aperture ratio of the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is the circuit diagram of Embodiment 1 of the present invention; Figure 2 is the timing diagram of Embodiment 1 of the present invention; Figure 3 is the schematic cross-sectional layout diagram of Embodiment 1 of the present invention; Figure 4 is the circuit diagram of Embodiment 2 of the present invention; Figure 5 is the schematic cross-sectional layout diagram of Embodiment 2 of the present invention; Figure 6 is the circuit diagram of Embodiment 3 of the present invention; Figure 7 is the timing diagram of Embodiment 3 of the present invention; Figure 8 is the schematic flow diagram of the method of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The present invention will be further described below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0014] It should be noted that the orientation or positional relationship indicated by "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use, or the orientation or positional relationship commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0015] It should be noted that, without conflict, the embodiments in the present invention and the features and technical solutions in the embodiments can be combined with each other. Embodiment

[0016] Referring to Figure 1 , the present invention provides a pixel circuit with an ultimate aperture ratio, including a first sub-pixel circuit and a second sub-pixel circuit, and the circuit structures of the first sub-pixel circuit and the second sub-pixel circuit are the same; the first sub-pixel circuit and the second sub-pixel circuit share a pre-storage capacitor Cs1.

[0017] Further, the first sub-pixel circuit includes a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a storage capacitor Cs2, and a pixel electrode Clc; a first source-drain of the first transistor T1 of the first sub-pixel circuit is coupled to a second data signal line Data2, a gate of the first transistor T1 of the first sub-pixel circuit is coupled to a row gate signal line Scan, and a second source-drain of the first transistor T1 of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor Cs1; the other end of the pre-storage capacitor Cs1 is coupled to the second sub-pixel circuit; A first source-drain of the second transistor T2 of the first sub-pixel circuit is coupled to the second source-drain of the first transistor T1 of the first sub-pixel circuit, a gate of the second transistor T2 of the first sub-pixel circuit is coupled to a transfer signal line Tran, and a second source-drain of the second transistor T2 of the first sub-pixel circuit is coupled to one end of the pixel electrode Clc; the other end of the pixel electrode Clc is coupled to a common signal line Com; one end of the storage capacitor Cs2 is coupled to the second source-drain of the second transistor T2; the other end of the storage capacitor Cs2 is coupled to the common signal line Com.

[0018] Further, the second sub-pixel circuit includes a first transistor T1' of the second sub-pixel circuit, a pre-storage capacitor Cs1, a second transistor T2', a second storage capacitor Cs2', and a second pixel electrode Clc'; a first source-drain of the first transistor T1' of the second sub-pixel circuit is coupled to a first data signal line Data1, a gate of the first transistor T1' of the second sub-pixel circuit is coupled to a row gate signal line Scan, a second source-drain of the first transistor T1' of the second sub-pixel circuit is coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the first sub-pixel circuit; A first source-drain of the second transistor T2' of the second sub-pixel circuit is coupled to the second source-drain of the first transistor T1' of the second sub-pixel circuit, a gate of the second transistor T2' of the second sub-pixel circuit is coupled to a transfer signal line Tran, and a second source-drain of the second transistor T2' of the second sub-pixel circuit is coupled to one end of the second pixel electrode Clc'; the other end of the second pixel electrode Clc' is coupled to a common signal line Com; one end of the second storage capacitor Cs2' is coupled to the second source-drain of the second transistor T2' of the second sub-pixel circuit; the other end of the second storage capacitor Cs2' is coupled to the common signal line Com.

[0019] In the first embodiment, as Figure 2 shown, the timing at the Nth frame of the pixel circuit is configured as: Backlight turning-on stage of the Nth frame: The row gate signal line Scan and the transfer signal line Tran transition to a high level, the first transistor T1 and the second transistor T2 are turned on, and the second data signal line Data writes the data signal voltage of the Nth frame to the pixel electrode Clc through the first transistor T1 and the second transistor T2 to complete signal display; After the writing of the Nth frame is completed, the row gate signal line Scan and the transfer signal line Tran transition to the normal level, and the normal level is Vcom; The row gate signal line Scan transitions to a high level, the first transistor T1 is turned on, and the second data signal line Data2 writes the overdrive voltage / demand voltage of the (N + 1)th frame to the pre-storage capacitor Cs1 through the first transistor T1; Backlight off stage of the Nth frame: The transfer signal line Tran transitions to a high level, the second transistor T2 is turned on, and the pre-storage capacitor Cs1 writes the OD data signal voltage of the (N + 1)th frame to the pre-storage capacitor Cs1.

[0020] In the present invention, the overdrive voltage of the (N + 1)th frame is pre-written into the pre-storage capacitor Cs1 during the display stage of the Nth frame, so that when the (N + 1)th frame is displayed, it can be ensured that the data signal voltage written from the data signal line to the pixel electrode Clc can quickly and reliably switch states, and the voltage difference between the data signal voltage required for the (N + 1)th frame and the voltage remaining on the pixel electrode Clc of the Nth frame exceeds the minimum inversion requirement.

[0021] Through the present invention, the pre-storage capacitor Cs1 is divided into a first pre-storage capacitor Cs1-1 and a second pre-storage capacitor Cs1-2; the pre-storage capacitor Cs1 of the first sub-pixel circuit and the pre-storage capacitor Cs2 of the second sub-pixel circuit share the second metal layer and overlap in the vertical direction; The lower plate of the first pre-storage capacitor Cs1-1 is composed of the second metal layer, the upper plate of the first pre-storage capacitor Cs1-1 is composed of the gate metal layer, the second metal layer also constitutes the lower plate of the second pre-storage capacitor Cs1-2 at the same time, and the upper plate of the second pre-storage capacitor is composed of the third metal layer; the second metal layer constitutes the common plate of the first pre-storage capacitor Cs1-1 and the second pre-storage capacitor Cs1-2, and the first pre-storage capacitor and the second pre-storage capacitor together form the pre-storage capacitor Cs1, so that the first sub-pixel circuit and the second sub-pixel circuit share the capacitor; Such as Figure 3As shown in the figure, it is a cross-sectional view of the layout designed by the present invention. It can be seen that the present invention realizes capacitance overlap in the vertical direction, thereby reducing the area. The present invention uses the second metal layer as a common electrode plate, adopts a sandwich design of upper and lower layers, and connects the first pre-storage capacitor Cs1-1 and the second pre-storage capacitor Cs1-2 in parallel, so that the capacitance becomes a pre-storage capacitor Cs1, realizing partial overlap of the capacitance in the vertical direction, thereby reducing the area, and thus improving the aperture ratio of the pixel circuit. Embodiment

[0022] As Figure 4 shown, in this embodiment, a pixel circuit with an extreme aperture ratio. In the second embodiment, the row gate signal line Scan includes a first row gate signal line Scan1 and a second row gate signal line Scan2. The gate of the first transistor T1 of the first sub-pixel circuit is coupled to the first row gate signal line Scan1, and the gate of the first transistor T1' of the second sub-pixel circuit is coupled to the second row gate signal line Scan2. The first row gate signal line Scan1 and the second row gate signal line Scan2 adopt a double-gate overlapping design.

[0023] As Figure 5 shown, during preparation, the light-shielding layer also forms the second row gate signal line Scan2. That is, a double-gate design can be adopted to overlap the first row gate signal line Scan1 prepared by the gate metal layer and the second row gate signal line Scan2 prepared by the light-shielding layer. They are overlapped in the vertical direction, and it does not affect the aperture ratio of the pixel circuit. Embodiment

[0024] As Figure 6 shown, Embodiment 3 provides a pixel circuit with an extreme aperture ratio. The first sub-pixel circuit further includes a third transistor T3. The gate of the third transistor T3 is coupled to the reset signal line Reset. The first source-drain of the third transistor T3 is coupled to one end of the pixel electrode Clc, and the second source-drain of the third transistor T3 is coupled to the first data signal line Data1; The second sub-pixel circuit further includes a third transistor T3'. The gate of the third transistor T3' is coupled to the reset signal line Reset. The first source-drain of the third transistor T3' is coupled to one end of the second pixel electrode Clc', and the second source-drain of the third transistor T3' is coupled to the second data signal line Data2.

[0025] As Figure 7 shown, in the backlight turning-on stage of the sub-circuit in the Nth row: The row gate signal line Scan and the transfer signal line Tran jump to a high level. The first transistor T1 and the second transistor T2 are turned on. The second data signal line Data writes the data signal voltage of the Nth frame into the pixel electrode Clc through the first transistor T1 and the second transistor T2 to complete signal display; After the writing of the Nth frame is completed, the row gate signal line Scan and the transfer signal line Tran jump to the normal level, and the normal level is Vcom; The row gate signal line Scan jumps to the high level, the first transistor T1 is turned on, and the second data signal line Data2 writes the OD data signal voltage (overdrive voltage / demand voltage) of the (N + 1)th frame into the pre-storage capacitor Cs1 through the first transistor T1; In the backlight off stage of the sub-circuit of the Nth row: The reset signal line Reset jumps to the high level, the third transistor T3 is turned on, and the pixel electrode Clc realizes pixel reset to the first data signal line Data through the third transistor T3; The transfer signal line Tran jumps to the high level, the second transistor T2 is turned on, and the pre-storage capacitor Cs1 writes the OD data signal voltage of the (N + 1)th frame into the pre-storage capacitor Cs1.

[0026] Compared with the first embodiment and the second embodiment, this embodiment adopts a three-transistor design, and uses the third transistor T3 as the reset transistor; this embodiment can reduce the requirement for the overdrive voltage and ensure that the data signal voltage input to the pixel electrode Clc is not affected by other residual voltages, ensuring the accuracy of the display screen. Embodiment

[0027] As Figure 8 shown, this embodiment is a method for fabricating an ultimate aperture ratio pixel circuit.

[0028] S1. Provide a substrate; sequentially form a light-shielding layer pattern on the substrate and form a whole-surface barrier layer; Form a buffer layer on the whole surface of the barrier layer; S2. Set an active layer on the buffer layer, and use the heavily doped process to form the channel region, the first end and the second end of the first transistor T1 of the first sub-pixel circuit, and at the same time, form the channel region, the first end and the second end of the second transistor T2 and the channel region, the first end and the second end of the third transistor T3; at the same time, form the channel region, the first end and the second end of the first transistor T1' of the second sub-pixel circuit, and at the same time, form the channel region, the first end and the second end of the second transistor T2' and the channel region, the first end and the second end of the third transistor T3'; Set a gate insulating layer on the whole surface of the active layer; S3. Form a gate metal pattern and a row gate signal line on the gate insulating layer, and the gate metal pattern constitutes the gates of the first transistor T1, the second transistor T2 and the third transistor T3 of the first sub-pixel circuit; at the same time, form the gates of the first transistor T1', the second transistor T2' and the third transistor T3' of the second sub-pixel circuit; The second insulating layer is disposed entirely on the gate metal pattern; S4. A second metal layer is formed on the second insulating layer, a common signal line Com is formed on the second metal layer, and the upper electrode of the first pre-storage capacitor Cs1-1 and the lower electrode of the second pre-storage capacitor Cs1-2 are formed; A third insulating layer is formed on the second metal layer, a third metal layer is formed on the third insulating layer, and the third metal layer serves as the upper electrode of the second pre-storage capacitor Cs1-2; The first pre-storage capacitor Cs1-1 and the second pre-storage capacitor Cs1-2 are connected in parallel through the second metal layer and overlap to form a pre-storage capacitor Cs1; The second metal layer serves as the common electrode plate of the pre-storage capacitor Cs1; S5. A fourth insulating layer is formed on the third metal layer, a fourth metal layer is formed on the fourth insulating layer, and a reference signal line Vref is formed on the fourth metal layer; S6. A fifth insulating layer is formed on the fourth metal layer, a fifth metal layer is formed on the fifth insulating layer, and a first data signal line Data1 and a second data signal line Data2 are formed on the fifth metal layer; S7. A sixth insulating layer is formed entirely on the fifth metal layer, and a first transparent conductive layer is formed on the sixth insulating layer as the storage capacitor Cs2 of the first sub-pixel circuit and the second storage capacitor Cs2' of the second sub-pixel circuit; S8. A seventh insulating layer is formed on the first transparent conductive layer, and a second transparent conductive layer is formed on the seventh insulating layer as the pixel electrode Clc of the first sub-pixel circuit and the second pixel electrode Clc' of the second sub-pixel circuit.

[0029] In the present invention, by using the second metal layer as the common electrode plate and adopting an upper and lower two-layer sandwich design, the first pre-storage capacitor Cs1-1 and the second pre-storage capacitor Cs1-2 are connected in parallel, so that the capacitors are combined into a pre-storage capacitor Cs1, and the capacitors overlap in the vertical direction to reduce the area, thereby improving the aperture ratio of the pixel circuit.

[0030] This embodiment is used to prepare the circuits of Embodiment 1, Embodiment 2, and Embodiment 3 and their deformed circuits, and the beneficial effects are the same as those of Embodiment 1.

[0031] The above embodiments only represent relatively preferred implementation manners, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention patent. It should be noted that for those of ordinary skill in the art, without departing from the premise of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. An extreme aperture ratio pixel circuit, characterized in that: It includes a first sub-pixel circuit and a second sub-pixel circuit, and the circuit structures of the first sub-pixel circuit and the second sub-pixel circuit are the same; The first sub-pixel circuit and the second sub-pixel circuit share a pre-storage capacitor (Cs1).

2. The pixel circuit with an ultimate aperture ratio according to claim 1, characterized in that The first sub-pixel circuit includes a first transistor (T1), a pre-storage capacitor (Cs1), a second transistor (T2), a storage capacitor (Cs2), and a pixel electrode (Clc); the first source-drain of the first transistor (T1) of the first sub-pixel circuit is coupled to a second data signal line (Data2), the gate of the first transistor (T1) of the first sub-pixel circuit is coupled to a row gate signal line (Scan), and the second source-drain of the first transistor (T1) of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor (Cs1); the other end of the pre-storage capacitor (Cs1) is coupled to the second sub-pixel circuit; The first source-drain of the second transistor (T2) of the first sub-pixel circuit is coupled to the second source-drain of the first transistor (T1) of the first sub-pixel circuit, the gate of the second transistor (T2) of the first sub-pixel circuit is coupled to a transfer signal line (Tran), and the second source-drain of the second transistor (T2) of the first sub-pixel circuit is coupled to one end of the pixel electrode (Clc); the other end of the pixel electrode (Clc) is coupled to a common signal line (Com); one end of the storage capacitor (Cs2) is coupled to the second source-drain of the second transistor (T2); the other end of the storage capacitor (Cs2) is coupled to the common signal line (Com).

3. The pixel circuit with an ultimate aperture ratio according to claim 2, characterized in that, The second sub-pixel circuit includes a first transistor (T1’) of the second sub-pixel circuit, a pre-storage capacitor (Cs1), a second transistor (T2’), a second storage capacitor (Cs2’), and a second pixel electrode (Clc’); the first source-drain of the first transistor (T1’) of the second sub-pixel circuit is coupled to a first data signal line (Data1), the gate of the first transistor (T1’) of the second sub-pixel circuit is coupled to a row gate signal line (Scan), the second source-drain of the first transistor (T1’) of the second sub-pixel circuit is coupled to one end of the pre-storage capacitor (Cs1), and the other end of the pre-storage capacitor (Cs1) is coupled to the first sub-pixel circuit; The first source-drain of the second transistor (T2’) of the second sub-pixel circuit is coupled to the second source-drain of the first transistor (T1’) of the second sub-pixel circuit, the gate of the second transistor (T2’) of the second sub-pixel circuit is coupled to a transfer signal line (Tran), and the second source-drain of the second transistor (T2’) of the second sub-pixel circuit is coupled to one end of the second pixel electrode (Clc’); the other end of the second pixel electrode (Clc’) is coupled to a common signal line (Com); one end of the second storage capacitor (Cs2’) is coupled to the second source-drain of the second transistor (T2’) of the second sub-pixel circuit; the other end of the second storage capacitor (Cs2’) is coupled to the common signal line (Com).

4. The pixel circuit with an ultimate aperture ratio according to claim 3, characterized in that, The row gate signal line (Scan) includes a first row gate signal line (Scan1) and a second row gate signal line (Scan2). The gate of the first transistor (T1) of the first sub-pixel circuit is coupled to the first row gate signal line (Scan1), and the gate of the first transistor (T1') of the second sub-pixel circuit is coupled to the second row gate signal line (Scan2). The first row gate signal line (Scan1) and the second row gate signal line (Scan2) overlap in the vertical direction.

5. The pixel circuit with an ultimate aperture ratio according to claim 3, wherein The first sub-pixel circuit further includes a third transistor (T3). The gate of the third transistor (T3) is coupled to the reset signal line (Reset). The first source-drain of the third transistor (T3) is coupled to one end of the pixel electrode (Clc), and the second source-drain of the third transistor (T3) is coupled to the first data signal line (Data1). The second sub-pixel circuit further includes a third transistor (T3'). The gate of the third transistor (T3') is coupled to the reset signal line (Reset). The first source-drain of the third transistor (T3') is coupled to one end of the second pixel electrode (Clc'), and the second source-drain of the third transistor (T3') is coupled to the second data signal line (Data2).

6. A method for fabricating a pixel circuit with an extreme aperture ratio, which is applied to any one of the pixel circuits described in claims 1 to 5, and is characterized in that, Comprising: Providing a substrate; sequentially forming a light-shielding layer pattern on the substrate and forming a whole-surface barrier layer; Forming a buffer layer on the barrier layer in a whole-surface manner; Providing an active layer on the buffer layer, and forming the channel region, the first end and the second end of the first transistor (T1) of the first sub-pixel circuit by using a heavily doped process. At the same time, the channel region, the first end and the second end of the second transistor (T2) and the channel region, the first end and the second end of the third transistor (T3) are also formed. At the same time, the channel region, the first end and the second end of the first transistor (T1') of the second sub-pixel circuit are formed, and the channel region, the first end and the second end of the second transistor (T2') and the channel region, the first end and the second end of the third transistor (T3') are also formed. Providing a gate insulating layer on the active layer in a whole-surface manner; Forming a gate metal pattern and a row gate signal line on the gate insulating layer. The gate metal pattern constitutes the gates of the first transistor (T1), the second transistor (T2) and the third transistor (T3) of the first sub-pixel circuit. At the same time, the gates of the first transistor (T1'), the second transistor (T2') and the third transistor (T3') of the second sub-pixel circuit are also formed. Providing a second insulating layer on the gate metal pattern in a whole-surface manner; Forming a second metal layer on the second insulating layer, forming a common signal line (Com) on the second metal layer, and forming the upper plate of the first pre-storage capacitor (Cs1-1) and the lower plate of the second pre-storage capacitor (Cs1-2); Forming a third insulating layer on the second metal layer, forming a third metal layer on the third insulating layer, and the third metal layer serves as the upper plate of the second pre-storage capacitor (Cs1-2); The first pre-storage capacitor (Cs1-1) and the second pre-storage capacitor (Cs1-2) overlap and are connected in parallel to form a pre-storage capacitor (Cs1); A fourth insulating layer is formed on the third metal layer, a fourth metal layer is formed on the fourth insulating layer, and a reference signal line (Vref) is formed on the fourth metal layer; A fifth insulating layer is formed on the fourth metal layer, a fifth metal layer is formed on the fifth insulating layer, and a first data signal line (Data1) and a second data signal line (Data2) are formed on the fifth metal layer; A sixth insulating layer is formed over the entire surface of the fifth metal layer, and a first transparent conductive layer is formed on the sixth insulating layer as a storage capacitor (Cs2) of the first sub-pixel circuit and a second storage capacitor (Cs2') of the second sub-pixel circuit; A seventh insulating layer is formed on the first transparent conductive layer, and a second transparent conductive layer is formed on the seventh insulating layer as a pixel electrode (Clc) of the first sub-pixel circuit and a second pixel electrode (Clc') of the second sub-pixel circuit.

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