Package structure

Abstract

A package structure is provided. The package structure includes a substrate, an electronic component, and a termination layer. The substrate is provided with a through hole, the through hole comprises a step type side wall structure, and the step type side wall structure comprises a step surface. The electronic component is supported by the tread of the stepped sidewall structure. The termination layer is disposed on a top surface of the tread.

Description

Technical Field

[0001] The present disclosure generally relates to a packaging structure. Background Art

[0002] Currently, to fabricate a packaging structure for a chip or component having input / output (I / O) terminals on opposite sides, a ceramic substrate may be fabricated to provide a specific structure for the chip or component to be placed therein such that the I / O terminals on the opposite sides of the chip or component can be exposed by the ceramic substrate for electrical connection. However, the cost and difficulty of fabricating a ceramic substrate with a specific structure may be relatively high, and the brittle texture of the ceramic substrate may make the ceramic substrate relatively fragile, thus reducing the yield. Summary of the Invention

[0003] In one or more arrangements, a packaging structure includes a substrate, an electronic component, and a termination layer. The substrate has a through hole that includes a stepped sidewall structure. The electronic component is supported by a tread of the stepped sidewall structure. The termination layer is disposed on a top surface of the tread.

[0004] In one or more arrangements, a packaging structure includes a substrate, an electronic component, and a first conductive element. The substrate has a through hole that extends between a top surface and a bottom surface of the substrate. The electronic component is disposed above the through hole of the substrate, wherein the electronic component has a bottom surface adjacent to the top surface of the substrate and a top surface remote from the top surface of the substrate, and the electronic component includes a first pad adjacent to the top surface of the electronic component. The first conductive element passes through the through hole to connect the first pad to the bottom surface of the substrate.

[0005] In one or more arrangements, a packaging structure includes a substrate and an electronic component. In a cross-sectional view, the substrate has a through hole. In a cross-sectional view, the electronic component is disposed above the through hole and has a first side surface and a second side surface opposite the first side surface, the first side surface vertically overlapping the substrate, and the second side surface not vertically overlapping the substrate. Brief Description of the Drawings

[0006] Aspects of the present disclosure are better understood when read in conjunction with the following detailed description. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for the clarity of the discussion.

[0007] Figure 1A is a cross-section of a packaging structure according to some configurations of the present disclosure.

[0008] Figure 1Bis a cross-section of a package structure according to some configurations of the present disclosure.

[0009] Figure 1C is a top view of a package structure according to some configurations of the present disclosure.

[0010] Figure 2 is a top view of a package structure according to some configurations of the present disclosure.

[0011] Figure 3A is a perspective view of a package structure according to some configurations of the present disclosure.

[0012] Figure 3B is a perspective view of a package structure according to some configurations of the present disclosure.

[0013] Figure 4A is a cross-section of a package structure according to some configurations of the present disclosure.

[0014] Figure 4B is a cross-section of a package structure according to some configurations of the present disclosure.

[0015] Figure 4C is a cross-section of a package structure according to some configurations of the present disclosure.

[0016] Figure 4D is a cross-section of a package structure according to some configurations of the present disclosure.

[0017] Figure 4E is a cross-section of a package structure according to some configurations of the present disclosure.

[0018] Figure 4F is a top view of a package structure according to some configurations of the present disclosure.

[0019] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11 、 Figure 12 and Figure 13 illustrate the various stages of an exemplary method for manufacturing a package structure according to some embodiments of the present disclosure.

[0020] Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed implementation manners

[0021] Figure 1A is a cross-section of the encapsulation structure 1 according to some configurations of the present disclosure. Figure 1B is a cross-section of the encapsulation structure 1 according to some configurations of the present disclosure. Figure 1C is a top view of the encapsulation structure 1 according to some configurations of the present disclosure. In some configurations, Figure 1A shows a cross-section taken along Figure 1C the line 1A-1A' in Figure 1B and Figure 1C shows a cross-section taken along the line 1B-1B' in. The encapsulation structure 1 may include a substrate 10, an electronic component 20, an adhesive layer 30, wires 40 and 42, a spacer structure 50, an adhesive element 51, a protection element 70, and electrical contacts 80. It should be noted that some elements (e.g., wires 40 and 42, pads 210a and 220a, portions 110B and 130B, and protective films 160B and 170B) are shown in dashed lines to indicate relative positions from a side view perspective.

[0022] The substrate 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 10 may include an interconnect structure, which may include a plurality of conductive traces and / or conductive vias. The interconnect structure may include a redistribution layer (RDL) and / or a grounding element. In some configurations, the substrate 10 may include an organic substrate or a lead frame. In some configurations, the substrate 10 may include a ceramic material or a metal plate. In some configurations, the substrate 10 may include a two-layer substrate including a core layer and conductive materials and / or structures disposed on the upper and lower surfaces of the substrate. The substrate 10 may include a semiconductor wafer or an electronic component. The electronic component may be a chip or die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit devices may include active devices such as transistors, and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. In some configurations, the substrate 10 may include one or more conductive elements, surfaces, contacts, or pads.

[0023] In some configurations, the substrate 10 has a surface 101 (also referred to as the "top surface" or "upper surface") and a surface 102 (also referred to as the "bottom surface" or "lower surface") opposite to the surface 101. In some configurations, with reference to Figures 1A to 1C, the substrate 10 further has a plurality of side surfaces (e.g., surfaces 103, 104, 104A, 104B, 106, 106A, 106B, and 107). In some configurations, the substrate 10 further has an intermediate surface (e.g., surface 105). In some configurations, the substrate 10 defines a through-hole T1. In some configurations, the through-hole T1 extends between the surface 101 (or top surface) and the surface 102 (or bottom surface) of the substrate 10. In some configurations, in a cross-sectional view, the through-hole T1 at least includes straight vertical sidewalls or substantially vertical inner sidewalls (e.g., surface 103) that define the through-hole T1 and a stepped sidewall structure T11. In a cross-sectional view, the substantially vertical inner sidewalls (e.g., surface 103) have a substantially flat surface that continuously extends from the surface 101 to the surface 102 of the substrate 10.

[0024] In some configurations, substrate 10 includes base layers 100A and 100B, circuit layers 110 and 130, dielectric layers 120 and 140, and one or more conductive vias 150. In some configurations, base layers 100A and 100B can independently be or include a semiconductor substrate or other suitable materials or components included in substrate 10 as described above. In some configurations, base layers 100A and 100B can independently include a dielectric material, such as polyimide (PI). In some configurations, circuit layer 110 is adjacent to surface 101 (or the top surface), and circuit layer 130 is adjacent to surface 102 (or the bottom surface). In some configurations, circuit layer 110 can be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some configurations, circuit layer 110 includes portions 110A and 110B. Portions 110A and 110B can be electrically disconnected from each other. In some configurations, circuit layer 110 further includes a protective film 160B on portion 110B. The protective film can be or include a metal finish layer, such as a NiAu alloy or other suitable materials. In some configurations, circuit layer 130 can be or include a conductive pad, a conductive layer, a conductive pattern, a conductive portion, etc. In some configurations, circuit layer 130 includes portions 130A and 130B. Portions 130A and 130B can be electrically disconnected from each other. In some configurations, circuit layer 130 further includes a protective film 170B on portion 130B. The protective film can be or include a metal finish layer, such as a NiAu alloy or other suitable materials. In some configurations, package structure 1 further includes a metal layer 190 disposed between electronic component 20 and stepped sidewall structure T11. In some configurations, metal layer 190 is partially embedded in base layers 100A and 100B. In some configurations, metal layer 190 includes a portion exposed to viathole T1 and another portion not exposed to viathole T1. In some configurations, a portion of metal layer 190 is disposed between base layer 100A and base layer 100B. Metal layer 190 can act as a termination layer or a laser blocker for blocking laser penetration through metal layer 190. Metal layer 190 can include a metal material, such as copper (Cu).

[0025] In some configurations, dielectric layers 120 and 140 are disposed on circuit layers 110 and 130, respectively. Dielectric layer 120 and dielectric layer 140 may jointly form an insulating structure or be referred to as an insulating structure. In some configurations, dielectric layer 120 has one or more openings 120T that expose portions of circuit layer 110. In some configurations, protective film 160B is exposed through opening 120T. In some configurations, dielectric layer 140 has one or more openings 140T that expose portions of circuit layer 130. In some configurations, protective film 170B is exposed through opening 140T. In some configurations, conductive via 150 electrically connects surface 101 to surface 102 of substrate 10. In some configurations, conductive via 150 penetrates base layers 100A and 100B. In some configurations, conductive via 150 includes conductive pad 151 and insulating fill layer 153 (e.g., a dielectric layer). In some configurations, one of conductive vias 150 electrically connects portion 110A of circuit layer 110 and portion 130A of circuit layer 130.

[0026] In some configurations, through - hole T1 in substrate 10 is defined by a straight vertical sidewall (e.g., surface 103) and a stepped sidewall structure T11. In some configurations, the straight vertical sidewall includes a generally flat surface (e.g., surface 103) that extends continuously from the top surface (e.g., surface 101) of substrate 10 to the bottom surface (e.g., surface 102).

[0027] In some configurations, substrate 10 has through - hole T1A and through - hole T1B connected to through - hole T1A. In some configurations, through - hole T1 includes through - holes T1A and T1B. Through - hole T1A may be above through - hole T1B and connected to through - hole T1B. Referring Figures 1A to 1C , through - hole T1A may be defined or surrounded by a plurality of lateral sidewalls (e.g., surfaces 104, 104A, 103, and 104B), and through - hole T1B may be defined or surrounded by a plurality of lateral sidewalls (e.g., surfaces 106, 106A, 103, and 106B). In some configurations, through - hole T1A and through - hole T1B share the same vertical sidewall (e.g., surface 103) of substrate 10.

[0028] Referring Figures 1A to 1C, in some configurations, the width of the vias T1A (e.g., the distance between surfaces 104 and 103) is greater than the width of the vias T1B (e.g., the distance between surfaces 106 and 103). In some configurations, the substrate 10 includes a platform 10P protruding from the sidewall of the via T1 (e.g., surface 104). The platform 10P can be referred to as a stepped surface. In some configurations, a termination layer or a laser termination layer (e.g., metal layer 190) is disposed on the top surface of the stepped surface (or platform 10P). In some configurations, the platform 100P protrudes from three sidewalls of the via T1 (e.g., surfaces 104, 104A, and 104B). In some configurations, the vias T1A and the vias T1B together define the platform 10P. In some configurations, the width of the vias T1A is greater than the width of the vias T1B by the width of a platform 10P. In some configurations, the vertical projection of the vias T1B is within the vias T1A. In some configurations, the pad of the substrate 10 (e.g., portion 130A) is outside the vias T1A and the vias T1B. In some configurations, the sidewall of the vias T1A (e.g., surface 104) has a first portion adjacent to the platform 10P and a second portion away from the platform 10P, and the roughness of the first portion is less than the roughness of the second portion.

[0029] In some configurations, the metal layer 190 defines a stepped sidewall structure T11's stepped surface (e.g., surface 105) for supporting the electronic component 20. In some configurations, the metal layer 190 includes a portion exposed by the base layer 100A. In some configurations, the edges of the stepped sidewall structure T11 (e.g., surfaces 106 and / or 107) are generally aligned with the edges of the metal layer 190. In some configurations, the sidewall (e.g., surface 104) defining the via T1 has a first portion adjacent to the metal layer 190 (or termination layer) and a second portion away from the metal layer 190, and the roughness of the first portion is less than the roughness of the second portion. In some configurations, the first portion is formed by a mechanical drilling operation for forming the via T1, the second portion is formed by a laser drilling operation for forming the via T1, and the metal layer 190 serves as a termination layer for the laser drilling operation.

[0030] In some configurations, the stepped sidewall structure T11 has an edge (e.g., surface 107) facing a straight vertical sidewall (e.g., surface 103) and spaced apart from the straight vertical sidewall by a gap G2. In some configurations, the stepped sidewall structure T11 further has a side (e.g., surface 104) facing the electronic component 20 and spaced apart from the electronic component by a gap G1. In some configurations, the gap G1 is less than the gap G2. In some configurations, the stepped sidewall structure T11 may include or be defined by the surfaces 104, 105, and 106.

[0031] In some configurations, the electronic component 20 is disposed at one side of the substrate 10. For example, the electronic component 20 is at one side of the base layer 100B of the substrate 10. In some configurations, the electronic component 20 may be disposed in the through-hole T1 of the substrate 10. In some configurations, the electronic component 20 is partially disposed within the through-hole T1 and partially protrudes beyond the surface 101 of the substrate 10. In some configurations, the electronic component 20 has a surface 211 (also referred to as the "top surface" or "upper surface"), a surface 221 (also referred to as the "top surface" or "upper surface"), a surface 212 opposite to the surface 211 (also referred to as the "bottom surface" or "lower surface"), a surface 222 opposite to the surface 211 or the surface 221 (also referred to as the "bottom surface" or "lower surface"), and at least surfaces 213, 214, 223, and 244 (also referred to as "lateral side surfaces"). In some configurations, the top surface (e.g., the surface 211) and the bottom surface (e.g., the surface 222) of the electronic component 20 are exposed through the through-hole T1. In some configurations, the surface 211 of the electronic component 20 protrudes beyond the surface 101 (or the top surface) of the substrate 10. In some configurations, the surface 211 of the electronic component 20 and the surface 101 of the substrate 10 are at different elevations. In some configurations, the lateral side surfaces (e.g., the surfaces 213, 214, 223, and 244) of the electronic component 20 are separated or spaced apart from the sidewall of the through-hole T1. In some configurations, the thickness of the electronic component 20 is greater than the thickness of the substrate 10. In some configurations, the thickness of the electronic component 20 is greater than the depth of the through-hole T1. The electronic component 20 may be or include a sensor. The sensor may be or include a microelectromechanical system (MEMS) sensor, a temperature sensor, a pressure sensor, a humidity sensor, an inertial force sensor, a chemical substance sensor, a magnetic field sensor, or a combination thereof.

[0032] In some configurations, the electronic component 20 is disposed on or supported by a stepped sidewall structure T11's stepped surface (e.g., platform 10P) within the through-hole T1. In some configurations, the electronic component 20 is disposed on the platform 10P within the through-hole T1. In some configurations, the electronic component 20 has a first active surface (e.g., surface 211) and a second active surface (e.g., surface 222) opposite the first active surface, and the first active surface (or surface 211) and the second active surface (or surface 222) are exposed through the through-hole T1A and the through-hole T1B, respectively. In some configurations, the first active surface (or surface 211) protrudes beyond the through-hole T1. In some configurations, the electronic component 20 is disposed within the through-hole T1A and does not extend into the through-hole T1B. In some configurations, the electronic component 20 includes pads 210a and 220a (also referred to as "conductive pads" or "conductive terminals"), which are within the through-hole T1 and wire-bonded to the substrate 10. In some configurations, the pads 210a and the pad 220a face opposite directions. In some configurations, the electronic component 20 includes a device 210 (also referred to as a "chip" or "electronic device"), a device 220 (also referred to as a "chip" or "electronic device") stacked with the first device 210, and a connection element 60 between the device 210 and the device 220 and connecting the device 210 and the device 220. In some configurations, the pad 210a is disposed on a portion of the device 210 exposed by the device 220. In some configurations, the pad 220a is disposed on a portion of the device 220 exposed by the device 210. In some configurations, the connection element 60 includes an insulating adhesive layer (e.g., die attach film (DAF)) or a conductive film (e.g., anisotropic conductive film (ACF)).

[0033] In some configurations, the device 210 includes a sensing element 210S adjacent to the surface 211. In some configurations, the sensing element 210S is exposed by the surface 211 of the device 210. In some configurations, the sensing element 210S is exposed by the through-hole T1A of the substrate 10. In some configurations, the device 210 includes an active surface (e.g., surface 211) and a backside surface (e.g., surface 212) connected to the connection element 60. In some configurations, the pad 210a of the device 210 is wire-bonded to the substrate 10. The device 210 may include an interconnect element (e.g., a conductive via) connecting the sensing element 210S to the pad 210a.

[0034] In some configurations, device 220 includes a sensing element 220S adjacent to surface 222. In some configurations, sensing element 220S is exposed by surface 222 of device 220. In some configurations, sensing element 220S is exposed by via hole T1B of substrate 10. In some configurations, device 220 includes an active surface (e.g., surface 222) and a back surface (e.g., surface 221) connected to connection element 60. In some configurations, pad 220a of device 220 is wire bonded to substrate 10. Device 220 may include an interconnect element (e.g., a conductive via) that connects sensing element 220S to pad 220a.

[0035] Adhesive layer 30 may be disposed between electronic component 20 and substrate 10. In some configurations, adhesive layer 30 connects electronic component 20 to stepped sidewall structure T11. In some configurations, adhesive layer 30 connects or adheres electronic component 20 to platform 10P. In some configurations, adhesive layer 30 is partially within via hole T1A and partially within via hole T1B. In some configurations, adhesive layer 30 contacts the sidewalls of via hole T1A (e.g., surface 104) and the sidewalls of via hole T1B (e.g., surface 106). In some configurations, adhesive layer 30 is further disposed in gap G1. In some configurations, adhesive layer 30 further fills gap G2. In some configurations, adhesive layer 30 further contacts portions of the edges of stepped sidewall structure T11 (e.g., surfaces 106 and 107). In some configurations, adhesive layer 30 further contacts the straight vertical sidewalls of via hole T1 (e.g., surface 103). In some configurations, pads 210a and 220a are exposed by adhesive layer 30. In some configurations, metal layer 190 includes a portion exposed by substrate 10, and adhesive layer 30 is disposed on the exposed portion of metal layer 190. In some configurations, metal layer 190 includes a portion exposed by base layer 100A and contacting adhesive layer 30. In some configurations, adhesive layer 30 may be or include a bottom filler or encapsulant. Adhesive layer 30 may include epoxy resin, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material containing silicone dispersed therein, or a combination thereof.

[0036] Wire 40 may connect electronic component 20 to substrate 10. In some configurations, device 220 is electrically connected to substrate 10 by wire 40. In some configurations, wire 40 protruding beyond surface 101 of substrate 10 is exposed by adhesive layer 30. In some configurations, wire 40 electrically connects pad 220a of device 220 to surface 101 of substrate 10. In some configurations, wire 40 electrically connects pad 220a of device 220 to portion 110B of circuit layer 110 of protective film 160B and substrate 10. Wire 40 may be referred to as a conductive element.

[0037] The wire 42 can connect the electronic component 20 to the substrate 10. In some configurations, the device 210 is electrically connected to the substrate 10 via the wire 42. In some configurations, the wire 42 is spaced apart from the adhesive layer 30. In some configurations, the wire 42 connects or electrically connects the pad 210a of the device 210 to the surface 102 (or bottom surface) of the substrate 10. In some configurations, the wire 42 electrically connects the pad 210a of the device 210 to a portion 130B of the circuit layer 130 of the protective film 170B and the substrate 10. In some configurations, a portion of the adhesive layer 30 horizontally overlaps a portion of the wire 42. In some configurations, the wire 42 connects the active surface (e.g., surface 222) of the electronic component 20 to a pad (e.g., portion 130A) of the substrate 10. In some configurations, the wire 42 is partially within the vias T1B. The wire 42 can be referred to as a conductive element.

[0038] The spacer structure 50 can be disposed around the wire 40. In some configurations, the elevation of the top surface 501 of the spacer structure 50 is higher relative to the surface 101 of the substrate 10 than the elevation of the top end 401 of the wire 40. In some configurations, the spacer structure 50 is disposed on the surface 101 of the substrate 10 and is configured to protect the electronic component 20 from damage. In some configurations, the spacer structure 50 is disposed on the surface 101 of the substrate 10 and defines a space for accommodating the wire 40 and a portion of the electronic component 20 that protrudes beyond the surface 101 of the substrate 10. In some configurations, the spacer structure 50 is connected to (or electrically connected to) ground via the conductive via 150. The spacer structure 50 can act as a shielding element configured to reduce electromagnetic interference (EMI). In some configurations, the spacer structure 50 can be referred to as or include a spacer, a metal spacer, an interposer, etc. The spacer structure 50 can be or include a metal frame, a metal wall structure, or a metal cover. In some embodiments, the spacer structure 50 is made of or includes a conductive material, including, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or a mixture, alloy, or other combination thereof.

[0039] The bonding element 51 can connect the spacer structure 50 to the substrate 10. In some configurations, the bonding element 51 is at least partially within the opening 120T of the dielectric layer 120. In some configurations, the bonding element 51 is formed of or includes a conductive material. The bonding element 51 can be or include a conductive layer (e.g., a metal layer), a conductive adhesive (e.g., silver paste or silver gel), or a combination thereof. The bonding element 51 can be or include a welding material. In some configurations, the bonding element 51 electrically connects the spacer structure 50 to a portion 110A of the circuit layer 110.

[0040] The protection element 70 may encapsulate a portion of the wire 42. In some configurations, the protection element 70 encapsulates the bottom end 422 of the wire 42. In some configurations, the protection element 70 further covers at least a portion of the protective film 170B. As Figure 1C shown, in some configurations, the protection element 70 contacts the adhesive layer 30. In some configurations, the protection element 70 has a non-uniform thickness along a direction generally parallel to the surface 1001 of the substrate 10. In some configurations, the protection element 70 protrudes beyond the bottom surface (e.g., surface 1002) of the substrate 10. The protection element 70 may comprise an encapsulant. The encapsulant may comprise an epoxy resin with fillers, a molding material (e.g., an epoxy molding compound or other molding material), polyimide, phenolic compounds or materials, a material with silicone dispersed therein, or a combination thereof. In some configurations, the protection element 70 may be or comprise a sealing gel. In some configurations, the protection element 70 may be or comprise a sealant.

[0041] The electrical contact 80 may be disposed on the surface 102 of the substrate 10. In some configurations, the elevation of the bottom surface 802 of the electrical contact 80 relative to the surface 102 of the substrate 10 is lower than the elevation of the bottom surface 702 of the protection element 70. In some configurations, the elevation of the bottom surface 802 of the electrical contact 80 relative to the surface 102 of the substrate 10 is lower than the elevation of the bottom end 422 of the wire 42. In some configurations, the electrical contact 80 is electrically connected to the circuit layer 130 of the substrate 10. In some embodiments, the electrical contact 80 comprises a controlled collapse chip connection (C4) bump, a ball grid array (BGA), or a land grid array (LGA).

[0042] The conductive layer, pad, post, portion, via, liner, and / or terminal may independently comprise a conductive material such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or alloys thereof. The dielectric layer may independently comprise an organic material, a solder mask, PI, ABF, one or more molding materials, one or more prepreg composite fibers (e.g., prepreg materials), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, etc.

[0043] In some cases of manufacturing a ceramic substrate to provide a specific structure for electronic components to be disposed therein, such that I / O terminals on opposite sides of the electronic components can be exposed by the ceramic substrate for electrical connection. However, the cost and difficulty of manufacturing a ceramic substrate with a specific structure may be relatively high, and the brittle texture of the ceramic substrate may make the ceramic substrate relatively fragile, thus reducing the yield. To address the above problems, a plastic substrate can be provided, which includes a specific structure for electronic components to be disposed therein. The plastic substrate can be formed by the following steps: a top cavity and a bottom cavity can be formed from the top surface and the bottom surface of the plastic substrate respectively to connect the top cavity and the bottom cavity, thereby forming a through-hole with a platform defined by the cavities in the plastic substrate, such that the electronic components can be disposed on the platform in the through-hole of the plastic substrate. However, during the two-step cavity formation process, it is relatively difficult to precisely control the depths of the top cavity and the bottom cavity from opposite directions, and thus variations in the cavity depths may result in an uneven elevation of the already formed platform, which may also reduce the yield.

[0044] According to some configurations of the present disclosure, the substrate includes two through-holes sharing the same straight vertical sidewalls, which are not formed by drilling from opposite surfaces of the substrate, and the electronic components are disposed on the platform formed by the two through-holes. The process for forming the through-holes is relatively simple and simplified (e.g., by performing a drilling operation from the same surface of the substrate), the problem of difficultly controlling the depths of multiple cavities from opposite surfaces can be omitted, thus the yield can be increased and the cost can be reduced. Additionally, two sides or surfaces of the electronic components can be exposed by the opposite openings of the through-holes, such that the two sides or surfaces of the electronic components can be electrically connected to conductive elements (e.g., wires).

[0045] Furthermore, according to some configurations of the present disclosure, the electronic components are adhered to the platform and the sidewalls of the through-holes by an adhesive layer. The material of the adhesive layer can flow into the relatively narrow gap (e.g., gap G1) between the electronic components and the sidewalls of the through-holes, and then cures during the manufacturing process to form the adhesive layer. Thus, the gap can be relatively small, such that the overall size of the package structure can be reduced. Additionally, the material of the adhesive layer can overflow to fill the gap (e.g., gap G2) between the edge of the platform and the sidewalls, such that the adhesion force between the electronic components and the substrate can be increased without increasing the package size, which further helps to increase the reliability and yield of the package structure.

[0046] In addition, according to some configurations of the present disclosure, through the design of the gap (e.g., gap G2) between the edge of the platform and the sidewalls, space tolerance is further provided when the electronic components are disposed in the through-holes. Thus, when the electronic components are disposed in the through-holes, the electronic components can be prevented from accidentally hitting the sidewalls of the through-holes (e.g., surface 103). Therefore, the yield can be improved.

[0047] In addition, according to some configurations of the present disclosure, the spacer structure is higher than the electronic components and wires above the top surface of the substrate, such that the spacer structure can protect the electronic components and wires from damage. Additionally, the spacer structure can be further electrically connected to ground, such that the spacer structure can further act as an EMI shielding element for the electronic components without the need to dispose or install an additional EMI shielding structure. Thus, the electrical performance of the package structure can be improved without increasing the package size.

[0048] In addition, according to some configurations of the present disclosure, the electrical contacts are higher than the protection elements and wires below the bottom surface of the substrate. Thus, in addition to being electrically connected to external components, the electrical contacts can further protect the protection elements and wires from damage. Accordingly, the reliability of the package structure can be improved without increasing the package size.

[0049] Figure 2 is a top view of a package structure 2 according to some configurations of the present disclosure. Figure 2 The package structure 2 illustrated in Figure 1C is similar to the package structure in Figure 1A and the differences therebetween are as follows. In some configurations, Figure 2 shows a cross-section taken along line 1A-1A' in Figure 1B and Figure 2 shows a cross-section taken along line 1B-1B' in

[0050] In some configurations, the adhesive layer 30 is spaced apart from the protection element 70.

[0051] Figure 3A is a perspective view of a package structure 3A according to some configurations of the present disclosure. In some configurations, Figure 1A shows a cross-section taken along line 1A-1A' in Figure 3A and Figure 1B shows a cross-section taken along line 1B-1B' in Figure 3A In some configurations, Figure 3A shows Figure 1C a perspective view of the structure illustrated in

[0052] In some configurations, the adhesive layer 30 is connected to the protection element 70. In some configurations, the adhesive layer 30 in combination with the protection element 70 surrounds the electronic component 20.

[0053] Figure 3B is a perspective view of a package structure 3B according to some configurations of the present disclosure. In some configurations, Figure 1A shows a cross-section taken along line 1A-1A' in Figure 3B and Figure 1B shows a cross-section taken along line 1B-1B' in Figure 3BThe cross-section taken along line 1B-1B' in. In some configurations, Figure 3B shows Figure 2 A perspective view of the structure illustrated in.

[0054] In some configurations, the adhesive layer 30 is separated from the protective element 70. In some configurations, a portion of the straight vertical sidewall (e.g., surface 103) of the through-hole T1 is exposed by the gap between the adhesive layer 30 and the protective element 70.

[0055] Figure 4A Is a cross-section of the encapsulation structure 4A according to some configurations of the present disclosure. Figure 4A The encapsulation structure 4A illustrated in is similar to Figure 1A The encapsulation structure in, and the differences therebetween are as follows.

[0056] In some configurations, the device 220 contacts the sidewall (e.g., surface 104) of the through-hole T1A. In some configurations, there is no gap (e.g., gap G1) between the device 220 and the sidewall (e.g., surface 104) of the through-hole T1A.

[0057] Figure 4B Is a cross-section of the encapsulation structure 4B according to some configurations of the present disclosure. Figure 4B The encapsulation structure 4B illustrated in is similar to Figure 1B The encapsulation structure in, and the differences therebetween are as follows.

[0058] In some configurations, the substrate 10 includes base layers 100A, 100B, and 100C. In some configurations, the base layer 100C may be or include a core layer, and the hardness of the core layer is greater than the hardness of the base layers 100A and 100B. In some configurations, the device 220 contacts the sidewall (e.g., surface 104) of the through-hole T1A. In some configurations, there is no gap (e.g., gap G1) between the device 220 and the sidewall (e.g., surface 104) of the through-hole T1A. In some configurations, the base layers 100A, 100B, and 100C may independently include a dielectric material.

[0059] Figure 4C Is a cross-section of the encapsulation structure 4C according to some configurations of the present disclosure. Figure 4C The encapsulation structure 4C illustrated in is similar to Figure 1B The encapsulation structure in, and the differences therebetween are as follows.

[0060] In some configurations, the substrate 10 includes base layers 100A, 100B, and 100C. In some configurations, the base layer 100C may be or include a core layer, and the hardness of the core layer is greater than the hardness of the base layers 100A and 100B.

[0061] Figure 4Dis a cross-section of the package structure 4D according to some configurations of the present disclosure. Figure 4D The package structure 4D described in Figure 1B is similar to the package structure in

[0062] In some configurations, the electronic component 20 is a single device. In some configurations, the electronic component 20 includes a sensing element 221S adjacent to the surface 211 and a sensing element 220S adjacent to the surface 222. In some configurations, the sensing element 210S is exposed by the surface 211 of the electronic component 20, and the sensing element 220S is exposed by the surface 222 of the electronic component 20. In some configurations, the sensing elements 210S and 220S are exposed by the through-hole T1 of the substrate 10.

[0063] In some configurations, the electronic component 20 includes at least pads 210a and 220a (also referred to as "conductive pads" or "conductive terminals"). In some configurations, the pad 210a is on the surface 211 (or top surface) of the electronic component 20, and the pad 220a is on the surface 222 (or bottom surface) of the electronic component 20. In some configurations, the pad 210a protrudes beyond the surface 211 of the electronic component 20, and the pad 220a protrudes beyond the surface 222 of the electronic component 20. In some configurations, the pad 210a is electrically connected to the surface 101 of the substrate 10, and the pad 220a is electrically connected to the surface 102 of the substrate 10.

[0064] Figure 4E is a cross-section of the package structure 4E according to some configurations of the present disclosure. Figure 4F is a top view of the package structure 4E according to some configurations of the present disclosure. In some configurations, Figure 4E is taken along Figure 4F the line 4E-4E' in Figure 4E and Figure 4F The package structure 4E described in Figures 1A to 1C is similar to the package structure in

[0065] In some configurations, the substrate 10 has an upper surface 1001 and a lower surface 1002 opposite the upper surface 1001. The upper surface 1001 may be the top surface of the base layer 100A exposed by the dielectric layer 120. The lower surface 1002 may be the bottom surface of the base layer 100A exposed by the dielectric layer 140. The dielectric layer 120 and the dielectric layer 140 may jointly form an insulating structure or are referred to as an insulating structure. In some configurations, the insulating structure (or the dielectric layer 120) of the substrate 10 and the upper surface 1001 jointly define a stepped structure (e.g., a stepped sidewall structure T11) for accommodating the electronic component 20. In some configurations, the adhesive layer 30 is between the electronic component 20 and the stepped structure (or the stepped sidewall structure T11). In some configurations, the insulating structure (or the dielectric layer 140) of the substrate 10 and the lower surface 1002 jointly define a stepped structure (e.g., a stepped sidewall structure T12) for accommodating a pad (e.g., the portion 130B) electrically connected to the electronic component 20.

[0066] In some configurations, the electronic component 20 has an upper surface (e.g., the surface 212) away from the substrate 10 and a lower surface (e.g., the surface 221) closer to the substrate 10 than the upper surface. In some configurations, the pad 210a is on the upper surface (e.g., the surface 212). In some configurations, in a cross-sectional view, the electronic component 20 includes an upper protrusion 210P and a lower protrusion 220P opposite the upper protrusion 210P. In some configurations, the pad 210a is disposed on the surface 212 of the upper protrusion 210P facing the substrate 10. In some configurations, the pad 220a is disposed on the surface 221a of the lower protrusion 220P facing away from the substrate 10. In some configurations, the elevation of the pad 210a is higher than the elevation of the pad 220a relative to the substrate 10. In some configurations, the electronic component 20 is disposed at one side of the substrate 10. In some configurations, the electronic component 20 has a side surface 220e and a side surface 210e opposite the side surface 220e. In some configurations, the side surface 220e vertically overlaps with the substrate 10 (or the base layer 100A), and the side surface 210e vertically overlaps with the through hole T1. In some configurations, the side surface 210e does not vertically overlap with the substrate 10. Refer to Figure 4F , in some configurations, the width 20W of the electronic component 20 is greater than the width T1W of the through hole T1.

[0067] In some configurations, wire 40 connects pad 220a to upper surface 1001 of substrate 10 without passing through through-via T1. In some configurations, wire 42 passes through through-via T1 (or through-via T1A) to connect pad 210a to lower surface 1002 of substrate 10. In some configurations, the length of wire 42 is longer than the length of wire 40. In some configurations, the curvature change of wire 42 is greater than the curvature change of wire 40. As used herein, the term "curvature change" may refer to a change in the height or elevation of a wire within a predetermined horizontal distance. The term "curvature change" may also reflect the slope of a wire.

[0068] In some configurations, the protection element 70 encapsulates the conductive line 42. In some configurations, the elevation of the lower surface (e.g., bottom surface 702) of the protection element 70 is lower than the elevation of the lower surface 1002 of the substrate 10 relative to the upper surface (e.g., surface 212) of the electronic component 20. In some configurations, the protection element 70 includes a portion 710 disposed outside the through-hole T1 and a portion 720 disposed within the through-hole T1. In some configurations, the height or thickness of the portion 710 is greater than the height or thickness of the portion 720 in a direction generally perpendicular to the lower surface 1002 (also referred to as the "first direction"). In some configurations, an edge 710e of the portion 710 of the protection element 70 protrudes beyond an edge (e.g., side surface 210e) of the electronic component 20 in a direction generally parallel to the lower surface 1002 (also referred to as the "second direction") (or in a second direction generally perpendicular to the first direction). In some configurations, the protection element 70 has an irregularly curved surface.

[0069] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11 、 Figure 12 and Figure 13 Various stages of an exemplary method for manufacturing a package structure 1 according to some embodiments of the present disclosure are described.

[0070] refer to Figure 5A and Figure 5B , Figure 5A It is along Figure 5BThe cross-section of line 5A - 5A' in []. A substrate 10 can be provided that includes base layers 100A and 100B, circuit layers 110 and 130, dielectric layers 120 and 140, one or more conductive vias 150, and a metal layer 190A. In some configurations, the metal layer 190A is inserted between the base layer 100A and the base layer 100B.

[0071] Reference Figure 6A and Figure 6B , Figure 6A is a cross-section taken along Figure 6B line 6A - 6A' in []. A through-hole 100T can be formed that penetrates the base layers 100A and 100B, the dielectric layers 120 and 140, and the metal layer 190A. In some configurations, a portion of the metal layer 190A is removed to form a metal layer 190 that has a U-shape when viewed from a top-down perspective. In some configurations, the metal layer 190 is embedded in the base layers 100A and 100B. The through-hole 100T can be formed by mechanical drilling.

[0072] Reference Figure 7A , Figure 7B and Figure 7C , Figure 7A is a cross-section taken along Figure 7C line 7A - 7A' in [], and Figure 7B is a cross-section taken along Figure 7C line 7B - 7B' in []. A portion of the base layer 100A can be further removed to widen the top portion of the through-hole 100T, thereby forming an upper through-hole 100T1 within the base layer 100A, and the lower portion of the through-hole 100T forms a lower through-hole 100T2 within the base layer 100B. The upper through-hole 100T1 can be formed by mechanical drilling. The drilling can stop before the metal layer 190 is exposed.

[0073] Reference Figure 8A , Figure 8B and Figure 8C , Figure 8A is a cross-section taken along Figure 8C line 8A - 8A' in [], and Figure 8B is a cross-section taken along Figure 8CThe cross-section taken by the line 8B-8B' in. Additional portions of the base layer 100A may be further removed to expose the metal layer 190, thereby forming a via hole T1A within the base layer 100A, and a lower portion of the lower via hole 100T2 forms a via hole T1B within the base layer 100B. The additional portions of the base layer 100A may be removed by laser drilling. The metal layer 190 may act as a laser blocker to prevent further removal of the portion of the base layer 100B below the metal layer 190 by laser drilling. In some configurations, portions of the base layer 100B exposed by the metal layer 190 may be removed by laser drilling to form a gap G2 between the straight vertical sidewall (e.g., surface 103) of the via hole T1B and the edge (e.g., surface 107) of the base layer 100B. Thus, a via hole T1 including the via holes T1A and T1B may be formed. Portions of the metal layer 190 may be exposed to the via hole T1. Portions of the metal layer 190 may define a platform 10P or a stepped surface (e.g., surface 105) for supporting electronic components.

[0074] According to some configurations of the present disclosure, the via hole 100T1 is formed by mechanical drilling to remove a relatively large portion of the base layer 100A to preliminarily define the scope of the via hole T1A, and then the remaining portion of the base layer 100A is further removed by laser drilling to form a via hole T1A that precisely terminates at the metal layer 190 (i.e., the laser blocker). Mechanical drilling can accelerate the process of partially removing the base layer 100A, and mechanical drilling after laser drilling can precisely define the end or bottom of the via hole T1A. Thus, the overall time for forming the via hole T1A can be reduced, and the depth of the via hole T1A can be precisely controlled.

[0075] Reference Figure 9A and Figure 9B , Figure 9A illustrates the stage after the stage illustrated in Figure 8A and Figure 9B illustrates the stage after the stage illustrated in Figure 8B An electronic component 20 including devices 210 and 220 and pads 210a and 220a may be disposed on the platform 10P in the via hole T1. In some configurations, the electronic component 20 may be connected or adhered to the platform 10P through an adhesive layer 30.

[0076] Reference Figure 10A and Figure 10B , Figure 10A illustrates the stage after the stage illustrated in 9A, and Figure 10B illustrates the stage after the stage illustrated in Figure 9B. Wires 40 may be provided or formed over surface 101 of substrate 10 to connect circuit layer 110 to pads 220a of electronic component 20, and spacer structure 50 may be adhered or attached to substrate 10. In some configurations, spacer structure 50 is adhered to portion 110A of circuit layer 110 exposed by opening 120T of dielectric layer 120 via adhesive element 51. In some configurations, a temporary carrier 1100 is further disposed on spacer structure 50.

[0077] refer to Figure 11 , Figure 11 Description Figure 10B The stage following the stage described in . Reversible Figure 10A and 10B The structure described in the embodiment of the present invention is shown in FIG. 1 , and the temporary carrier 1100 can serve as a temporary support carrier for the structure to undergo subsequent operations. Next, a conductive line 42 can be provided or formed over the surface 102 of the substrate 10 to connect the circuit layer 130 to the pad 210a of the electronic component 20.

[0078] refer to Figure 12 , a protective element 70 may be formed to encapsulate a portion of the conductive line 42, and an electrical contact 80 may be disposed or formed on the surface 102 of the substrate 10. In some configurations, the protective element 70 may be formed by a liquid crystal drop casting (ODF) process. In some configurations, the protective element 70 may be or include a sealing gel. In some configurations, the protective element 70 may be or include a sealant.

[0079] refer to Figure 13 , reversible Figure 12 The structure described in the embodiment of the present invention can be formed, and the temporary carrier 1100 can be removed. Figures 1A to 1C The packaging structure 1 described in .

[0080] Unless otherwise specified, spatial descriptions such as "above," "below," "up," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "above," "below," etc., are indicated relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that embodiments of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not deviated by such arrangements.

[0081] As used herein, the terms "approximately", "substantially", "substantive", "about", and "circa" are used to describe and account for minor variations. When used in connection with an event or circumstance, these terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. For example, when used in connection with a numerical value, these terms can refer to a range of variation that is less than or equal to ±10% of the stated numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first numerical value is within a range of variation that is less than or equal to ±10% of a second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first numerical value can be considered to be "substantially" the same as or equal to the second numerical value. For example, "substantially" vertical can refer to an angular range of variation that is less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0082] If the displacement amount between two surfaces is not greater than 5 μm, not greater than 2 μm, not greater than 1 μm, or not greater than 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement amount between the highest point and the lowest point of a surface does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm, or does not exceed 0.5 μm, then the surface can be considered to be substantially flat.

[0083] As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" can include plural referents.

[0084] As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to conduct an electric current. A conductive material is a material that presents little or no resistance to the flow of an electric current. One unit of measure for conductivity is Siemens per meter (S / m). Generally, a conductive material is a material having a conductivity greater than about 104 S / m, such as at least 10 5 S / m or at least 10 6 S / m. The conductivity of a material sometimes varies with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0085] In addition, quantities, ratios, and other numerical values are sometimes presented in a range format in this document. It should be understood that such range formats are used for convenience and brevity and should be interpreted flexibly as encompassing not only the explicitly specified values defining the limits of the range, but also all individual values or sub-ranges subsumed within that range as if each value and sub-range were explicitly specified.

[0086] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not restrictive. Those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The figures may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproductions and the actual equipment in the present disclosure. There may be other embodiments not specifically described in the present disclosure. The specification and drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present disclosure. All such modifications are considered to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, sub-divided, or re-ordered without departing from the teachings of the present disclosure to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. An encapsulation structure, comprising: A substrate having a through hole, the through hole including a stepped sidewall structure, the stepped sidewall structure including a stepped surface; An electronic component supported by the stepped surface of the stepped sidewall structure; and A termination layer disposed on the top surface of the stepped surface.

2. The encapsulation structure according to claim 1, wherein the termination layer includes a first portion exposed to the through hole and a second portion not exposed to the through hole.

3. The encapsulation structure according to claim 2, wherein the edge of the stepped surface is substantially aligned with the edge of the termination layer.

4. The encapsulation structure according to claim 1, wherein the sidewall defining the through hole has a first portion adjacent to the termination layer and a second portion remote from the termination layer, and the roughness of the first portion is less than the roughness of the second portion.

5. The encapsulation structure according to claim 1, wherein the encapsulation structure further includes a substantially vertical inner sidewall that defines the through hole and has a substantially flat surface that continuously extends from the top surface of the substrate to the bottom surface in a cross-sectional view.

6. The encapsulation structure according to claim 1, wherein the electronic component is partially disposed within the through hole and partially protrudes beyond the surface of the substrate.

7. An encapsulation structure, comprising: A substrate having a through hole extending between the top surface and the bottom surface of the substrate; An electronic component disposed above the through hole of the substrate, wherein the electronic component has a lower surface adjacent to the top surface of the substrate and an upper surface remote from the top surface of the substrate, and the electronic component includes a first pad adjacent to the upper surface of the electronic component; And A first conductive element passing through the through hole to connect the first pad to the bottom surface of the substrate.

8. The encapsulation structure according to claim 7, further comprising a protective element encapsulating the first conductive element.

9. The encapsulation structure according to claim 8, wherein the protective element includes a first portion disposed outside the through hole and a second portion within the through hole.

10. The encapsulation structure according to claim 9, wherein in a first direction substantially perpendicular to the bottom surface of the substrate, the thickness of the first portion is greater than the thickness of the second portion.

11. The encapsulation structure according to claim 8, wherein the protective element has a non-uniform thickness along a direction substantially parallel to the top surface of the substrate.

12. The encapsulation structure according to claim 10, wherein the edge of the first portion of the protective element protrudes beyond the edge of the electronic component in a second direction substantially perpendicular to the first direction.

13. The encapsulation structure according to claim 8, wherein the protective element protrudes beyond the bottom surface of the substrate.

14. The encapsulation structure according to claim 8, wherein in a cross-sectional view, the electronic component includes an upper protrusion and a lower protrusion opposite to the upper protrusion.

15. The encapsulation structure according to claim 14, wherein the first gasket is disposed on the surface of the upper protrusion facing the substrate.

16. The encapsulation structure according to claim 15, wherein the electronic component further includes a second gasket, and the second gasket is disposed on the surface of the lower protrusion facing away from the substrate.

17. The encapsulation structure according to claim 16, further comprising a second conductive element that connects the second gasket to the top surface of the substrate without passing through the through hole.

18. An encapsulation structure, wherein in a cross-sectional view, the encapsulation structure includes: a substrate having a through hole; and an electronic component disposed above the through hole, wherein the electronic component has a first side surface and a second side surface opposite to the first side surface, the first side surface vertically overlaps with the substrate, and the second side surface does not vertically overlap with the substrate.

19. The encapsulation structure according to claim 18, further comprising an insulating structure, wherein the insulating structure and the upper surface of the substrate commonly define a first stepped structure for disposing the electronic component.

20. The encapsulation structure according to claim 19, wherein the insulating structure and the lower surface of the substrate commonly define a second stepped structure for disposing a gasket electrically connected to the electronic component.

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