Dual cold mosfet for low rdson and low thermal power

Abstract

A dual cooled MOSFET for low RDSon and low thermal power is presented. The semiconductor package includes a first terminal exposed on a backside surface of the semiconductor package, one or more further terminals extending to an exterior of the semiconductor package, and a second terminal exposed on a top surface of the semiconductor package. The second terminal includes a metal block serving as the second terminal. The metal block is electrically connected to the first terminal via one or more curved ends of the metal block. The metal block includes one or more stress relief features.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages including a dual-cooling configuration, particularly metal-oxide-semiconductor field effect transistors (MOSFETs). The present disclosure further relates to a process for manufacturing such semiconductor packages. Background Art

[0002] Power MOSFET packages and products with low RDSon, low inductance, and low thermal resistance are becoming increasingly important, for example, in the automotive industry.

[0003] One way to improve the thermal resistance of a product is to add a slug on the clip source interconnect and then expose it on the top surface of the package. The product resistance and inductance can be achieved by flip-chip die (source down) such that the source unit is directly attached to the PCB board. On the other hand, a source-down configuration with an exposed drain terminal on the top surface of the package generally offers more benefits in terms of thermal performance.

[0004] However, introducing low thermal resistance poses additional challenges in terms of exposing the top surface of the package. Known methods of exposing a slug on the top surface of the package typically involve additional process steps such as package grinding, or require additional materials and systems such as film-assisted molding. In addition, known methods introduce a risk of damaging the package due to the lack of stress relief during molding and package grinding. Summary of the Invention

[0005] An overview of aspects of the specific examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide a brief overview of these particular embodiments to the reader and are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may cover a number of aspects and / or combinations of aspects that may not be set forth.

[0006] The present disclosure aims to overcome the disadvantages pointed out in the background art section.

[0007] According to an aspect of the present disclosure, a semiconductor package is provided. The semiconductor package may include a first terminal exposed on a back surface of the semiconductor package. The semiconductor package may further include one or more additional terminals extending outside the semiconductor package. The semiconductor package may further include a second terminal exposed on a top surface of the semiconductor package. The second terminal may include a slug serving as the second terminal. The slug may be electrically connected to the first terminal via one or more bent ends of the slug. The slug may include one or more stress relief features.

[0008] In one embodiment, one or more stress relief features may include one or more of the following: a half-cut feature at the transition from the top surface of the metal block to one or more bent ends; a half-cut feature located on the side of one or more bent ends; a groove or similar feature.

[0009] In one embodiment, one or more bent ends may be bent at an angle with respect to the top surface of the metal block, preferably at a perpendicular angle, and optionally include portions that further bend outward.

[0010] In one embodiment, one or more bent ends may form feet of the metal block.

[0011] In one embodiment, the first terminal may be formed by a paddled die. The paddled die may include one or more recessed surfaces for receiving one or more bent ends. One or more bent ends may be solder printed onto one or more recessed surfaces.

[0012] In one embodiment, the first surface of the metal block may be exposed on the top surface of the semiconductor package, while the second surface of the metal block may face the semiconductor silicon die before molding.

[0013] In one embodiment, the first surface of the metal block may be exposed on the top surface of the semiconductor package by direct or indirect contact with the molding cavity.

[0014] In one embodiment, if the first surface of the metal block does not contact the top molding cavity, it may have been exposed using a package grinding process.

[0015] In one embodiment, the first terminal may include a first surface exposed at the back of the semiconductor package. The first terminal may include a second surface that serves as a die pad for a flip-chip semiconductor die.

[0016] In one embodiment, the semiconductor package may further include one or more additional terminals that extend outside the semiconductor package and are formed as gull wings or microleads, or leadless, or a combination of both geometries.

[0017] In one embodiment, the first terminal and the second terminal may be source terminals. One or more additional terminals may include one or more drain terminals and one or more gate terminals.

[0018] In one embodiment, the first terminal and the second terminal may be drain terminals. One or more additional terminals may include one or more source terminals and one or more gate terminals.

[0019] In one embodiment, a semiconductor package can form a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0020] According to aspects of the present disclosure, a method of manufacturing a semiconductor package having one or more of the above-described features is provided. The method can include providing die pads. The method can further include dispensing or printing solder on the die pads. The method can further include die attachment, optionally including flip-chip die attachment. The method can further include dispensing or printing solder on the die surface or the back surface of the die. The method can further include attaching one or more additional terminals. The method can further include attaching a metal block to the die pads by inserting one or more bent ends of the metal block into one or more recessed surfaces of the die pads and solder printing the one or more bent ends to the die pads. The method can further include molding while exposing a first surface of the metal block.

[0021] In one embodiment, the method can further include providing one or more stress relief features on the metal block in one or more of the following forms: a half-cut feature at the transition from the top surface of the metal block to one or more bent ends; a half-cut feature located on the sides of one or more bent ends; and a groove or similar feature.

[0022] The semiconductor package of the present disclosure can be used in a source-down or drain-down configuration, i.e., a flip-chip die. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic diagrams, in which corresponding reference numerals represent corresponding components, wherein:

[0024] Figures 1A to 1E The top of a first example semiconductor package is shown, where Figure 1A A 2D top view is shown, Figure 1B A 3D top view is shown, Figure 1C A 2D top view of the interior is shown, Figures 1D to 1E A 3D top view of the interior is shown;

[0025] Figures 2A to 2C The back of a first example semiconductor package is shown, where Figure 2A A 2D rear view is shown, Figure 2B A 3D rear view is shown, Figure 1C A 3D rear view of the interior is shown;

[0026] Figures 3A to 3E The top of a second example semiconductor package is shown, where Figure 3A A 2D top view is shown,Figure 3B shows a 3D top view, Figure 3C shows an internal 2D top view, Figures 3D to 3E shows an internal 3D top view;

[0027] Figures 4A to 4C shows the back side of a second example semiconductor package, where Figure 4A shows a 2D rear view, Figure 4B shows a 3D rear view, Figure 4C shows an internal 3D rear view;

[0028] Figure 5 A through Figure 5 H are side views of example source / drain slabs; and

[0029] Figure 6 shows an example process flow for manufacturing a semiconductor package in accordance with the present disclosure.

[0030] The figures are for illustrative purposes only and are not to be construed as limiting the scope defined by the claims. DETAILED DESCRIPTION

[0031] It will be readily understood that the components of the embodiments generally described herein and illustrated in the figures can be arranged and designed in a wide variety of different configurations. Accordingly, the more detailed description of the various embodiments presented below is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. While aspects of the embodiments are presented in the figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0032] The described embodiments are to be considered in all respects only illustrative and not restrictive. Thus, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes that come within the meaning and range of equivalency of the claims are embraced within their scope.

[0033] The mention of features, advantages or similar language throughout the specification does not mean that all features and advantages that can be realized by the present disclosure should be in any single example of the present disclosure or should be in any single example of the present disclosure. Rather, the language referring to the features and advantages should be understood to mean that a particular feature, advantage or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the discussion of the features and advantages throughout the specification and similar language can, but does not necessarily, refer to the same example.

[0034] In addition, the features, advantages, and characteristics of the present disclosure described herein can be combined in any suitable manner in one or more embodiments. Those skilled in the relevant art will recognize that, in accordance with the description herein, the present disclosure can be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Throughout the specification, references to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one embodiment" and similar language may, but do not necessarily, refer to the same embodiment.

[0035] The present disclosure presents backside-cooled packaging, top-side-cooled packaging, and dual-cooled source-down packaging, such as LFPAK packaging or PQFN packaging. The packaging has a common metal block design, which serves as the source or drain depending on the packaging configuration.

[0036] In some configurations, the package may include dual source pads that are exposed on the top and back sides of the package. When heat is generated at the source, the source can be exposed and attached to the metal block for better heat dissipation.

[0037] In other configurations, the package may include dual drain pads that are exposed on the top and back sides of the package. When heat is generated at the drain, the drain can be exposed and attached to the metal block for better heat dissipation.

[0038] Depending on the configuration, the metal block that serves as the source or drain can be designed to provide stress relief to absorb any forces or pressures applied to the metal block, which can be intentionally increased inside the semiconductor package to improve thermal performance. Advantageously, in one embodiment, the metal block can be exposed without using film-assisted molding or additional package grinding to meet any target thermal performance.

[0039] In Figures 1A to 1E and Figures 2A to 2C In the first example shown in, the exemplary semiconductor package 100 is presented in a source-down configuration (flip-chip die), where an additional source metal block is connected to the die pad to achieve low RDSon, low inductance, and low thermal resistance. Figures 1A to 1E The top of the package 100 is shown, Figures 2A to 2C The back side of the package 100 is shown. In this example, the package 100 is a dual-cooled source-down LFPAK package, but the present disclosure is not limited to such a package and can be similarly applied to, for example, PQFN packages or any other suitable packages.

[0040] InFigure 1A and Figure 1B , the exterior of package 100 is shown in a top view. Example package 100 includes three source pins 102, four drain pins 104, and a gate pin 106. The number of pins and their locations may vary depending on the configuration requirements. Encapsulation 108 protects the interior of package 100.

[0041] The source metal block 110 exposed on the outside of the package 100 covers most of the top portion of the package 100 to allow heat dissipation. The source metal block 110 is internally electrically connected to the source pin 102.

[0042] exist Figure 1C and Figure 1D , the interior of the package 100 is shown in a top view, i.e., without the encapsulation 108. The source metal block 110 is made of a first conductive metal. The source metal block 110 may be bent at an angle at one or more ends 112 of the source metal block 110 so that the one or more ends 112 may be attached to a recessed surface 114 of a second conductive metal (see Figure 1E ), such as a die pad for the source. Thus, one or more end portions 112 can function as legs. The first conductive material and the second conductive material can have the same composition. The one or more end portions 112 of the source metal block 110 can be attached to the recessed surface 114 by welding, sintering, welding, or any similar attachment process.

[0043] exist Figure 1E , the interior of the package 100 is shown with the source metal block 110 separated. In this view, the recessed surface 114 is visible. Figure 1E In the example shown, the recessed surface 114 is recessed within the die pad of the source.

[0044] exist Figure 2A and Figure 2B , the exterior of the package 100 is shown in a rear view. Three source pins 102, four drain pins 104, a gate pin 106, and an encapsulation 108 are shown. Figure 2A In the example of FIG, the source is exposed at the back side of the package and includes a source pin 102 . The gate is exposed at the back side of the package and includes a gate pin 106 .

[0045] exist Figure 2C , the interior of the package 100 is shown in a rear view, i.e., without the encapsulation 108. A portion of the source metal block 110 is visible, including the bent end 112.

[0046] exist Figures 3A to 3E as well as Figures 4A to 4CIn the second embodiment shown, example semiconductor package 200 is presented in a drain-down configuration (flip chip), where an additional drain metal block is connected to the die pad to achieve low RDSon, low inductance, and low thermal resistance. Figures 3A to 3E The top of package 200 is shown, Figures 4A to 4C and the back of package 200 is shown. In this example, package 200 is a dual-drain cold LFPAK package, but the present disclosure is not limited to such a package and can be similarly applied to, for example, a PQFN package or any other suitable package.

[0047] In Figure 3A and Figure 3B the exterior of package 200 is shown in a top view. Example package 200 includes three source pins 202, two drain pins 204, and a gate pin 206. Depending on the configuration requirements, the number and location of the pins can vary. Encapsulation 208 protects the interior of package 200.

[0048] The drain metal block 210 exposed on the exterior of package 200 covers most of the top portion of package 200 to allow heat dissipation. The drain metal block 210 is internally electrically connected to the drain pin 204.

[0049] In Figure 3C and Figure 3D the interior of package 200 is shown in a top view, i.e., without encapsulation 208. The drain metal block 210 is made of a first conductive metal. The drain metal block 210 can be bent at an angle at one or more ends 212 of the drain metal block 210 such that one or more ends 212 can be attached to the recessed surface 214 of a second conductive metal, such as the die pad for the drain. Thus, one or more ends 212 can act like legs. The first conductive material and the second conductive material can have the same composition. One or more ends 212 of the drain metal block 210 can be attached to the recessed surface 214 by soldering, sintering, welding, or any similar attachment process.

[0050] In Figure 3E the interior of package 200 is shown in the case of a separate drain metal block 210. In this view, the recessed surface 214 is visible. In Figure 3E the example, the recessed surface 214 is recessed within the die pad of the drain.

[0051] In Figure 4A and Figure 4B the exterior of package 200 is shown in a rear view. Three source pins 202, two drain pins 204, a gate pin 206, and encapsulation 208 are shown. In Figure 4A the example, the drain is exposed at the back portion of the package and includes source pins 202.

[0052] In Figure 4C it, the interior of the package 200 is shown in the rear view, i.e., without the encapsulation 208. A part of the source metal block 210 is visible, including the bent end 212.

[0053] In addition to the metal block terminals 110, 210, the terminals 102, 104, 106, 202, 204, 206 extend outside the package body and can be formed as gull wings or micro leads, leadless, or a combination of the two geometries.

[0054] The source metal block 110 can be attached to the source terminal 102 using a conductive material / metal such as copper, which is bare copper or copper plated with, for example, Ag, Sn, Ti, Ni, etc. Similarly, the drain metal block 210 can be attached to the drain terminal 204 using such a conductive material / metal. As illustrated in the figure, the drain / source metal blocks 110, 210 are preferably attached via the recessed surfaces 114, 214.

[0055] The first surfaces of the source / drain metal blocks 110, 210 can be exposed on the top surface of the package by direct or indirect contact with the molding cavity, while the second surfaces of the source / drain metal blocks 110, 210 face the semiconductor silicon die. Preferably, the second surfaces of the source / drain metal blocks 110, 210 are as close as possible to the semiconductor die, for example, 100 um or less, so that heat transfer from the source / drain metal blocks 110, 210 can be maximized.

[0056] If the first outer surfaces of the source / drain metal blocks 110, 210 do not contact the molding cavity, they can be exposed using a package grinding process or a similar polishing technique to expose the top surface.

[0057] The second conductive metal, which serves as the second source in the first embodiment or the second drain in the second embodiment, can have its first surface exposed on the back of the package, where its second surface serves as a die pad to connect the source terminal in the first embodiment of the flip-chip semiconductor die or the drain terminal in the second embodiment.

[0058] Thus, a standard or flip-chip process can be used to obtain semiconductor package 100, forming a source-down configuration, where the additional metal block 110 serves as the first source and is attached at the main source terminal or the second source terminal 102. Similarly, a standard or flip-chip process can be used to obtain semiconductor package 200, forming a drain-down configuration, where the additional metal block 210 serves as the first drain and is attached at the main drain terminal or the second drain terminal 204. The first surface of the first conductive metal forming the source / drain metal blocks 110, 210 can be exposed on the top surface of the package by direct or indirect contact with the molding cavity, while the second surface of the source / drain metal blocks 110, 210 faces the semiconductor silicon die before molding. If the first surface of the first conductive metal of the source / drain metal block does not contact the top molding cavity, a package grinding process can be used to expose it. Depending on the configuration, the first surface of the second conductive metal serving as the second source or the second drain can be exposed at the back of packages 100, 200, and the second surface of the second conductive metal can be used as a die pad for a flip-chip semiconductor die.

[0059] Depending on the package orientation, packages 100, 200 can form back-cooled or top-cooled packages.

[0060] In one embodiment, the bent ends 112, 212 of the source / drain metal blocks 110, 210 can be designed to serve as force / stress elimination or absorption members during the molding process. Up to this point, the bent ends 112, 212 can include a half-cut feature at the transition from the top surface of the source / drain metal blocks 110, 210 to the bent ends 112, 212. In another example, the bent ends 112, 212 can include a half-cut feature located on the side of the bent legs. In another example, the bent ends 112, 212 can include grooves or similar features. One or more of these stress elimination features can be combined in a single bent end 112, 212.

[0061] Figure 5 Various non-limiting examples A to H of source / drain metal blocks containing such stress elimination features are shown. Each of examples A to H shows a metal block, which can serve as the source metal block 110 or the drain metal block 210 depending on the configuration of the semiconductor package. Each source / drain metal block can include a first conductive metal surface 510 and one or more bent ends 512 serving as the legs of the source / drain metal blocks 110, 210.

[0062] In Figure 5 Example A, the bent end 512 includes a half-cut feature 520 at the transition from the top surface 510 to the bent end 512.

[0063] InFigure 5 In the example of B, the curved end portion 512 includes a sloped transition portion 522 between the top surface 510 and the curved end portion 512 .

[0064] exist Figure 5 In the example of C, the curved end portion 512 includes a half-cut feature 524 on the side of the curved leg.

[0065] exist Figure 5 In the example of D, the curved end portion 512 includes a groove or similar feature 526 on the side of the curved leg.

[0066] The curved end portion 512 may be curved substantially perpendicular to the top surface 510, such as Figure 5 A to Figure 5 As shown in the example of D. Alternatively, part or all of the curved end portion 512 may be further curved outward, such as Figure 5 E to Figure 5 H, except for the further outward bend 528, these examples are similar to Figure 5 A to Figure 5 D.

[0067] Figure 6 An example process flow 600 for manufacturing a semiconductor package 100, 200 including source / drain metal blocks 110, 210 according to the present disclosure is shown in FIG. In step 602, a die pad may be provided. In step 604, solder may be dispensed or printed on the die pad. Step 606 may include a die attach process, which may be a flip-chip die attach, depending on the configuration of the semiconductor package. In step 608, solder may be dispensed or printed on the die surface or the backside die surface, depending on the configuration of the semiconductor package. In step 610, a drain clip 104 or a source clip 202 may be attached, depending on the configuration of the semiconductor package.

[0068] In step 612, the source / drain metal blocks 110, 210 (depending on the configuration of the semiconductor package) can be attached to the die pad. To this end, the bent ends 112, 212 of the source / drain metal blocks 110, 210 can be inserted into the recessed surfaces 114, 214 and solder can be printed onto the die pad.

[0069] Step 614 involves reflow. Step 616 involves a forming process, optionally including polishing to expose the first top surface of the source / drain metal blocks 110, 210. Step 618 involves a plating / trim / forming / singulation process step.

[0070] By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and realize other variations of the disclosed embodiments when implementing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a / an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting their scope.

Claims

1. A semiconductor package, comprising: A first terminal exposed on a back surface of the semiconductor package; One or more additional terminals extending outside the semiconductor package; And A second terminal exposed on a top surface of the semiconductor package; Wherein the second terminal includes a metal block serving as the second terminal, Wherein the metal block is electrically connected to the first terminal via one or more bent ends of the metal block, and wherein the metal block includes one or more stress relief features.

2. The semiconductor device according to claim 1, wherein the one or more stress relief features include one or more of the following: A half-cut feature at a transition from a top surface of the metal block to the one or more bent ends; A half-cut feature located on a side of the one or more bent ends; and A groove or similar feature.

3. The semiconductor device according to claim 1 or claim 2, wherein the one or more bent ends are bent at an angle with respect to a top surface of the metal block, preferably at a perpendicular angle, optionally including a further outwardly bent portion.

4. The semiconductor package according to any one of the preceding claims, wherein the one or more bent ends form legs of the metal block.

5. The semiconductor package according to any one of the preceding claims, Wherein the first terminal is formed by a pad die, Wherein the pad die includes one or more recessed surfaces for receiving the one or more bent ends, And wherein the one or more bent ends are solder-printed onto the one or more recessed surfaces.

6. The semiconductor package according to any one of claims 1 to 5, wherein a first surface of the metal block is exposed on the top surface of the semiconductor package, while a second surface of the metal block faces a semiconductor silicon die before molding.

7. The semiconductor package according to claim 6, wherein the first surface of the metal block is exposed on the top surface of the semiconductor package by direct or indirect contact with a molding cavity.

8. The semiconductor package according to any one of claims 1 to 5, wherein the first surface of the metal block has been exposed using a package grinding process if it does not contact a top molding cavity.

9. The semiconductor package according to any one of the preceding claims, Wherein the first terminal includes a first surface exposed at a back of the semiconductor package, And wherein the first terminal includes a second surface serving as a die pad of a flip-chip semiconductor die.

10. The semiconductor package according to any one of the preceding claims, further comprising one or more additional terminals that extend outside the semiconductor package and are formed as gull wings or micro leads, or are leadless, or are a combination of the two geometries.

11. The semiconductor package according to claim 10, wherein the first terminal and the second terminal are source terminals, and wherein the one or more additional terminals include one or more drain terminals and one or more gate terminals.

12. The semiconductor package according to claim 10, wherein the first terminal and the second terminal are drain terminals, and wherein the one or more additional terminals include one or more source terminals and one or more gate terminals.

13. The semiconductor package according to any one of the preceding claims, which forms a metal-oxide-semiconductor field effect transistor MOSFET.

14. A method of manufacturing a semiconductor package according to any one of claims 1 to 13, comprising: providing a die pad; dispensing or printing solder on the die pad; die attachment, optionally including flip-chip die attachment; dispensing or printing solder on the die surface or the back surface of the die; attaching one or more additional terminals; attaching the metal block to the die pad by inserting one or more bent ends of the metal block into one or more recessed surfaces of the die pad and solder printing the one or more bent ends to the die pad, wherein the metal block includes one or more stress relief features; and molding while exposing a first surface of the metal block.

15. The method according to claim 14, further comprising providing one or more stress relief features on the metal block in one or more of the following forms: a half-cut feature at the transition from the top surface of the metal block to the one or more bent ends; a half-cut feature located on the side of the one or more bent ends; and grooves or similar features.

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