Multi-mode resonant circuit and corresponding method

Abstract

The invention relates to a multimode resonant circuit and a corresponding method. The circuit includes: first and second electronic switches cascaded in a current flow line between an input node and ground; a transformer having a primary winding coupled across the second electronic switch; and a capacitor coupled across the secondary winding, the circuit operating by turning on and off the first and second electronic switches in a series of phases including an energy storage phase (with current in the primary winding, without current in the secondary winding) and a subsequent simultaneous turn-on phase (with current in both the primary and secondary windings of the transformer). The circuit is operable in a first mode in which the simultaneous on-phase is maintained for a first off-time of the first switch, and in a second mode in which the simultaneous on-phase is maintained for a second off-time of the first switch, the second off-time being shorter than the first off-time.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of Italian Patent Application No. 102024000001530, filed on January 26, 2024, which is hereby incorporated herein by reference. Technical Field

[0003] This specification relates to resonant flyback circuits. Background Art

[0004] For example, aspects of this specification can be used in applications that use AC-DC converters.

[0005] Personal computers, mobile phones, various types of power supplies, and extended power range (EPR) chargers are examples of such possible applications.

[0006] The name "resonant flyback topology" applies to a switched converter topology that is gaining attention due to its flexibility in output voltage regulation, high efficiency, and low voltage stress on both primary and secondary side components.

[0007] This topology is denoted in the literature by various other names, such as "half-bridge flyback", "hybrid flyback", "asymmetric half-bridge" (the last name is sometimes also used for different topologies, which can cause some confusion).

[0008] In Figure 1 is illustrated the topology of such a circuit, generally designated by 10, for quick reference.

[0009] As illustrated (in a deliberately simplified manner for ease of understanding), circuit 10 includes a high-side switch QH and a low-side switch QL (e.g., such as MOSFET transistors), which have a current path therethrough (in the case of field-effect transistors such as MOSFETs, source-drain), cascaded in the current flowline between a power supply node / line VIN (from a signal source, which is not visible in the figure for simplicity) and a ground node / line PRI_GND.

[0010] As illustrated, a transformer Tx is provided, which is arranged with:

[0011] a primary winding, which is coupled between a node N located intermediate the electronic switches QH, QL and one terminal of a resonant capacitor C RES and the other terminal of the resonant capacitor is connected to PRI_GND; and

[0012] A secondary winding, which is coupled between a first terminal of the capacitor C and the cathode of the diode D, wherein the diode is coupled (at the anode) to the other terminal of the capacitor C.

[0013] The voltage across the capacitor C can be considered as the output voltage Vout of the circuit 10 (which is intended to be applied to a load, which is not visible in the figure for simplicity).

[0014] The electronic switches (MOSFET transistors QH and QL) can be selectively "turned on" (i.e., made conductive) and "turned off" (i.e., made non-conductive) via control signals, which are applied to the control electrodes (labeled HSGD and LSGD) of the electronic switches (in the case of field-effect transistors such as MOSFETs, the gates) in a manner known per se to a person skilled in the art via a controller circuit arrangement not visible in the figure other than Figure 15 and Figure 20 in the figure.

[0015] These figures will be discussed in the detailed description of the embodiments.

[0016] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B The diagrams of

[0017] the current Isec in the secondary winding of the transformer Tx;

[0018] the current Ipri in the primary winding of the transformer Tx; and

[0019] the voltage Vlsd at the drain of the low-side switch QL, i.e., the voltage at the node N, are examples of possible time behaviors plotted (from top to bottom) against a common abscissa time scale:

[0020] As Figure 1 illustrated in

[0021] During the "on" phase, the high-side switch QH is turned on (made conductive), and energy is stored in the magnetizing inductance of the transformer Tx and the associated resonant capacitor C in series with the primary winding of the transformer Tx RES in.

[0022] During the "off" phase, the high-side switch QH is turned off (made non-conductive) and the low-side switch QL is turned on (made conductive); the energy previously stored in the capacitor C RES and the magnetizing inductance of the transformer Tx is transferred to the secondary side (across the capacitor C) via the transformer Tx and the diode D.

[0023] Note that the structure of the primary side of the circuit 10 is symmetrical: by changing the polarity of the transformer winding, the switch QL (referred to here as the low side) can be used as the switch during the "on" phase and the switch QH (referred to here as the high side) can be used as the switch during the "off" phase.

[0024] The choice between these two configurations depends on design choices that are not specific to the embodiments. For simplicity, the first solution (switch QH for the "on" phase) will be referred to throughout this specification.

[0025] More specifically, as Figure 1 illustrated, the operation of the converter circuit 10 can be considered to involve five (sub)phases labeled I, II, III, IV, and V as represented respectively as follows:

[0026] During Figure 2A and Figure 2B (phase I);

[0027] During Figure 3A and Figure 3B (phase II);

[0028] During Figure 4A and Figure 4B (phase III);

[0029] During Figure 5A and Figure 5B (phase IV); and

[0030] During Figure 6A and Figure 6B (phase V).

[0031] During the energy storage phase as represented in Figure 2A and Figure 2B (labeled I in Figure 2B ), the high side switch QH is turned on (conducted) while the low side switch QL is not conducted. The current in the primary side of the transformer Tx increases almost linearly - as long as the "on" time can be assumed to be much shorter than the resonance period generated between the resonant capacitor C RES and the inductance of the primary side of the transformer Tx. Practically no current flows on the secondary side of the transformer Tx.

[0032] Figure 3A and Figure 3B are examples of the (first) dead time (labeled II in Figure 3B ), during which both the high side switch QH and the low side switch QL are turned off (not conducted), and the current flowing in the primary side of the transformer Tx discharges the parasitic capacitance C associated with the switch node NPAR Discharge, forcing it to drop to 0V.

[0033] Figure 4A and Figure 4B are examples of the secondary - side conduction phase (marked as III in Figure 4B ), during which the low - side switch QL is turned on (conducted) while the high - side switch QH is not conducted. Current flows in both the primary and secondary sides of the transformer Tx, creating a "bump" due to the resonance between the leakage inductance of the transformer Tx and the clamping capacitor C.

[0034] This phase terminates when the current on the secondary side of the transformer Tx reaches zero, or it can be truncated earlier if QL is turned off (made non - conductive) prematurely.

[0035] The duration T of this phase (marked as III) cond is almost constant because it is determined by the resonance period of the leakage inductance Lk of the transformer Tx and the capacitance of the resonance capacitor C RES and is approximately equal to:

[0036] T cond ≈π / √(Lk * CRES )

[0037] Figure 5A and Figure 5B are examples of an additional "off" time (marked as IV in Figure 5B ), during which the low - side switch QL remains on (conducted) while current no longer flows on the secondary side of the transformer Tx.

[0038] During this phase, the current in the primary side of the transformer Tx is substantially equal to the magnetizing current. The purpose of this phase is to load energy into the magnetizing inductance of the transformer Tx to achieve soft switching in a later phase.

[0039] From the perspective of the controller on the primary side of the transformer Tx, the additional "off" time phase IV is merely a continuation of the previous phase because the switches are controlled in the same way (high - side switch QH off; low - side switch QL on).

[0040] Figure 6A and Figure 6B are examples of the second dead - time phase (marked as V in Figure 6B ), during which the low - side switch QL is turned off (non - conductive), and the current flowing in the magnetizing inductance of the transformer Tx charges the parasitic capacitance associated with the switch node N, raising it up to the input voltage VIN.

[0041] Then, the converter circuit 10 can then restart the cycle from phase I with the high-side switch QH turned on (conducting).

[0042] The "simultaneously conducting" phases III and IV can be considered to represent the "off" phase mentioned at the beginning, i.e., the phase during which the primary-side switch QH is off.

[0043] The dead-time intervals II and V have a very short duration and are practically negligible compared to the other phases and will not be specifically considered in the remainder of this specification.

[0044] For various reasons, it can prove difficult to determine the duration of the "off" phase.

[0045] The optimum duration of the "off" phase is the duration that causes the magnetizing inductance of the transformer Tx to be loaded with just enough energy to force a soft switch when the low-side switch QL turns off.

[0046] Achieving this goal is difficult for at least two reasons.

[0047] First, during the entire secondary-side conducting phase, the current "seen" from the primary side of the transformer Tx is the sum of the current reflected to the primary side and flowing to the secondary side of the transformer Tx and the current flowing in the magnetizing inductance of the transformer Tx. Therefore, it is almost infeasible to determine the current flowing in the magnetizing inductance. Detecting when the secondary-side conducting phase terminates from the primary side of the transformer Tx is equally complex.

[0048] Additionally, the amount of energy absorbed in the magnetizing inductance of the transformer Tx to achieve soft switching depends on the parasitic capacitances of both the switch QH and the switch QL: these are non-linear and are largely affected by uncertainties.

[0049] Additionally, during the "off" time, the voltage across the magnetizing inductance of the transformer Tx is equal to the output voltage multiplied by the turns ratio n of the transformer Tx. The slope at which the magnetizing current iM decreases as a function of time during this phase can be expressed as:

[0050]

[0051] where Lm represents the magnetizing inductance of the transformer Tx.

[0052] The time required for the magnetizing current iM to reach zero from its initial value is inversely proportional to the output voltage.

[0053] The resonant flyback topology discussed herein is suitable for power supplies that can have a widely varying output voltage, such as USB Power Delivery (USB-PD) power supplies. For example, it is desirable that various power supplies can generate an output voltage that varies from 5V to 48V in accordance with a command received from a load connected to the power supply. In this case, for the same peak current, the "off" time can vary by a factor of 10:1.

[0054] For example, Figure 7A and Figure 7B show possible waveforms for high and low output voltages with similar output currents (likewise for currents Isec and Ipri and voltage Vlsd).

[0055] In the first case (low voltage - Figure 7A ), the magnetizing current drops rapidly, and shortly after the conduction termination on the secondary side of transformer Tx, a new cycle can restart.

[0056] In the second case (high voltage - Figure 7B ), the current in the magnetizing inductor drops (very) slowly, and in order to achieve soft switching, after the conduction termination on the secondary side of transformer Tx, the low-side switch QL remains on (conducting) for a long time. This results in a significant drop in conversion efficiency because all the current is delivered to the secondary side of the transformer at a very high peak current within a short period of time, thereby causing high RMS currents on both the primary and secondary sides of transformer Tx.

[0057] Document CN113765407B discloses an adaptive soft-switching control system for a primary-side feedback active flyback converter. The system includes a main topology circuit and a closed-loop control loop; additionally, an auxiliary winding is arranged on the secondary side of the transformer, voltage sampling is implemented across the two ends of the auxiliary winding through two voltage-dividing resistors, and the feedback voltage of the winding voltage is input into the closed-loop control loop; a current sampling resistor is added between the main switching tube and the ground terminal, and the voltage of the sampling resistor is input into the closed-loop control loop; the closed-loop control loop includes a primary-side current detection module, an auxiliary winding detection module, a dead-time calculation module, and a PWM drive module; the dead-time calculation module calculates the dead time of the control signals of the main switching tube and the auxiliary switching tube according to the time signal and the current signal received at the input end; and the system is connected to the controlled switching power supply to form a closed loop. Zero-voltage switching ZVS is achieved, reducing the switching loss, and thus improving the efficiency of the entire system.

[0058] Document CN115833601A discloses a soft-switching control circuit applied to an isolated power supply system. The secondary soft-switching control circuit includes a secondary controller, a synchronous rectifier tube, and an output capacitor; the secondary-side controller includes a power system energy transfer module, a matching module, and a synchronous rectification and zero-voltage switching module connected in sequence; according to the soft-switching control circuit provided by the present invention, the power system energy can be detected through the power system energy transfer module, and then the power system energy can be used to predict in advance the "on" time of the primary controller in the current period in an adaptive energy matching mode.

[0059] Other documents of interest include US2004 / 032754 A1, EP 2081288 A1, US 6504267B1, US2023 / 080559 A1, and CN 116073639 A. Summary of the Invention

[0060] The aim of one or more embodiments is to help solve the various problems discussed above.

[0061] According to one or more embodiments, such an aim can be achieved by a circuit having the features set forth in the appended claims.

[0062] One or more embodiments relate to corresponding devices (any device using the converter circuit discussed can be an example of such a device).

[0063] One or more embodiments involve corresponding methods.

[0064] The claims are the main part of the technical teachings of the embodiments provided herein.

[0065] In the solution described herein, when the "off" time exceeds a threshold, the non-complementary control mode adopted via switch operation is used to improve efficiency, especially when operating at a low output voltage.

[0066] In the solution described herein, for example, when the "off" time exceeds twice the duration of the resonance "bump", non-complementary control is used, and by changing the switch control sequence in response to the duration of the "off" time, an improvement in the conversion efficiency of a resonant flyback converter that can operate at a variable output voltage can be achieved. Brief Description of the Drawings

[0067] Now, one or more embodiments will be described only by way of example with reference to the drawings, wherein:

[0068] Figure 1 ; Figure 2A 、 Figure 2B ; Figure 3A 、 Figure 3B ;Figure 4A , Figure 4B ; Figure 5A , Figure 5B ; Figure 6A , Figure 6B ; and 7A, Figure 7B illustrates the circuit and its operation;

[0069] Figure 8 is a circuit diagram example of a possible implementation of the solution described in this specification;

[0070] Figure 9A , Figure 9B and Figure 9C as well as Figure 10 is a timing diagram explaining the basic principle of the solution described in this specification;

[0071] Figure 11A , Figure 11B ; Figure 12A , Figure 12B ; Figure 13A , Figure 13B ; and Figure 14A , Figure 14B illustrates the subsequent stages in the control sequence according to the solution described in this specification;

[0072] Figure 15 is a circuit diagram example of a possible digital implementation of the solution described in this specification;

[0073] Figure 16 and Figure 17 is a timing diagram explaining the possible operation of the solution described in this specification;

[0074] Figure 18 and Figure 19 are flowchart examples of the possible operation of the solution described in this specification; and

[0075] Figure 20 is a circuit diagram of a possible analog implementation of the solution described in this specification.

[0076] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and need not be drawn to scale.

[0077] The edges of the features drawn in the figures do not necessarily indicate the termination of the feature limits. Detailed Description

[0078] In the following description, one or more specific details are set forth in order to provide an in-depth understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details, or by other means, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail so that certain aspects of the embodiments will not be obscured.

[0079] References to "an embodiment" or "one embodiment" in the context of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to the same embodiment. Furthermore, the particular configurations, structures, or features may be combined in any desirable manner in one or more embodiments.

[0080] The headings / reference numbers used herein are provided merely for convenience and thus do not define the scope of protection or the scope of the embodiments.

[0081] In the figures attached herein, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals, and the corresponding descriptions will not be repeated for the sake of brevity.

[0082] In this regard, it is noted that Figure 11A and Figure 11B ; Figure 12A and Figure 12B ; and Figure 14A and Figure 14B basically correspond respectively to Figure 2A and Figure 2B ; Figure 3A and Figure 3B ; and Figure 4A and Figure 4B .

[0083] This repetition of the figures is essentially intended to facilitate understanding of the operation of the circuit 10 represented in Figure 13A and Figure 13B during the phase labeled IIA.

[0084] Again, for the sake of simplicity and ease of illustration, the same names may be applied throughout this specification to designate:

[0085] a certain node or line and the signal that appears at that node or line (the signal / node VIN in the figure is an example thereof), and / or a certain component (such as a capacitor, resistor, or inductor of a coil) and its electrical parameters.

[0086] For ease of understanding, from Figure 8The circuit 10 is again illustrated in a deliberately simplified manner and includes a high-side switch QH and a low-side switch QL (e.g., such as MOSFET transistors), the high-side switch and the low-side switch having current paths therethrough (in the case of field-effect transistors such as MOSFETs, source-drain) that are cascaded in the current flow line between the power supply node / line VIN (from a signal source that is not visible in the figure for simplicity) and the ground node / line PRI_GND.

[0087] As illustrated, a transformer Tx is provided and is arranged with:

[0088] A primary winding that is coupled between a node N located intermediate the electronic switches QH, QL and a terminal of a resonant capacitor C RES the other terminal of which is connected to ground PRI_GND; and

[0089] A secondary winding that is coupled between a first terminal of the capacitor C and the cathode of a diode D, where the diode (at its anode) is coupled to the other terminal of the capacitor C.

[0090] The voltage across the capacitor C can be considered the output voltage Vout of the circuit 10 (which is intended to be applied to a load that is not visible in the figure for simplicity).

[0091] The electronic switches (MOSFET transistors QH and QL) can be selectively "turned on" (i.e., made conductive) and "turned off" (i.e., made non-conductive) via control signals that are applied to the control electrodes (labeled HSGD and LSGD) of the electronic switches (in the case of field-effect transistors such as MOSFETs, the gates) in a manner known per se to a person skilled in the art via the controller circuitry illustrated in Figure 15 and Figure 20 which will be discussed in detail subsequently.

[0092] Again, note that the structure on the primary side of the circuit 10 is symmetric: by changing the polarity of the transformer windings, the switch QL (here called the low side) can be used as the switch during the "on" phase and the switch QH (here called the high side) can be used as the switch during the "off" phase.

[0093] In Figure 8 as in Figure 1 the circuit 10 thus includes:

[0094] A first electronic switch (in the exemplary case considered herein, the high-side switch QH) and a second electronic switch (in the exemplary case considered herein, the low-side switch QL), which are cascaded (with node N in the middle) in the current flow path between the input node VIN and (primary-side) ground PRI_GND, have a current flow path through the first and second electronic switches (exemplary case of field-effect transistors such as MOSFET transistors considered herein, source-drain);

[0095] A transformer Tx, which has a primary winding coupled across the second electronic switch (here, QL - via a resonant capacitor C RES ); and

[0096] A capacitor C, which is coupled across the secondary winding of the transformer Tx, where the output voltage from the circuit 10 can be obtained across the capacitor C.

[0097] When an element is referred to herein as being "connected to" or "coupled to" another element, it should be understood that another element may be interposed therebetween. For example, this is the case for the resonant capacitor C RES where the primary winding of the transformer Tx is coupled across the second electronic switch QL via this resonant capacitor, with the primary winding coupled between node N (which is in the middle of the electronic switches QH, QL) and the terminal of the resonant capacitor C RES and the other terminal of the resonant capacitor is connected to ground PRI_GND.

[0098] Conversely, when it is possible to refer to an element as being "directly connected to" or "directly coupled to" another element, it should be understood that no other element is interposed therebetween.

[0099] Likewise, Figure 8 the exemplary circuit 10 includes a series connection of a capacitor C and a diode D coupled across the secondary winding of the transformer Tx, where the capacitor C is coupled between node N and the diode D (anode).

[0100] Figure 8 The exemplary circuit illustrated in includes: drive circuit means (such as the elements 106 discussed below; HFF, LFF, 212H, 212L), which are configured to turn on and off the first electronic switch QH and the second electronic switch QL in a series of stages, which include:

[0101] An energy storage stage (labeled I), where the first electronic switch QH is on and the second electronic switch QL is off, enabling (allowing) current flow in the primary winding of the transformer Tx and canceling (substantially preventing) current flow in the secondary winding of the transformer Tx;

[0102] The stage (subsequent in the sequence) marked as III, in which the first electronic switch QH is non-conductive and the second electronic switch QL is conductive, is a kind of "simultaneous conduction" obtained by promoting current flow in both the primary winding and the secondary winding of the transformer Tx.

[0103] As already discussed, referring to the sequence of operating stages of the circuit 10 as including an energy storage stage (marked as I) and a subsequent simultaneous conduction stage (marked as III) does not mean that the sequence consists only of those stages or that the simultaneous conduction stage immediately follows the energy storage stage.

[0104] In fact, as already discussed, the exemplary sequence of operating stages of the circuit 10 also includes other stages (such as those marked as II, IV, and V), where stage (dead time) II may be extended by the secondary-side conduction time, as exemplified by IIA between stage I and stage II below.

[0105] Compared with Figure 1 the circuit 10 of Figure 8 the exemplary circuit 10 includes a series connection of the following elements arranged in the current flow path between the node N and the ground or the node PRI_GND:

[0106] Another electronic switch Q SSDET (also, for example, a MOSFET transistor), which has a current path through it (in the case of a field-effect transistor such as a MOSFET, source-drain); and

[0107] Another capacitor C SSDET , which is arranged between the node N and the switch Q SSDET , at the node Q there appears a voltage V SSDET , where the switch Q SSDET is arranged between the node N and the ground or the node PRI_GND.

[0108] Figure 9A , Figure 9B and Figure 9C The diagrams of

[0109] the voltage V SW at the switch node N;

[0110] the voltage V SSDET ;

[0111] the drive voltage V SSG , which is applied to the control terminal of the switch Q SSDET ;

[0112] the drive voltage V LSG, which is applied to the control terminal LSGD of the low-side switch QL (in the case of a field-effect transistor such as a MOSFET transistor, the gate); and

[0113] Drive voltage V HSG , which is applied to the control terminal HSGD of the high-side switch QH (in the case of a field-effect transistor such as a MOSFET transistor, the gate).

[0114] The solution proposed herein employs an adaptive control of the "turn-off" time Toff, where such "turn-off" time is determined via an adaptive algorithm that adapts the duration based on a soft-switch detector, as Figure 8 represented on the left-hand side.

[0115] Advantageously, a small value (around 10 pF) is selected for the capacitor C SSDET associated with the switch Q SSDET such that the voltage V SSDET at the node Q between the capacitor C SSDET and the switch Q SSDET can be measured to determine whether the system operates in soft-switching.

[0116] The switch Q SSDET remains on (conducting) most of the time and turns off (becomes non-conducting) during the dead time between the "turn-off" time of the low-side switch QL and the "turn-on" time of the high-side switch QH. After the high-side switch QH turns on, the voltage V SSDET is measured, and the switch Q SSDET turns on again.

[0117] When the switch Q SSDET turns on, the voltage V SSDET at the node Q is forced to be 0, and when the switch Q SSDET turns off, it tracks the voltage at the switch node N, so it can be used to measure the voltage transition during the dead time.

[0118] Figure 9A , Figure 9B and Figure 9C show the possible waveforms during the dead time (referred to as the "QL-QH" dead time for short) between the turn-off time of the low-side switch QL and the turn-on time of the high-side switch QH for different conditions.

[0119] Figure 9A refers to the situation where the energy in the magnetizing inductor is too low at the end of the "turn-off" time to achieve soft switching. When the gate of the low-side switch QL (the voltage V LSG ) turns off, the voltage V SWStarts to rise. When the gate of the high-side switch QH (voltage V in the figure) is turned on, the voltage V at the switching node HSG is still lower than the converter input voltage VIN, so it suddenly rises to the input voltage. SW

[0120] Figure 9B Refers to the situation of the following optimal soft switching: when the low-side switch QL is turned off, the energy in the magnetizing inductor is just enough to make the voltage V at the switching node N SW reach the input voltage VIN just before the high-side switch QH is turned on.

[0121] Figure 9C Refers to the following situation: Excessive energy is stored in the magnetizing inductor, so that the voltage V at the switching node N SW bypasses the input voltage during the dead time that causes the body diode of the high-side switch QH to turn on (become conductive).

[0122] From the moment when the switch Q SSDET is turned off, the voltage V SSDET tracks the voltage V at the switching node N with a constant difference SW . If the voltage V SSDET is measured at a time after the high-side switch QH is turned on, then the difference between the voltage V SSDET when the switch Q is turned off and the input voltage can be measured. SSDET

[0123] The timing between the switch Q SSDET being turned off and the high-side switch QH being turned on is an arbitrary parameter that can be defined during the design phase of the system. Depending on this, the voltage V at the sampling moment corresponding to the desired soft switching SSDET can be determined by calculation or experimentally, and can be fixed as a system parameter: below, this "optimal" voltage will be called V OPT .

[0124] The "turn-off" time at each cycle m + 1 as a function of the "turn-off" time at the previous cycle can be adjusted based on the following relationship.

[0125] T off (m + 1) = T off (m) + g(V SSDET - V OPT )

[0126] where g represents a fixed gain parameter selected based on a sensible balance of adaptive speed and noise sensitivity: a high value helps the system converge quickly to the optimal point, but causes time jitter due to sensitivity to noise.

[0127] In the steady state, the "off" time will be the time to provide a measured voltage V equal to the optimum point V OPT of SSDET .

[0128] A disadvantage of this method is that the "off" time involved in reaching the optimum point of soft switching is proportional to the peak current at the end of the "on" time.

[0129] At any time when the converter load current changes, the control loop reacts by increasing or decreasing the peak current, and the adaptive process regulation operation will take some time to reach the optimum conditions again: if the load changes frequently, the converter 10 can remain away from the optimum conditions for a long time, which has an adverse effect on efficiency.

[0130] This disadvantage can be overcome if the peak current or the duration of the "on" phase at the end of the "on" phase is known, as is the case with most converter control methods.

[0131] Looking at Figure 10 , and mainly looking at the time behavior of the current I in the primary winding of the transformer Tx pri , it can be observed that the slope of the magnetizing current i m during the on-time satisfies the following relationship:

[0132]

[0133] while the slope of the magnetizing current i m during the off-time satisfies the following relationship:

[0134]

[0135] Looking at Figure 10 , it can be observed that the time to reach zero current during the "off" phase is approximately given by the following ratio:

[0136] I peak (Lm / nVout)

[0137] In the above relationship:

[0138] I peak is the peak value of the current I pri in the primary winding of the transformer Tx

[0139] L m is the magnetizing inductance of the transformer Tx

[0140] L k is the leakage inductance of the transformer Tx

[0141] n is the turns ratio of the transformer Tx

[0142] V CRES is the voltage across capacitor C RES and

[0143] VIN and Vout are the input and output voltages of circuit 10

[0144] These relationships can be used to calculate the "off" time as

[0145] T off = k ipk I pk + T offset

[0146] or

[0147] T off = k t T on + T offset

[0148] where k ipk = (L m / nV out ) and k t = (V in - nV out ) / (nV out ), and the time T offset is adaptively calculated as previously discussed as

[0149] T offset (m + 1) = T offset (m) + g(V SSDET - V OPT )

[0150] The advantage of this method is that the adaptive process only compensates for the difference between the "off" time estimated based on the peak current or "on" time and the time required to achieve optimal soft switching

[0151] The solution described herein uses a modified control sequence based on the duration of the "off" time calculated by the process described above (or a similar process), and this modified control sequence can be considered a non - complementary mode

[0152] Such non - complementary control sequences are summarized in Figure 11A 、 Figure 11B ; Figure 12A 、 Figure 12B ; Figure 13A 、 Figure 13B ; and Figure 14A 、 Figure 14B

[0153] As noted Figure 11A and​Figure 11B ; Figure 12A and Figure 12B ; and Figure 14A and Figure 14B corresponds essentially respectively to Figure 2A and Figure 2B ; Figure 3A and Figure 3B ; and Figure 4A and Figure 4B .

[0154] This repetition of the figures is essentially intended to assist in understanding the operation of circuit 10 during the phases represented in Figure 13A and Figure 13B .

[0155] As also noted, the dead times, referred to as II and V in Figure 3B and Figure 6B , have a very short duration and are in fact negligible compared to the other phases and will not be considered further in the remainder of this specification.

[0156] The non-complementary mode discussed herein depends on a control sequence including an energy storage phase I, with current flow and waveforms as depicted in Figure 11A and Figure 11B . This phase operates with the high-side switch QH on (conducting) and the low-side switch QL off (non-conducting), exactly as in the conventional control method illustrated in Figure 2A and Figure 2B .

[0157] (Short) dead time II follows the current flow and waveforms depicted in Figure 12A and Figure 12B , i.e., both the high-side switch QH and the low-side switch QL are off (non-conducting), exactly as in the conventional control method illustrated in Figure 3A and Figure 3B .

[0158] The "secondary side only conducting" phase IIA follows the illustration in Figure 13A and Figure 13B .

[0159] The addition of this phase IIA marks a difference from the conventional control sequence discussed in the introductory part of this specification.

[0160] During the phases illustrated in Figure 13A and Figure 13B , both switches QL and QH remain off for a time advantageously longer (much longer) than the dead time.

[0161] By keeping both switches QH and QL open, the secondary-side diode D becomes conducting and current starts to flow (only) on the secondary side. As in a conventional flyback topology, the current in the secondary side of transformer Tx decreases linearly.

[0162] Figure 14A and Figure 14B The figure illustrates a subsequent stage (labeled III by reference to Figure 4A and 4B ), in which, after a time determined by the controller, the low-side switch QL on the primary side of the transformer is turned on, and during this stage, current flows on both the primary and secondary sides of transformer Tx (a "simultaneous conduction"), as in the case of the conventional solution depicted in Figure 4A and Figure 4B .

[0163] This stage ends when the current in the secondary side reaches zero.

[0164] At the end of stage III, an additional "off" time can be added, during which the low-side switch QL is on, but no current flows on the secondary side of the transformer. As described for a conventional control sequence, the dead time is beneficial for avoiding cross-conduction after the low-side switch QL turns off and helps the switch node N reach an input voltage sufficient to achieve soft switching when the (subsequent) high-side switch QH turns on (in the new energy storage stage I).

[0165] The duration of the only-secondary-side stage (labeled IIA in Figure 13B ) and the subsequent "simultaneous conduction" stage (labeled III in Figure 14B ) can be determined based on the "off" time calculated by the method described above (or by a different method).

[0166] The duration of the stage labeled III in k can be programmed as a fixed parameter based on the value of the leakage inductance L RES and the value of the resonant capacitor C Figure 14B . cond This can be considered approximately equal to:

[0167] This can be considered approximately equal to:

[0168] T cond ≈π / √(L k C RES )

[0169] The duration T Figure 13B of the only-secondary-side stage (labeled IIA in SSONLY ) can be calculated as, for example, the total "off" time T offThe difference between the duration T of the "simultaneous conduction" phase cond and

[0170] T SSONLY is: off T cond One can choose between a normal operating mode ( Figure 2A , Figures 2B to 6A , Figure 6B ) and a non-complementary mode ( Figure 11A , Figures 11B to 14A , Figure 14B ), noting that the latter control sequence is more effective when the duration of the "off" time is longer (much longer) than the duration T cond .

[0171] Such a choice can be made based on the duration of the "off" time T off such that when T off > k1 * T cond the system switches to the non-complementary mode and when T off < k2 * T cond the system switches back to the normal mode.

[0172] The difference between the value k1 and the value k2 provides some hysteresis to avoid the system continuously switching between these two modes. For example, a sensible choice could be k1 = 3 and k2 = 2.

[0173] Figure 15 FIG. shows a first possible implementation of a complete system including the circuit 10 as described previously (for example, see Figure 8 ).

[0174] As Figure 15 illustrated, the system includes a resonant flyback converter 10, a voltage feedback circuit 12, and (here, numerically) a controller 100 that is configured to cooperate with a soft-switching detector circuit that includes a capacitor C coupled to the switch node N via a node Q therebetween SSDET and a switch Q SSDET .

[0175] The soft-switching detector circuit under discussion has been described in conjunction with Figure 8 and, for simplicity and ease of illustration, is shown in FIG. 5 as a separate entity from the converter 10.

[0176] A feedback circuit 12 of any type known to those skilled in the art is configured to compare the output voltage Vout of the converter 10 (advantageously its replica obtained via a voltage divider / rectifier arrangement 120) with a reference voltage and generate a feedback signal FB (advantageously via an optocoupler 122) representative of the desired peak current for the operation of the converter 10.

[0177] The microcontroller 100 reads the feedback value FB (via the analog-to-digital converter ADC 102) and sets the peak current I pk accordingly, and the value of the peak current I pk is applied to a processing unit (MCU) 104 configured to generate a value of "off" time T off .

[0178] The value of the "off" time T off is supplied to a PWM generator 106, which drives the high-side switch QH and the low-side switch QL of the converter 10 via the control terminals (i.e., HSGD and LSGD) of the high-side switch QH and the low-side switch QL of the converter 10 (in the case of a field-effect transistor such as a MOSFET transistor, the gate).

[0179] When in the normal mode, the PWM generator 106 generates waveforms HSG (high side) and LSG (low side) shown in two upper curves in Figure 16 respectively applied to the control terminals HSGD and LSGD.

[0180] Figure 16 The lower curve in

[0181] where all curves share a common abscissa time scale represents the possible corresponding time behavior of the signal SSG at the control terminal (in the case of a field-effect transistor such as a MOSFET transistor, the gate) of the switch SSGD sampled (via the analog-to-digital converter ADC 108) at the sampling moment SS ADC sample under the control of the signal ADC sample from the PWM generator 106.

[0181] The switching period can be considered to start with a "QL-QH" dead time. During this period, after a time programmed by the MCU, the switch Q SSDET turns off (becomes non-conductive). At the end of the dead time, the high-side switch QH turns on (becomes conductive) and remains on until the comparator 110 is triggered in response to the signal CS comp being asserted in response to finding that the (voltage) signal CS at the switch node N exceeds the peak I provided by the microcontroller unit 104 pk .

[0182] During the "on" time of the high-side switch QH, the voltage SSDET at node D is sampled (see the signal SS ADC sample in Figure 16 ), to determine the start of the soft-switching condition.

[0183] In response to the high-side switch QH turning off, the PWM generator 106 waits within a second dead time (again, this can be a fixed value programmed by the MCU 104), and remains off (non-conducting) for a time equal to T off -T dLH , where T dLH is the "QL - QH" dead time.

[0184] To implement the non-complementary mode, the MCU 104 is programmed to provide a long dead time between the time when the high-side switch QH turns off and the time when the low-side switch QL turns on, such a long dead time being equal to Tpre, as represented in Figure 17 .

[0185] Here, again, as in Figure 16 , all curves share a common abscissa time scale, and the two upper curves show the possible time behavior of the waveforms HSG (high side) and LSG (low side) applied by the PWM generator 106 to the control terminals HSGD and LSGD (in the case of a field-effect transistor such as a MOSFET transistor, the gate) of the high-side switch QH and the low-side switch QL, respectively.

[0186] Similarly, Figure 17 the lower curve in shows the corresponding possible time behavior of the signal SSG at the control terminal (in the case of a field-effect transistor such as a MOSFET transistor, the gate) of the switch SSGD sampled at the sampling moment SS ADC (via the ADC 108) under the control of the signal ADC sample from the PWM generator 106.

[0187] In summary, in the solution described herein:

[0188] In the first ("normal") operating mode, the dead time II has a first (shorter) dead-time duration, where stage III remains within the (first) off time T off , and

[0189] In the second ("non-complementary") operating mode, the dead time (labeled IIA) has a second dead-time duration (T in Figure 17 ) pre), the second dead time duration is extended beyond the first dead time duration by the secondary side conduction time during which current starts to flow in the secondary winding of transformer Tx, where the (second) turn-off time of the first switch (transistor QH) (i.e., T off -T pre ) is shortened by the second dead time duration T off with respect to the first turn-off time T of the first switch QH pre .

[0190] Each time the voltage SSDET is sampled, the process shown in the flowchart of Figure 18 is run to update the "turn-off" time for optimized soft switching.

[0191] Figure 18 The boxes in

[0192] 1000: Start (SS ADC sample available)

[0193] 1002: Read the SS ADC value as V SSDET

[0194] 1004: Adjust T offset to

[0195] T offset (m + 1)=T offset (m)+g(V SSDET -V OPT )

[0196] 1006: Calculate T off as

[0197] T off =k ipk I pk +T offset

[0198] 1008: Stop

[0199] After running the process in Figure 18 , start the process shown in the flowchart of Figure 19 to select between normal mode and non-complementary mode.

[0200] Figure 19 The boxes in

[0201] 2000: Start

[0202] 2002: Check if T off is higher than k*T res2: This is a fixed reference (which may be adjustable), which can be used to determine whether the converter should operate in normal mode or non - complementary mode.

[0203] 2004: If it is lower (the result of step 2002 = N), then select / maintain normal mode (T pre = T dHL ), and set k = k1 (relative hysteresis) in step 2006;

[0204] 2008: If it is higher (the result of step 2002 = Y), then select non - complementary mode (T pre = T off -T res2 ), and set k = k2 (relative hysteresis) in step 2010;

[0205] 2012: Stop.

[0206] The operating mode described above can also be implemented in an analog form as shown in Figure 20 .

[0207] Components or elements such as Figure 15 the components or elements already visible in (e.g., resonant flyback converter 10, its associated soft - switch detector circuit, voltage feedback circuit 12, and comparator 110) are indicated with the same reference numerals in Figure 20 and will not be described in detail again for the sake of brevity.

[0208] In Figure 20 the case of the analog implementation, the calculation of the offset time T offset can be done by using a sample - and - hold circuit (S / H) 200 configured to sample the voltage SSDET at node Q.

[0209] The sampled value is applied to an operational transconductance amplifier (OTA) 202. This is an amplifier that outputs a current proportional to the difference between the voltage at its input terminals (i.e., the voltage SSDET sampled at node Q) and a fixed reference Vopt. The OTA 202 charges or discharges a capacitor C offset with a current proportional to the error between the sampled voltage SSDET and the target voltage, integrated over relative time. The voltage on the capacitor can be summed at a summing node 204 with a voltage proportional to the feedback signal FB (via a factor k ipk ) provided by a gain stage 206 to obtain the "turn - off" time T off at the output of node 204.

[0210] The "turn - off" time T at the output of node 204 is in a comparator 208off is compared with a fixed reference k*T (generated in reference source 210 in a manner well-known to a person skilled in the art) res2 to determine whether the converter should operate in normal mode or in non-complementary mode.

[0211] As Figure 20 illustrated, the high-side switch QH and the low-side switch QL are driven via respective flip-flops HFF and LFF (via their control terminals HSGD and LSGD).

[0212] The high-side switch QH is turned off, and then the current sense comparator 110 (coupled to the reset input of the flip-flop HFF) is triggered, thus implementing a peak current mode control scheme.

[0213] In normal mode, the low-side switch QL is turned on (via its set input) after a high-low dead time TdHL set in block 212L, while in non-complementary mode, a delay T determined by the comparator 214 is added via the first input of the multiplexer 216 pre .

[0214] The delay T pre is determined by the comparator 214 by comparing the following signals:

[0215] A ramp signal R, which has a predetermined slope and is reset each time the high-side switch QH is turned off (the ramp signal R is generated via a ramp generator in a manner well-known to a person skilled in the art, and the ramp generator is not visible for simplicity); and

[0216] A "turn-off" time signal T off (from the summing node 204) minus a fixed voltage T res2 , which is generated in a reference source 218 (which may at least partially correspond to the source 210) in a manner well-known to a person skilled in the art.

[0217] When another comparator 220 (coupled to the reset input of the flip-flop LFF) is triggered, the "turn-on" phase of the low-side switch QL terminates.

[0218] The comparator 220 is configured to compare the voltage T off with the ramp signal R, and also:

[0219] is coupled via block 212H to the set input of the flip-flop HFF, which block 212H provides a low-high dead time T for turning on the high-side switch QH dLH ;

[0220] is coupled via a timing block 222 to a sample and hold circuit 200 for controlling the sampling of the signal SSDET at node Q; and

[0221] Coupled to switch Q via timing block 224 SSDET to the control terminal SSGD thereof.

[0222] The operation of MUX 216 can be explained as follows.

[0223] Consider the normal mode, i.e., when the calculated T off is less than k*T res2 and assuming starting from the QH “on” condition, i.e., starting from the condition indicated by the waveform in Figure 2:

[0224] When the current detected by the current sense signal CS exceeds the threshold Ipk level, comparator 110 trips, and the output signal from comparator 110 activates the reset input R of flip-flop HFF, thereby turning off switch QH, thus entering the stage shown in Figure 3; and

[0225] The same signal passes through MUX 216 and reaches delay 212L; after the delay TdHL (set in block 212L), the set input of flip-flop LFF is activated, and then the device transitions to the stage in Figure 4.

[0226] Consider the non-complementary mode, i.e., when the calculated T off is higher than k*T res2 and assuming starting from the QH “on” condition, i.e., starting from the condition indicated by the waveform in Figure 11:

[0227] When the current detected by the current sense signal CS exceeds the threshold Ipk level, comparator 110 trips, and the output signal from comparator 110 activates the reset input of flip-flop HFF, thereby turning off switch QH, thus entering the stage shown in Figure 12;

[0228] The trip of comparator 110 resets the ramp R, and the low-side switch QL remains off even during the stage shown in Figure 13: the transition from Figure 12 to Figure 13 does not occur due to the device, but only because the current in the primary side reaches zero;

[0229] After the time determined by the input level on comparator 214, the comparator trips, and via MUX 216, the signal from this comparator reaches the set input S of flip-flop LFF (advantageously, adding a very small delay TdHL).

[0230] Summarize as follows:

[0231] In this case, MUX 216 “transmits” the signal to turn on switch QL shortly after switch QH is turned off, and

[0232] In another case, MUX 216 turns off switch QL after a delay related to (proportional to) the input at comparator 214.

[0233] In both of these cases ( Figure 15 and Figure 20 ), circuit 10 includes control circuitry 100 configured to operate drive circuitry 106 in FIG. 12 or Figure 20 the HFF, LFF, 212H, 212L in

[0234] In a first “normal” operating mode, in which phase III is maintained within (a first) turn-off time T of (a first switch / transistor QH) off and

[0235] In a second “non-complementary” operating mode, in which phase III is maintained within (a second) turn-off time T of (a first switch / transistor QH) off -T pre which (second) turn-off time has a shorter duration than the first turn-off time T off .

[0236] Selecting between these two operating modes (“normal” or “non-complementary”) involves comparing the first turn-off time T off with at least one reference threshold (such as k*T res2 , k1*T cond , k2*T cond ).

[0237] Thus, the first operating mode (“normal”) can be selected in response to the first turn-off time T off not reaching the reference threshold k*T res2 or k2*T cond .

[0238] The second operating mode (“non-complementary”) can be selected in response to the first turn-off time T off reaching at least one reference threshold (k*T res2 or k1*T cond ).

[0239] Advantageously, the hysteresis mechanism can be set with a first turn-off time T cond compared to a first reference threshold k2*T cond and a second reference threshold k1*T off , the second reference threshold k1*T cond being higher than the first reference threshold k2*T cond .

[0240] In this case:

[0241] in response to a first disconnection time T off failing to reach the (lower) first reference threshold k2*T cond a first operating mode (“normal”) is selected, and

[0242] in response to the first disconnection time T off reaching the (higher) second reference threshold k1*T cond a second operating mode (“non-complementary”) is selected.

[0243] Without prejudice to the underlying principles and without departing from the scope of protection, details and embodiments may vary even significantly from what is described by way of example only.

[0244] The scope of protection is determined by the appended claims.

Claims

1. A circuit, comprising: A first electronic switch and a second electronic switch, the first electronic switch and the second electronic switch being cascaded in a current flow path between an input node of the circuit and ground, having a current flow path through the first electronic switch and the second electronic switch; A transformer having a primary winding coupled across the second electronic switch; A capacitor coupled across a secondary winding of the transformer, wherein an output voltage from the circuit can be obtained across the capacitor; Drive circuitry configured to cause the first electronic switch and the second electronic switch to conduct and non-conduct in a series of phases, the series of phases including an energy storage phase and a subsequent simultaneous conduction phase, in the energy storage phase the first electronic switch is conducting and the second electronic switch is non-conducting, causing current flow in the primary winding of the transformer and cancelling current flow in the secondary winding of the transformer, in the simultaneous conduction phase the first electronic switch is non-conducting and the second electronic switch is conducting, causing current flow in both the primary winding of the transformer and the secondary winding of the transformer; And Control circuitry configured to: Compare a first turn-off time of the first electronic switch with at least one reference threshold; In response to the first turn-off time of the first electronic switch failing to reach the at least one reference threshold, operate the drive circuitry in a first operating mode, in which the simultaneous conduction phase is maintained during the first turn-off time of the first electronic switch; And In response to the first turn-off time of the first electronic switch reaching the at least one reference threshold, operate the drive circuitry in a second operating mode, in which the simultaneous conduction phase is maintained during a second turn-off time of the first electronic switch, wherein the second turn-off time has a shorter duration than the first turn-off time.

2. The circuit according to claim 1, wherein the control circuitry is configured to compare the first turn-off time with a first reference threshold and a second reference threshold, the second reference threshold being higher than the first reference threshold, and the control circuitry is configured to: In response to the first turn-off time failing to reach the first reference threshold, operate the drive circuitry in the first operating mode; and In response to the first turn-off time reaching the second reference threshold, operate the drive circuitry in the second operating mode.

3. The circuit according to claim 1, further comprising a series connection of the capacitor and a diode coupled across the secondary winding of the transformer.

4. The circuit according to claim 1, wherein: The drive circuitry is configured to cause neither the first electronic switch nor the second electronic switch to conduct during a dead time between the energy storage phase and the simultaneous conduction phase in the series of phases; And The control circuit device is configured to: operate the drive circuit device in the first operating mode, the dead time having a first dead time duration, and maintain the simultaneous conduction phase during the first turn-off time of the first electronic switch; and operate the drive circuit device in the second operating mode, the dead time having a second dead time duration, the second dead time duration being extended beyond the first dead time duration by a secondary-side conduction time during which current begins to flow in the secondary winding of the transformer, the second turn-off time of the first electronic switch being shortened relative to the first turn-off time of the first electronic switch by the second dead time duration.

5. The circuit according to claim 1, further comprising: a primary sensing node on the current flow line between the input node of the circuit and ground, the primary sensing node being arranged between the first electronic switch and the second electronic switch; and a soft-switch detector including a soft-switch detection node capacitively coupled to the primary sensing node and configured to be set to ground in response to another switch turning on; wherein the control circuit device is configured to: detect a soft-switch detection signal at the soft-switch detection node in response to the other switch turning off after the first electronic switch is turned on; and iteratively adjust the first turn-off time of the first electronic switch with an adjustment factor based on the difference between the soft-switch detection signal and a soft-switch reference value.

6. The circuit according to claim 1, wherein the drive circuit device includes a pulse-width modulation (PWM) generator configured to: start the simultaneous conduction phase by turning off the first electronic switch and turning on the second electronic switch at respective edges of a pulse-width modulation signal generated by the PWM generator; and generate the respective edges of the pulse-width modulation signal in the second operating mode, the respective edges being delayed relative to the respective edges of the pulse-width modulation signal generated in the first operating mode.

7. The circuit according to claim 1, wherein the drive circuit device includes a flip-flop circuit device configured to: start the simultaneous conduction phase by turning off the first electronic switch and turning on the second electronic switch in response to a reset signal and a set signal applied to the first electronic switch and the second electronic switch, respectively; and generate the reset signal and the set signal in the second operating mode, the reset signal and the set signal being delayed relative to the reset signal and the set signal generated in the first operating mode.

8. A method of operating a circuit, the circuit including a first electronic switch and a second electronic switch, a transformer, and a capacitor, the first electronic switch and the second electronic switch being cascaded in a current flow path between an input node of the circuit and ground, having a current flow path through the first electronic switch and the second electronic switch, the transformer having a primary winding coupled across the second electronic switch, the capacitor being coupled across a secondary winding of the transformer, the method including: Causing the first electronic switch and the second electronic switch to conduct and non-conduct in a series of phases by drive circuitry, the series of phases including an energy storage phase and a subsequent simultaneous conduction phase, in the energy storage phase the first electronic switch being conductive and the second electronic switch being non-conductive, causing current flow in the primary winding of the transformer and canceling current flow in the secondary winding of the transformer, in the simultaneous conduction phase the first electronic switch being non-conductive and the second electronic switch being conductive, causing current flow in both the primary winding of the transformer and the secondary winding of the transformer; Configuring for operation in a first operating mode and a second operating mode, in the first operating mode maintaining the simultaneous conduction phase during a first off-time of the first electronic switch, and in the second operating mode maintaining the simultaneous conduction phase during a second off-time of the first electronic switch, the second off-time having a duration shorter than the first off-time; And Comparing, by control circuitry, the first off-time with at least one reference threshold, and: In response to the first off-time failing to reach the at least one reference threshold, operating the drive circuitry in the first operating mode; Or In response to the first off-time reaching the at least one reference threshold, operating the drive circuitry in the second operating mode.

9. The method according to claim 8, further including: Comparing the first off-time with a first reference threshold and a second reference threshold, the second reference threshold being higher than the first reference threshold, and In response to the first off-time failing to reach the first reference threshold, operating the circuit in the first operating mode; And In response to the first off-time reaching the second reference threshold, operating the circuit in the second operating mode.

10. The method according to claim 8, further including: Causing both the first electronic switch and the second electronic switch to be non-conductive during a dead time between the energy storage phase and the simultaneous conduction phase in the series of phases; And Operating the circuit in the first operating mode, the dead time having a first dead time duration, and maintaining the simultaneous conduction phase during the first off-time; And Operating the circuit in the second operating mode, the dead time having a second dead time duration that is extended beyond the first dead time duration by a secondary side conduction time during which current begins to flow in the secondary winding of the transformer, and the second turn-off time being shortened relative to the first turn-off time by the second dead time duration.

11. The method according to claim 8, wherein the circuit includes a primary sensing node on the current flow line between the input node of the circuit and ground, the primary sensing node being disposed between the first electronic switch and the second electronic switch, and the method further includes: Detecting a soft-switching detection signal at the soft-switching detection node capacitively coupled to the primary sensing node in response to the soft-switching detection node being decoupled from ground after the first electronic switch is turned on; And Iteratively adjusting the first turn-off time of the first electronic switch with an adjustment factor based on a difference between the soft-switching detection signal and a soft-switching reference value.

12. The method according to claim 8, wherein the circuit includes a series connection of the capacitor and a diode coupled across the secondary winding of the transformer, and the method further includes providing an output voltage across the capacitor.

13. The method according to claim 8, further includes: Initiating the simultaneous conduction phase by the pulse width modulation (PWM) generator of the drive circuitry by turning off the first electronic switch and turning on the second electronic switch at respective edges of the pulse width modulation signal generated by the PWM generator; And Generating the respective edges of the pulse width modulation signal in the second operating mode by the PWM generator, the respective edges being delayed relative to the respective edges of the pulse width modulation signal generated in the first operating mode.

14. The method according to claim 8, further includes: Initiating the simultaneous conduction phase by the flip-flop circuitry of the drive circuitry by turning off the first electronic switch and turning on the second electronic switch in response to a reset signal and a set signal respectively applied to the first electronic switch and the second electronic switch; And Generating the reset signal and the set signal in the second operating mode, the reset signal and the set signal being delayed relative to the reset signal and the set signal generated in the first operating mode.

15. A method of operating a circuit including a first electronic switch and a second electronic switch, a transformer, and a capacitor, the first electronic switch and the second electronic switch being cascaded in a current flow line between an input node of the circuit and ground and having a current flow path through the first electronic switch and the second electronic switch, the transformer having a primary winding coupled across the second electronic switch, and the capacitor being coupled across a secondary winding of the transformer, the method including: The first electronic switch and the second electronic switch are turned on and off in a series of phases by a drive circuit device, the series of phases including an energy storage phase and a subsequent simultaneous conduction phase, in which the first electronic switch is on and the second electronic switch is off during the energy storage phase, causing current to flow in the primary winding of the transformer and canceling current flow in the secondary winding of the transformer, and in which the first electronic switch is off and the second electronic switch is on during the simultaneous conduction phase, causing current to flow in both the primary winding of the transformer and the secondary winding of the transformer; The first turn-off time of the first electronic switch is compared with at least one reference threshold by a control circuit device; In response to the first turn-off time of the first electronic switch failing to reach the at least one reference threshold, the control circuit device operates the drive circuit device in a first operating mode, in which the simultaneous conduction phase is maintained during the first turn-off time of the first electronic switch; The third turn-off time of the first electronic switch is compared with the at least one reference threshold by the control circuit device; And In response to the third turn-off time of the first electronic switch reaching the at least one reference threshold, the control circuit device operates the drive circuit device in a second operating mode, in which the simultaneous conduction phase is maintained during a second turn-off time of the first electronic switch, the second turn-off time having a shorter duration than the first turn-off time.

16. The method according to claim 15, further comprising: Comparing the first turn-off time with a first reference threshold and a second reference threshold, the second reference threshold being higher than the first reference threshold; In response to the first turn-off time failing to reach the first reference threshold, operating the circuit in the first operating mode; Comparing the third turn-off time with the first reference threshold and the second reference threshold; And In response to the third turn-off time reaching the second reference threshold, operating the circuit in the second operating mode.

17. The method according to claim 15, further comprising: Turning off both the first electronic switch and the second electronic switch during a dead time period between the energy storage phase and the simultaneous conduction phase in the series of phases; Operating the circuit in the first operating mode, the dead time having a first dead time duration and maintaining the simultaneous conduction phase during the first turn-off time; And Operating the circuit in the second operating mode, the dead time having a second dead time duration, the second dead time duration being extended beyond the first dead time duration by a secondary-side conduction time, during which current begins to flow in the secondary winding of the transformer, and the second turn-off time being shortened relative to the first turn-off time by the second dead time duration.

18. The method according to claim 15, wherein the circuit includes a primary sensing node on the current flow line between the input node of the circuit and the ground, the primary sensing node being arranged between the first electronic switch and the second electronic switch, and the method further includes: Detecting a soft-switching detection signal at a soft-switching detection node capacitively coupled to the primary sensing node in response to the soft-switching detection node being decoupled from the ground after the first electronic switch is turned on; And Iteratively adjusting the first turn-off time of the first electronic switch with an adjustment factor based on the difference between the soft-switching detection signal and a soft-switching reference value.

19. The method according to claim 15, further including: Starting the simultaneous conduction phase by the pulse-width modulation (PWM) generator of the drive circuit means by turning off the first electronic switch and turning on the second electronic switch at respective edges of the pulse-width modulation signal generated by the PWM generator; And Generating the respective edges of the pulse-width modulation signal by the PWM generator in the second operating mode, the respective edges being delayed with respect to the respective edges of the pulse-width modulation signal generated in the first operating mode.

20. The method according to claim 15, further including: Starting the simultaneous conduction phase by the flip-flop circuit means of the drive circuit means by turning off the first electronic switch and turning on the second electronic switch in response to a reset signal and a set signal respectively applied to the first electronic switch and the second electronic switch; And Generating the reset signal and the set signal in the second operating mode, the reset signal and the set signal being delayed with respect to the reset signal and the set signal generated in the first operating mode.

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