Transconductance amplification circuit, circuit system and electronic equipment

Abstract

The invention provides a transconductance amplification circuit, a circuit system and electronic equipment, and the circuit system comprises a differential current conversion module which is used for converting a first voltage into a first first current, and is also used for converting a second voltage into a first second current; the N differential amplification modules are adjacent in sequence; the ith differential amplification module is used for carrying out k-time amplification and k + 1-time amplification on the received ith first current and ith second current; subtracting the i second current of k + 1 times and the i first current of k times to obtain an (i + 1) first current, and subtracting the i first current of k + 1 times and the i second current of k times to obtain an (i + 1) second current; and the current amplification output unit is used for receiving the Nth first current and the Nth second current, amplifying the Nth first current and the Nth second current by k times, subtracting the k-time Nth first current and the k-time Nth second current to obtain an amplified output current, and outputting the amplified output current.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular, to a transconductance amplifier circuit, a circuit system, and an electronic device. Background Art

[0002] An operational transconductance amplifier (OTA) is an amplifier that converts an input differential voltage into an output current, so it is a voltage-controlled current source. A transconductance amplifier with a high transconductance gain plays a key role in various electronic systems, and its application scenarios usually require precise signal amplification, low-noise processing, or high-impedance matching. For example, the electrocardiogram signal amplifier amplifies microampere-level signals; the signal selection filter of a radio frequency receiver and the front-end driver in a high-speed ADC, etc.

[0003] However, in the prior art, while increasing the transconductance gain of the transconductance amplifier, the circuit power consumption will also increase proportionally, thus not meeting the power consumption requirements of the circuit. Summary of the Invention

[0004] The present invention provides a transconductance amplifier circuit, a circuit system, and an electronic device to achieve a high transconductance gain of the transconductance amplifier on the basis of low power consumption.

[0005] To solve the above technical problems, the technical solution of the present invention provides a transconductance amplifier circuit, including:

[0006] A differential current conversion module, configured to convert the input first voltage into a first first current and output it, and further configured to convert the input second voltage into a first second current and output it;

[0007] N differential amplification modules, the N differential amplification units are configured to perform N times of amplification on the first first current and the first second current, and are configured to output an Nth first current and an Nth second current. The ith differential amplification module in the N differential amplification units is configured to: receive the ith first current and the ith second current, and perform k-fold amplification and (k + 1)-fold amplification on both the received ith first current and the received ith second current; subtract the (k + 1)-fold ith second current from the k-fold ith first current to obtain an (i + 1)th first current and output it, and subtract the (k + 1)-fold ith first current from the k-fold ith second current to obtain an (i + 1)th second current and output it; a current amplification output unit, configured to receive the Nth first current and the Nth second current, and perform k-fold amplification on both the Nth first current and the Nth second current, and subtract the k-fold Nth first current from the k-fold Nth second current to obtain an amplified output current and output it;

[0008] N, k, and i are positive integers, where 1 ≤ i ≤ N and k ≥ 1.

[0009] Optionally, the differential current conversion module includes: a bias current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0010] The cathode of the bias current source is connected to the power supply voltage. The anode of the bias current source is respectively connected to the source of the first PMOS transistor and the source of the second PMOS transistor. The gate of the first PMOS transistor serves as the non-inverting input terminal of the transconductance amplifier circuit to input the first voltage. The gate of the second PMOS transistor serves as the inverting input terminal of the transconductance amplifier circuit to input the second voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both connected to the ground terminal. The drain of the first PMOS transistor outputs the first first current. The drain of the second PMOS transistor outputs the first second current. The gate of the first NMOS transistor is connected to its own drain and serves as the first output terminal of the differential current conversion module. The gate of the second NMOS transistor is connected to its own drain and serves as the second output terminal of the differential current conversion module.

[0011] Optionally, k is set to 10 and N is set to 1. Then the first differential amplification module includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

[0012] The gate of the third NMOS transistor is connected to the first output terminal of the differential current conversion module, i.e., connected to the gate of the first NMOS transistor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is respectively connected to its own drain, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The drain of the fourth PMOS transistor is respectively connected to the drain of the fourth NMOS transistor and the drain of the sixth PMOS transistor. The drain of the fifth PMOS transistor is respectively connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor. The gate of the sixth PMOS transistor is connected to its own drain and serves as the first output terminal of the first differential amplification module. The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage. The aspect ratio ratios among the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are 1:10:11:1;

[0013] The gate of the fourth NMOS transistor is respectively connected to the second output terminal of the differential current conversion module, i.e., the gate of the second NMOS transistor and the gate of the fifth NMOS transistor. The gate of the sixth NMOS transistor is connected to its own drain and serves as the second output terminal of the first differential amplification module. The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to the power supply voltage. The width-to-length ratio of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor is 1:1:1:11:10:1.

[0014] Optionally, the current amplification output unit includes a seventh PMOS transistor and the seventh NMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage. The gate of the seventh PMOS transistor is connected to the first output terminal of the first differential amplification module, i.e., the gate of the sixth PMOS transistor. The drain of the seventh PMOS transistor serves as the output terminal of the current amplification output unit and is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the first output terminal of the first differential amplification module, i.e., the gate of the sixth NMOS transistor. The source of the seventh NMOS transistor is connected to the ground terminal. The width-to-length ratio between the seventh PMOS transistor and the sixth PMOS transistor is 1:10, and the width-to-length ratio between the seventh NMOS transistor and the sixth NMOS transistor is also 1:10.

[0015] Optionally, set k to 10 and N to 2. Then the first differential amplification module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor;

[0016] The gate of the third NMOS transistor is connected to the first output terminal of the differential current conversion module, i.e., connected to the gate of the first NMOS transistor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to its own drain, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the drain of the sixth PMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor. The gate of the sixth PMOS transistor is connected to its own drain and serves as the first output terminal of the first differential amplification module. The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage. The width-to-length ratio of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor is 1:10:11:1;

[0017] The gate of the fourth NMOS transistor is connected to the second output terminal of the differential current conversion module, i.e., the gate of the second NMOS transistor and the gate of the fifth NMOS transistor. The gate of the sixth NMOS transistor is connected to its own drain and serves as the second output terminal of the first differential amplification module. The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to the power supply voltage. The width-to-length ratio of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor is 1:1:1:11:10:1.

[0018] Optionally, the second differential amplification module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor;

[0019] The gate of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor and the gate of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor and the drain of the ninth PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor and the drain of the ninth NMOS transistor. The gate of the ninth PMOS transistor is connected to its own drain and serves as the first output terminal of the second differential amplification module. The sources of the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the power supply voltage. The width-to-length ratio of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor is 1:10:11:1;

[0020] The gate of the seventh NMOS transistor is connected to the gates of the sixth NMOS transistor and the eighth NMOS transistor respectively. The gate of the ninth NMOS transistor is connected to its own drain and serves as the second output terminal of the second differential amplification module. The seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are all connected to the ground terminal. The width-to-length ratio of the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor is 1:11:10:1.

[0021] Optionally, the current amplification output unit includes a tenth PMOS transistor and the tenth NMOS transistor. The source of the tenth PMOS transistor is connected to the power supply voltage. The gate of the tenth PMOS transistor is connected to the first output terminal of the second differential amplification module, that is, the gate of the ninth PMOS transistor. The drain of the tenth PMOS transistor serves as the output terminal of the current amplification output unit and is connected to the drain of the tenth NMOS transistor. The gate of the tenth NMOS transistor is connected to the second output terminal of the first differential amplification module, that is, the gate of the ninth NMOS transistor. The source of the tenth NMOS transistor is connected to the ground terminal. The width-to-length ratio of the ninth PMOS transistor and the tenth PMOS transistor is 1:10, and the width-to-length ratio of the ninth NMOS transistor and the tenth NMOS transistor is also 1:10.

[0022] The technical solution of the present invention also provides a circuit system including the transconductance amplification circuit.

[0023] The technical solution of the present invention also provides an electronic device including the circuit system.

[0024] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0025] The transconductance amplifier circuit provided by the technical solution of the present invention is provided with a differential current conversion module to convert the input first voltage into the first first current and output it, and convert the input second voltage into the first second current and output it; and N sequentially adjacent differential amplification modules are provided, and each differential amplification module amplifies the input i-th first current and i-th second current by k times and k + 1 times respectively, and outputs the difference between the (k + 1)-times i-th second current and the k-times i-th first current as the (i + 1)-th first current, and outputs the difference between the (k + 1)-times i-th first current and the k-times i-th second current as the (i + 1)-th second current. Finally, the current amplification output unit amplifies the received N-th first current and N-th second current by k times respectively, and subtracts the k-times N-th first current and the k-times N-th second current to obtain the amplified output current, thereby realizing an exponential amplification of the difference between the first first current and the first second current by approximately (2*k)^N times. Since the power consumption generated by each differential amplification module is the same in the balanced state, the overall power consumption of the circuit is approximately the product of the number of differential amplification modules and the power consumption of a single differential amplification module. Therefore, as the number of differential amplification modules increases, the transconductance gain of the circuit increases exponentially and the power consumption of the circuit increases slowly. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic circuit structure diagram of an embodiment of a transconductance amplifier circuit;

[0027] Figure 2 is a schematic module structure diagram of the transconductance amplifier circuit provided by the embodiment of the present invention;

[0028] Figure 3 is a schematic circuit structure of the transconductance amplifier circuit provided by the embodiment of the present invention Figure 1 ;

[0029] Figure 4 is a schematic circuit structure of the transconductance amplifier circuit provided by the embodiment of the present invention Figure 2 . DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Figure 1 is a schematic circuit structure diagram of an embodiment of a transconductance amplifier circuit.

[0031] Please refer to Figure 1, this embodiment includes a first PMOS transistor mp0, a second PMOS transistor mp1, a third PMOS transistor mp2, a fourth PMOS transistor mp3, a first NMOS transistor mn0, a second NMOS transistor mn1, a third NMOS transistor mn2, a fourth NMOS transistor mn3, and a bias current source ibias. The bias current source ibias supplies the first PMOS transistor mp0 and the second PMOS transistor mp1. The first PMOS transistor mp0 and the second PMOS transistor mp1 form a differential input pair, which is used to convert the voltage difference between the first voltage input to the gate of the first PMOS transistor mp0 and the second voltage input to the gate of the second PMOS transistor mp1 into a current difference. Through the first current mirror formed by the first NMOS transistor mn0 and the second NMOS transistor mn1, the second current mirror formed by the third NMOS transistor mn2 and the fourth NMOS transistor mn3, and the third current mirror formed by the third PMOS transistor mp2 and the fourth PMOS transistor mp3, this current difference is transmitted to the output end of the transconductance amplifier. If the current ratios of the first current mirror, the second current mirror, and the third current mirror are all 1:1, the formula for the output current iout of the transconductance amplifier is:

[0032] iout = gm(V1 - V2) Equation (1)

[0033] Wherein, iout is used to represent the output current, gm is used to represent the transconductance of the differential input pair, V1 is used to represent the first voltage, and V2 is used to represent the second voltage.

[0034] At this time, the transconductance gain of the transconductance amplifier is equivalent to that of a single-stage amplifier. However, in most applications, the transconductance gain of a single-stage amplifier is troubled by insufficient transconductance gain. Since the transconductance gain of the transconductance amplifier is proportional to the output current iout, in order to increase the transconductance gain of the transconductance amplifier, the output current iout can be increased by increasing the current ratios of the first current mirror, the second current mirror, and the third current mirror, thereby increasing the circuit transconductance gain.

[0035] However, the problem with increasing the circuit transconductance gain as described above is that increasing the circuit transconductance gain by increasing the current ratios of the first current mirror, the second current mirror, and the third current mirror respectively will also increase the power consumption of the circuit synchronously. For example, set the current ratio of the first current mirror to 1:1, and set the current ratios of the second current mirror and the third current mirror to 1:100 respectively, that is, the current ratio between the third NMOS transistor mn2 and the fourth NMOS transistor mn3 is 1:100, and the current ratio between the third PMOS transistor mp2 and the fourth PMOS transistor mp3 is also 1:100. Although the output current iout increases by 100 times at this time, the power consumption of the circuit will also increase by 25.75 times synchronously. If the current ratio of the first current mirror is set to 1:1, and the current ratios of the second current mirror and the third current mirror are set to 1:1000 respectively, then although the output current iout increases by 1000 times, the power consumption of the circuit will also increase by 250.75 times synchronously. Therefore, it can be seen that the ratio between the increase multiple of the output current iout and the increase multiple of the circuit power consumption is approximately fixed at 4:1.

[0036] In view of this, the embodiments of the present invention provide a new transconductance amplifier circuit to achieve high transconductance gain of the transconductance amplifier on the basis of low power consumption.

[0037] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0038] Figure 2 It is a schematic diagram of the module structure of the transconductance amplifier circuit provided by the embodiment of the present invention.

[0039] Please refer toFigure 2 , the transconductance amplifier circuit provided by an embodiment of the present invention includes:

[0040] A differential current conversion module 10, configured to convert an input first voltage V1 into a first first current I11 and output it, and further configured to convert an input second voltage V2 into a first second current I21 and output it.

[0041] N differential amplification modules 20, the N differential amplification units 20 are configured to perform N - times amplification on the first first current I11 and the first second current I22, and are configured to output the N - th first current I1 N and the N - th second current I2 N , the i - th differential amplification module 20 among the N differential amplification units 20 is configured to:

[0042] Receive the i - th first current I1 i and the i - th second current I2 i , and perform k - fold amplification and (k + 1) - fold amplification on the received i - th first current I1 i , and perform k - fold amplification and (k + 1) - fold amplification on the received i - th second current I2 i .

[0043] Subtract the (k + 1) - fold i - th second current I2 i from the k - fold i - th first current I1 i to obtain the (i + 1) - th first current I1 i+1 and output it, and subtract the (k + 1) - fold i - th first current I1 i from the k - fold i - th second current I2 i to obtain the (i + 1) - th second current I1 i+2 and output it.

[0044] Specifically, when i is equal to 1, the first differential amplification module 20 receives the first first current I11 and the first second current I21 output by the differential current conversion module 10, and outputs the second first current I12 and the second second current I22 to the second differential amplification module 20. When i is greater than 1, the i - th differential amplification module 20 receives the i - th first current I1i and the i - th second current I2i output by the (i - 1) - th differential amplification module 20, and outputs the (i + 1) - th first current I1i + 1 and the (i + 1) - th second current I1i + 2 to the (i + 1) - th differential amplification module 20.

[0045] A current amplification output unit 30 is configured to receive the Nth first current I1N and the Nth second current I2N, amplify both the Nth first current I1N and the Nth second current I2N by k times, and subtract the k-fold Nth first current I1N from the k-fold Nth second current I2N to obtain an amplified output current IOUT and output it.

[0046] N, k, and i are positive integers, 1 ≤ i < N, and k is greater than or equal to 1.

[0047] In the embodiment of the present invention, the differential current conversion module 10 first converts the input first voltage V1 into the corresponding first current of the first one, and converts the input second voltage V2 into the second current of the first one. In order to increase the output current of the transconductance amplification circuit and thus increase the transconductance gain of the circuit, the embodiment of the present invention provides N sequentially adjacent differential amplification modules 20, and each differential amplification module 20 is configured to perform differential amplification on the input current and output the corresponding differential current. Therefore, the first current of the first one and the second current of the first one are sequentially differentially amplified from the first differential amplification module 20 to the Nth differential amplification module 20, so that the first current of the first one and the second current of the first one are amplified N times. Also, because each differential amplification module 20 amplifies both the ith first current and the ith second current by k times and k + 1 times, and outputs the difference between the (k + 1)-fold ith second current and the k-fold ith first current as the (i + 1)th first current, and outputs the difference between the (k + 1)-fold ith first current and the k-fold ith second current as the (i + 1)th second current.

[0048] Finally, the current amplification output unit 30 amplifies both the received Nth first current and the Nth second current by k times, and subtracts the k-fold Nth first current from the k-fold Nth second current to obtain the amplified output current IOUT, thereby realizing an exponential amplification of the difference between the first current of the first one and the second current of the first one by approximately (2*k)N times. Since in the balanced state, the power consumption generated by each differential amplification module 20 is the same, the overall power consumption of the circuit is approximately the product of the number of differential amplification modules 20 and the power consumption of a single differential amplification module 20. Thus, as the number of differential amplification modules 20 increases, an exponential increase in the transconductance gain of the circuit is achieved and the power consumption of the circuit increases slowly.

[0049] It should be noted that the specific values of k and N can be adaptively adjusted according to the requirements for the transconductance gain and power consumption of the transconductance amplification circuit in actual applications, and are not limited herein. For example, if the circuit requires a transconductance gain of several hundred times, k can be selected as 10 and N can be selected as 1. If the circuit requires a transconductance gain of several thousand times, k can be selected as 10 - 15 and N can be selected as 2.

[0050] Taking k equal to 10 and N equal to 1 as an example, the specific circuit of the transconductance amplifier circuit provided by the embodiment of the present invention will be described in detail as follows:

[0051] Figure 3 Schematic diagram of the circuit structure of the transconductance amplifier circuit provided by the embodiment of the present invention Figure 1 。

[0052] Please refer to Figure 2 and Figure 3 , as a specific implementation manner, the differential current conversion module 10 includes: a bias current source Ibias, a first PMOS transistor MP0, a second PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2.

[0053] The input end of the bias current source Ibias is connected to the power supply voltage VCC. The output end of the bias current source Ibias is respectively connected to the source electrodes of the first PMOS transistor MP0 and the second PMOS transistor MP1. The gate of the first PMOS transistor MP0 serves as the non-inverting input end of the transconductance amplifier circuit to input the first voltage V1. The gate of the second PMOS transistor MP1 serves as the inverting input end of the transconductance amplifier circuit to input the second voltage V2. The drain of the first PMOS transistor MP0 is connected to the drain of the first NMOS transistor MN1. The drain of the second PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2. The source electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to the ground terminal. The drain of the first PMOS transistor MP0 outputs the first first current I11. The drain of the second PMOS transistor MP1 outputs the first second current I22. The gate of the first NMOS transistor MN1 is connected to its own drain and serves as the first output end of the differential current conversion module 10. The gate of the second NMOS transistor MN2 is connected to its own drain and serves as the second output end of the differential current conversion module 10.

[0054] Please continue to refer to Figure 3 , the first differential amplification module 20 includes: a third NMOS transistor MN0, a fourth NMOS transistor MN3, a fifth NMOS transistor MN4, a sixth NMOS transistor MN5, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a fifth PMOS transistor MP4, and a sixth PMOS transistor MP5.

[0055] The gate of the third NMOS transistor MN0 is connected to the first output terminal of the differential current conversion module 10, that is, connected to the gate of the first NMOS transistor MN1. The drain of the third NMOS transistor MN0 is connected to the drain of the third PMOS transistor MP2. The gate of the third PMOS transistor MP2 is connected to its own drain, the gate of the fourth PMOS transistor MP3, and the gate of the fifth PMOS transistor MP4. The drain of the fourth PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN3 and the drain of the sixth PMOS transistor MP5. The drain of the fifth PMOS transistor MP4 is connected to the drain of the fifth NMOS transistor MN4 and the drain of the sixth NMOS transistor MN5. The gate of the sixth PMOS transistor MP5 is connected to its own drain and serves as the first output terminal of the first differential amplification module 20. The sources of the third PMOS transistor MP2, the fourth PMOS transistor MP3, the fifth PMOS transistor MP4, and the sixth PMOS transistor MP5 are all connected to the power supply voltage VCC. The width-to-length ratio of the third PMOS transistor MP2, the fourth PMOS transistor MP3, the fifth PMOS transistor MP4, and the sixth PMOS transistor MP5 is 1:10:11:1.

[0056] The gate of the fourth NMOS transistor MN3 is connected to the second output terminal of the differential current conversion module 10, that is, the gate of the second NMOS transistor MN2 and the gate of the fifth NMOS transistor MN4. The gate of the sixth NMOS transistor MN5 is connected to its own drain and serves as the second output terminal of the first differential amplification module 20. The sources of the third NMOS transistor MN0, the fourth NMOS transistor MN3, the fifth NMOS transistor MN4, and the sixth NMOS transistor MN5 are all connected to the ground terminal. The width-to-length ratio of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN0, the fourth NMOS transistor MN3, the fifth NMOS transistor MN4, and the sixth NMOS transistor MN5 is 1:1:1:11:10:1.

[0057] Please continue to refer to Figure 3, the current amplification output unit 30 includes a seventh PMOS transistor MP6 and the seventh NMOS transistor MN6. The source of the seventh PMOS transistor MP6 is connected to the power supply voltage VCC. The gate of the seventh PMOS transistor MP6 is connected to the first output terminal of the first differential amplification module 20, that is, the gate of the sixth PMOS transistor MP5. The drain of the seventh PMOS transistor MP6 serves as the output terminal of the current amplification output unit 30 and is connected to the drain of the seventh NMOS transistor MN6. The gate of the seventh NMOS transistor MN6 is connected to the second output terminal of the first differential amplification module 20, that is, the gate of the sixth NMOS transistor MN5. The source of the seventh NMOS transistor MN6 is connected to the ground terminal. The width-to-length ratio between the seventh PMOS transistor MP6 and the sixth PMOS transistor MP5 is 1:10, and the width-to-length ratio between the seventh NMOS transistor MN6 and the sixth NMOS transistor MN5 is also 1:10.

[0058] The following Figure 3 explains the working principle of the transconductance amplification circuit shown:

[0059] The bias current source Ibias outputs a bias current to the source of the first PMOS transistor MP0 and the source of the second PMOS transistor MP1.

[0060] The first PMOS transistor MP0 and the second PMOS transistor MP1 form a PMOS differential input pair, which is used to convert both the input first voltage V1 and the second voltage V2 into currents, and respectively output the first first current I11 and the first second current I12 from the drain of the first PMOS transistor MP0 and the drain of the second PMOS transistor MP1. Among them, the formula for the difference between the first first current and the first second current is:

[0061] I11 - I21 = gm * (V2 - V1) Formula (2)

[0062] Equivalently written as I21 - I11 = gm * (V1 - V2) Formula (3)

[0063] Among them, I11 is used to represent the first first current, I21 is used to represent the first second current, gm is used to represent the differential pair transconductance of the differential input pair formed by the first PMOS transistor and the second PMOS transistor, V1 is used to represent the first voltage, and V2 is used to represent the second voltage.

[0064] Since the first NMOS transistor MN1 and the third NMOS transistor MN0 form a current mirror and the ratio of their width-to-length ratios is 1:1, the first first current flowing through the first NMOS transistor MN1 is mirrored to the drain of the third NMOS transistor MN0 and flows through the third PMOS transistor MP2.

[0065] Since the third PMOS transistor MP2 and the fourth PMOS transistor MP3 form a current mirror and the ratio of their width-to-length ratios is 1:10, the first first current flowing through the third PMOS transistor MP2 is mirrored and amplified ten times to the fourth PMOS transistor MP3. The second NMOS transistor MN2 and the fourth NMOS transistor MN3 form a current mirror and the ratio of their width-to-length ratios is 1:11, so the first second current flowing through the second NMOS transistor MN2 is mirrored and amplified eleven times to the drain of the fourth NMOS transistor MN3. According to Kirchhoff's current law, the formula for the current flowing through the sixth PMOS transistor MP5, which is the second first current, is:

[0066] I12 = 11 * I21 - 10 * I11 Equation (4)

[0067] where I12 is used to represent the second first current.

[0068] Since the third PMOS transistor MP2 and the fifth NMOS transistor MN4 form a current mirror and the ratio of their width-to-length ratios is 1:11, the first first current flowing through the third NMOS transistor MN0 is mirrored and amplified eleven times to the drain of the fifth NMOS transistor MN4. The second NMOS transistor MN2 and the fifth NMOS transistor MN4 form a current mirror and the ratio of their width-to-length ratios is 1:10, so the first second current flowing through the second NMOS transistor MN2 is mirrored and amplified ten times to the drain of the fifth NMOS transistor MN4. According to Kirchhoff's current law, the formula for the current flowing through the sixth NMOS transistor MN5, which is the second second current, is:

[0069] I22 = 11 * I11 - 10 * I21 Equation (5)

[0070] where I22 is used to represent the second second current.

[0071] Since the sixth PMOS transistor MP5 and the seventh PMOS transistor MP6 in the current amplification output unit 30 also form a current mirror and the aspect ratio of the two is 1:10, the second first current flowing through the sixth PMOS transistor MP5 is mirrored and amplified ten times to the drain of the seventh PMOS transistor MP6. Since the sixth NMOS transistor MN5 and the seventh NMOS transistor MN6 in the current amplification output unit 30 also form a current mirror and the aspect ratio of the two is 1:10, the second second current flowing through the sixth NMOS transistor MN5 is mirrored and amplified ten times to the drain of the seventh NMOS transistor MN6. According to Kirchhoff's current law, the formula for the amplified output current IOUT can be obtained as follows:

[0072] IOUT = 10 * I12 - 10 * I22 Formula (6)

[0073] Wherein, IOUT is used to represent the amplified output current IOUT.

[0074] Combining Formula (4) and Formula (5), it can be further obtained that IOUT = 210 * gm(V1 - V2) Formula (6)

[0075] It can be clearly seen from the formula of the amplified output current IOUT above that compared with the gain of a single-stage amplifier, the output current in this embodiment is amplified 210 times, thereby achieving a greater circuit gain.

[0076] The circuit power consumption of this embodiment is calculated as follows:

[0077] According to circuit principles, the power consumption of a transconductance amplifier circuit consists of static power consumption and dynamic power consumption. Compared with the static power consumption, the dynamic power consumption of the circuit can be basically ignored. Therefore, the power consumption calculation of the transconductance amplifier circuit below refers to the static power consumption of the circuit.

[0078] When the circuit is in an equilibrium state, that is, when the first voltage V1 is equal to the second voltage V2, the static power consumption of the circuit is equal to the sum of the power consumption of each branch in the circuit. Therefore, the formula for the static power consumption of the circuit is as follows:

[0079] Pstatic = PMN2 + PMN0 + PMN1 + PMN3 + PMP4 + PMN6 Formula (7)

[0080] Also, because PMN2 = IMN2 * VCC Formula (8)

[0081] PMN0 = IMN0 * VCC Formula (9)

[0082] PMN1 = IMN1 * VCC Formula (10)

[0083] P MN3 = I MN3 * VCC, Equation (11)

[0084] P MP4 = I MP4 * VCC, Equation (12)

[0085] P MN6 = I MN6 * VCC, Equation (13)

[0086] Also, since the first voltage V1 is equal to the second voltage V2, then I MN0 = I MN1 = I bias / 2, Equation (14)

[0087] where I bias is used to represent the bias current output by the bias current source Ibias.

[0088] Combining the aspect ratio ratios of the MOS transistors in each of the above current mirrors and Equations (7) to (14), the static power consumption of the circuit can be further obtained as follows:

[0089] Pstatic = 17.5 * Ibias * VCC, Equation (15)

[0090] It can be seen from Equation (15) that compared with the power consumption of the single-stage amplifier, the power consumption of the embodiment of the present invention only increases by 8.75 times.

[0091] Therefore, it can be seen from the above embodiments that under the condition that k is set to 10 and N is set to 1, this embodiment achieves a current as high as 220 times that of the single-stage amplifier, but the circuit power consumption only increases by 8.75 times.

[0092] It should be added that the output current of the single-stage amplifier is as shown in Equation (1), and the power consumption of the single-stage amplifier in the balanced state is equal to 2 * Ibias.

[0093] The following takes k equal to 10 and N equal to 2 as an example to detail the specific circuit of the transconductance amplifier circuit provided by another embodiment of the present invention:

[0094] Figure 4 Schematic diagram of the circuit structure of the transconductance amplifier circuit provided by the embodiment of the present invention Figure 1 .

[0095] Please refer to Figure 4 , as a specific implementation manner, the circuit structures of the differential current conversion module 10 and the first differential amplification module 40 are both the same as those of the embodiment shown in Figure 3 , and will not be elaborated here.

[0096] The second differential amplification module 40 includes a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, a ninth PMOS transistor MP8, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, and a ninth NMOS transistor MN8.

[0097] The gate of the seventh PMOS transistor MP6 is respectively connected to the gate of the sixth PMOS transistor MP5 and the gate of the eighth PMOS transistor MP7. The drain of the seventh PMOS transistor MP6 is respectively connected to the drain of the seventh NMOS transistor MN6 and the drain of the ninth PMOS transistor MP8. The drain of the eighth PMOS transistor MP7 is respectively connected to the drain of the eighth NMOS transistor MN7 and the drain of the ninth NMOS transistor MN8. The gate of the ninth PMOS transistor MP8 is connected to its own drain and serves as the first output terminal of the second differential amplification module 40. The sources of the seventh PMOS transistor MP6, the eighth PMOS transistor MP7, and the ninth PMOS transistor MP8 are all connected to the power supply voltage VCC. The aspect ratio ratios among the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, the eighth PMOS transistor MP7, and the ninth PMOS transistor MP8 are 1:10:11:1.

[0098] The gate of the seventh NMOS transistor MN6 is respectively connected to the gate of the sixth NMOS and the gate of the eighth NMOS transistor MN7. The gate of the ninth NMOS transistor MN8 is connected to its own drain and serves as the second output terminal of the second differential amplification module 40. The seventh NMOS transistor MN6, the eighth NMOS transistor MN7, and the ninth NMOS transistor MN8 are all connected to the ground terminal. The aspect ratio ratios among the sixth NMOS transistor MN5, the seventh NMOS transistor MN6, the eighth NMOS transistor MN7, and the ninth NMOS transistor MN8 are 1:11:10:1.

[0099] Please continue to refer to Figure 4, the current amplification output unit 30 includes a tenth PMOS transistor MP9 and the tenth NMOS transistor MN9. The source of the tenth PMOS transistor MP9 is connected to the power supply voltage VCC. The gate of the tenth PMOS transistor MP9 is connected to the first output terminal of the second differential amplification module 40, that is, the gate of the ninth PMOS transistor MP8. The drain of the tenth PMOS transistor MP9 serves as the output terminal of the current amplification output unit 30 and is connected to the drain of the tenth NMOS transistor MN9. The gate of the tenth NMOS transistor MN9 is connected to the second output terminal of the first differential amplification module 40, that is, the gate of the ninth NMOS transistor MN8. The source of the tenth NMOS transistor MN9 is connected to the ground terminal. The aspect ratio ratio between the ninth PMOS transistor MP8 and the tenth PMOS transistor MP9 is 1:10, and the aspect ratio ratio between the ninth NMOS transistor MN8 and the tenth NMOS transistor MN9 is also 1:10.

[0100] The working principle of the following Figure 4 shown transconductance amplification circuit will be elaborated:

[0101] Since the working principles and output signals of the differential current conversion module 10 and the first differential amplification module 40 in this embodiment are both the same as those in Figure 3 the shown embodiment, they will not be elaborated here.

[0102] Since the sixth PMOS transistor MP5 respectively forms a current mirror structure with the seventh PMOS transistor MP6 and the eighth PMOS transistor MP7, and the aspect ratio ratio among the sixth PMOS transistor MP5, the seventh PMOS transistor MP6, and the eighth PMOS transistor MP7 is 1:10:11. Therefore, the second first current flowing through the sixth PMOS transistor MP5 is mirror - amplified eleven times to the eighth PMOS transistor MP7 and ten times to the seventh PMOS transistor MP6.

[0103] Since the sixth NMOS transistor MN5 also respectively forms a current mirror structure with the seventh NMOS transistor MN6 and the eighth NMOS transistor MN7, and the aspect ratio ratio among the sixth NMOS transistor MN5, the seventh NMOS transistor MN6, and the eighth NMOS transistor MN7 is 1:11:11. Therefore, the second second current flowing through the sixth NMOS transistor MN5 is mirror - amplified ten times to the eighth NMOS transistor MN7 and eleven times to the seventh NMOS transistor MN6.

[0104] Therefore, according to Kirchhoff's current law, the formula for the current flowing through the ninth PMOS transistor MP8, that is, the third first current, is:

[0105] I13 = 11 * I22 - 10 * I12 Equation (16)

[0106] Among them, I13 is used to represent the 3rd first current.

[0107] The formula for the current flowing through the ninth NMOS transistor MN8, which is the 3rd second current, can be obtained as follows:

[0108] I23 = 11 * I12 - 10 * I22 Equation (17)

[0109] Among them, I23 is used to represent the 3rd second current.

[0110] Since the ninth PMOS transistor MP8 and the tenth PMOS transistor MP9 in the current amplification output unit 30 also form a current mirror and the aspect ratio of the two is 1:10, the 3rd first current flowing through the ninth PMOS transistor MP8 is mirrored and amplified ten times to the drain of the tenth PMOS transistor MP9. Since the ninth NMOS transistor MN8 and the tenth NMOS transistor MN9 in the current amplification output unit 30 also form a current mirror and the aspect ratio of the two is 1:10, the 3rd second current flowing through the ninth NMOS transistor MN8 is mirrored and amplified ten times to the drain of the tenth NMOS transistor MN9.

[0111] Therefore, according to Kirchhoff's current law, the formula for the amplified output current IOUT can be obtained as follows:

[0112] IOUT = 10 * I13 - 10 * I23 Equation (18)

[0113] Combining Equation (4), (5), (16) and Equation (17), it can be further obtained that IOUT = 4410 * gm(V1 - V2) Equation (18)

[0114] It can be clearly seen from the formula of the amplified output current IOUT above that compared with the gain of a single-stage amplifier, the output current of this embodiment is amplified 4410 times, thus achieving a greater circuit gain.

[0115] Next, the circuit power consumption of this embodiment will be calculated as follows:

[0116] P static = P MN2 + P MN0 + P MN1 + P MN3 + P MP4 + P MN6 + P MP7 + P MN9 Equation (19)

[0117] Also, because P MP7 = P MP7 * VCC Equation (20)

[0118] P MN9 = P MN9 * VCC Equation (21)

[0119] In the circuit equilibrium state, by combining Formula (8) to Formula (14), Formula (20) and Formula (21), and combining the width-to-length ratio of the MOS transistors in each current mirror above, the static power consumption of the circuit can be further obtained as follows:

[0120] Pstatic = 28.5 * Ibias * VCC Formula (21)

[0121] It can be seen from Formula (21) that compared with the power consumption of the single-stage amplifier, the power consumption of the embodiment of the present invention only increases by 14.25 times.

[0122] Therefore, it can be seen from the above embodiments that under the condition that k is set to 10 and N is set to 2, the current of this embodiment is approximately 20 times that of the Figure 3 shown embodiment, but the circuit power consumption only increases by 1.6 times.

[0123] When k is set to 10 and N is set to 3, according to the Figure 3 shown circuit to the Figure 4 shown circuit change rule, adaptively change the Figure 4 shown circuit, and thus according to the changed circuit and the above Formula (16) and Formula (17), it can be obtained that:

[0124] IOUT = 92610 * gm(V1 - V2) Formula (22)

[0125] And the circuit power consumption is only:

[0126] Pstatic = 39.5 * Ibias * VCC Formula (23)

[0127] Therefore, it can be seen from Formula (6), Formula (15), Formula (18), Formula (21), Formula (22) and Formula (23) that when k is 10, as N increases, the current of the circuit increases exponentially by approximately 2 * k times, that is, 20 times, while the power consumption of the circuit only increases one by one by k * Ibias * VCC. And because the transconductance gain of the circuit is proportional to the current, the transconductance amplifier circuit provided by the embodiment of the present invention realizes that the transconductance gain of the circuit increases exponentially as N increases, but makes the circuit power consumption increase fixedly as N increases, thereby realizing a low-power and high-gain transconductance amplifier circuit.

[0128] In summary, the transconductance amplifier circuit provided by the embodiment of the present invention sets a differential current conversion module to convert the input first voltage into the first first current and output it, and convert the input second voltage into the first second current and output it; and sets N sequentially adjacent differential amplification modules, and each differential amplification module amplifies the input i-th first current and i-th second current by k times and k + 1 times respectively, and outputs the difference between the (k + 1)-times i-th second current and the k-times i-th first current as the (i + 1)-th first current, and outputs the difference between the (k + 1)-times i-th first current and the k-times i-th second current as the (i + 1)-th second current. Finally, the current amplification output unit amplifies the received N-th first current and N-th second current by k times respectively, and subtracts the k-times N-th first current and k-times N-th second current to obtain the amplified output current, thereby realizing an exponential amplification of the difference between the first first current and the first second current by approximately (2*k)^N times. Since the power consumption generated by each differential amplification module is the same in the balanced state, the overall power consumption of the circuit is approximately the product of the number of differential amplification modules and the power consumption of a single differential amplification module. Therefore, as the number of differential amplification modules increases, the transconductance gain of the circuit increases exponentially and the power consumption of the circuit increases slowly.

[0129] The embodiment of the present invention also provides a circuit system, including the transconductance amplifier circuit.

[0130] The embodiment of the present invention also provides an electronic device, including the circuit system.

[0131] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A transconductance amplifier circuit, characterized in that, The transconductance amplifier circuit includes: A differential current conversion module, configured to convert the input first voltage into a first current and output it, and also configured to convert the input second voltage into a second current and output it; N differential amplification modules, where the N differential amplification units are configured to perform N - stage amplification on the first current and the second current, and output the Nth first current and the Nth second current. The ith differential amplification module among the N differential amplification units is configured to: receive the ith first current and the ith second current, and perform k - fold amplification and (k + 1) - fold amplification on both the received ith first current and the ith second current; subtract the (k + 1) - fold ith second current from the k - fold ith first current to obtain and output the (i + 1)th first current, and subtract the (k + 1) - fold ith first current from the k - fold ith second current to obtain and output the (i + 1)th second current; A current amplification and output unit, configured to receive the Nth first current and the Nth second current, amplify both the Nth first current and the Nth second current by k times, and subtract the k - fold Nth first current from the k - fold Nth second current to obtain and output an amplified output current; N, k, and i are positive integers, 1 ≤ i ≤ N, and k is greater than or equal to 1.

2. The transconductance amplifier circuit according to claim 1, wherein The differential current conversion module includes: a bias current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The cathode of the bias current source is connected to the power supply voltage, the anode of the bias current source is respectively connected to the source electrodes of the first PMOS transistor and the second PMOS transistor. The gate of the first PMOS transistor serves as the non - inverting input terminal of the transconductance amplifier circuit to input the first voltage, the gate of the second PMOS transistor serves as the inverting input terminal of the transconductance amplifier circuit to input the second voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The source electrodes of the first NMOS transistor and the second NMOS transistor are both connected to the ground terminal. The drain of the first PMOS transistor outputs the first current, the drain of the second PMOS transistor outputs the second current. The gate of the first NMOS transistor is connected to its own drain and serves as the first output terminal of the differential current conversion module, and the gate of the second NMOS transistor is connected to its own drain and serves as the second output terminal of the differential current conversion module.

3. The transconductance amplifier circuit according to claim 2, wherein When k is set to 10 and N is set to 1, the first differential amplification module includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The gate of the third NMOS transistor is connected to the first output terminal of the differential current conversion module, that is, connected to the gate of the first NMOS transistor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to its own drain, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the drain of the sixth PMOS transistor respectively. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor respectively. The gate of the sixth PMOS transistor is connected to its own drain and serves as the first output terminal of the first differential amplification module. The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage. The ratio of the aspect ratios of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor is 1:10:11:1; The gate of the fourth NMOS transistor is connected to the second output terminal of the differential current conversion module, that is, the gate of the second NMOS transistor and the gate of the fifth NMOS transistor. The gate of the sixth NMOS transistor is connected to its own drain and serves as the second output terminal of the first differential amplification module. The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to the power supply voltage. The ratio of the aspect ratios of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor is 1:1:1:11:10:

1.

4. The transconductance amplifier circuit according to claim 3, wherein The current amplification output unit includes a seventh PMOS transistor and a seventh NMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage. The gate of the seventh PMOS transistor is connected to the first output terminal of the first differential amplification module, that is, the gate of the sixth PMOS transistor. The drain of the seventh PMOS transistor serves as the output terminal of the current amplification output unit and is connected to the drain of the seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the first output terminal of the first differential amplification module, that is, the gate of the sixth NMOS transistor. The source of the seventh NMOS transistor is connected to the ground terminal. The ratio of the aspect ratios of the seventh PMOS transistor and the sixth PMOS transistor is 1:10, and the ratio of the aspect ratios of the seventh NMOS transistor and the sixth NMOS transistor is also 1:

10.

5. The transconductance amplifier circuit according to claim 2, wherein Set k to 10 and N to 2, then the first differential amplification module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The gate of the third NMOS transistor is connected to the first output terminal of the differential current conversion module, i.e., connected to the gate of the first NMOS transistor. The drain of the third NMOS transistor is connected to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to its own drain, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the drain of the sixth PMOS transistor respectively. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor respectively. The gate of the sixth PMOS transistor is connected to its own drain and serves as the first output terminal of the first differential amplification module. The sources of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage. The aspect ratio ratios among the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are 1:10:11:1; The gate of the fourth NMOS transistor is connected to the second output terminal of the differential current conversion module, i.e., the gate of the second NMOS transistor and the gate of the fifth NMOS transistor. The gate of the sixth NMOS transistor is connected to its own drain and serves as the second output terminal of the first differential amplification module. The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all connected to the power supply voltage. The aspect ratio ratios among the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are 1∶1:1:11:10:

1.

6. The transconductance amplifier circuit according to claim 5, wherein The second differential amplification module includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The gate of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor and the gate of the eighth PMOS transistor respectively. The drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor and the drain of the ninth PMOS transistor respectively. The drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor and the drain of the ninth NMOS transistor respectively. The gate of the ninth PMOS transistor is connected to its own drain and serves as the first output terminal of the second differential amplification module. The sources of the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the power supply voltage. The aspect ratio ratios among the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are 1:10:11:1; The gate of the seventh NMOS transistor is connected to the gate of the sixth NMOS transistor and the gate of the eighth NMOS transistor respectively. The gate of the ninth NMOS transistor is connected to its own drain and serves as the second output terminal of the second differential amplification module. The seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are all connected to the ground terminal. The width-to-length ratio among the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor is 1:11:10:

1.

7. The transconductance amplifier circuit according to claim 6, wherein The current amplification output unit includes a tenth PMOS transistor and a tenth NMOS transistor. The source of the tenth PMOS transistor is connected to the power supply voltage. The gate of the tenth PMOS transistor is connected to the first output terminal of the second differential amplification module, i.e., the gate of the ninth PMOS transistor. The drain of the tenth PMOS transistor serves as the output terminal of the current amplification output unit and is connected to the drain of the tenth NMOS transistor. The gate of the tenth NMOS transistor is connected to the second output terminal of the first differential amplification module, i.e., the gate of the ninth NMOS transistor. The source of the tenth NMOS transistor is connected to the ground terminal. The width-to-length ratio between the ninth PMOS transistor and the tenth PMOS transistor is 1:10, and the width-to-length ratio between the ninth NMOS transistor and the tenth NMOS transistor is also 1:

10.

8. A circuit system, characterized in that, Comprising the transconductance amplification circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that, Comprising the circuit system according to claim 8.

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