Low area and power multi-bit flip-flop

Abstract

The invention relates to a low area and power multi-bit flip-flop. Embodiments disclosed herein relate to device testing using scan chains containing various flip-flop devices in a multi-bit flip-flop configuration. A circuit arrangement comprised herein includes a first flip-flop sub-circuit (110-1) and a second flip-flop sub-circuit (110-2). A first flip-flop sub-circuit (110-1) is coupled to receive a clock signal (103) and an input, and a second flip-flop circuit (110-2) is coupled to the first flip-flop sub-circuit (110-1). The first flip-flop sub-circuit (110-1) includes an input sub-circuit (120), a first latch sub-circuit (131), a first latch tri-state (140), a second latch sub-circuit (145), and a first output inverter (155). The second latch sub-circuit (145) includes a first pass gate (149), a second inverter (146), and a third inverter (152).

Description

Field of the Invention

[0001] This disclosure generally relates to multi-bit flip-flop circuits, and more particularly to performing scan chain testing with such multi-bit flip-flop circuits. Background Art

[0002] In digital logic circuits, flip-flops and latches may be included to store state information and ensure proper sequencing of logic in an electronic device. The output of a flip-flop may transition at specific times determined based on the state of a clock signal (e.g., switching states from "0" to "1" and from "1" to "0"). Outside of these times, the flip-flop maintains its current state. In this way, the flip-flop stores state data, such as "0" or "1", based on the state of the clock signal and the state of the data input.

[0003] As the complexity of digital system functionality increases, optimization of the individual standard cell areas of digital circuits, such as flip-flops and latches, becomes increasingly critical. To reduce the design area and power consumption of digital circuits, existing solutions may include multi-bit flip-flops in place of single-bit flip-flops. Multi-bit flip-flops can be used to store multiple bit signals using a single clock signal, and thus, they can save the area where multiple single-bit flip-flops could be used.

[0004] However, the problem is that various multi-bit flip-flops currently available, although reducing the design area relative to single-bit flip-flops, contain a large number of transistors. Therefore, for increasingly complex digital systems, the existing architectures of multi-bit flip-flops may not achieve power and area savings. Summary of the Invention

[0005] The various embodiments disclosed herein relate to multi-bit flip-flop circuits, and more particularly to the architecture of flip-flop circuits in multi-bit flip-flop circuits. In an exemplary embodiment, a circuit device is provided. The circuit device includes a first flip-flop sub-circuit coupled to receive a clock signal and an input, and a second flip-flop sub-circuit coupled to receive the clock signal and coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit coupled to receive the clock signal and the input, a first latch sub-circuit coupled to receive the clock signal and coupled to the input sub-circuit, a first latch tri-state coupled to receive the clock signal and coupled to the first latch sub-circuit, a second latch sub-circuit coupled to receive the clock signal and coupled to the first latch tri-state, and a first output inverter coupled to the first latch tri-state and the second latch sub-circuit. The second latch sub-circuit includes a first transmission gate coupled to the first latch tri-state, the first output inverter, and the second flip-flop sub-circuit, a first inverter coupled to the first transmission gate, and a second inverter coupled to the first inverter, the first latch tri-state, and the first output inverter. The second flip-flop sub-circuit includes a second transmission gate coupled to receive the clock signal and coupled to the first transmission gate of the second latch sub-circuit, a first clock tri-state coupled to receive the clock signal and coupled to the second transmission gate, a third latch sub-circuit coupled to receive the clock signal and coupled to the clock tri-state, a second latch tri-state coupled to receive the clock signal and coupled to the third latch sub-circuit, a fourth latch sub-circuit coupled to receive the clock signal and coupled to the second latch tri-state, and a second output inverter coupled to the second latch tri-state and the fourth latch sub-circuit. The fourth latch sub-circuit includes a third transmission gate coupled to the second latch tri-state and the second output inverter, a third inverter coupled to the third transmission gate, and a fourth inverter coupled to the third inverter, the second latch tri-state, and the second output inverter.

[0006] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. It is understood that this summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and 1B (collectively as FIG. 1) illustrate an example multi-bit flip-flop circuit in accordance with one embodiment.

[0008] Figure 2 illustrate an example operating environment for performing logic with a multi-bit flip-flop circuit in accordance with one embodiment.

[0009] The figures are not necessarily drawn to scale. In the figures, like reference numerals refer to corresponding parts throughout the several views. In some embodiments, components or operations may be separated into different blocks or combined into a single block. Detailed Description

[0010] Embodiments of the present disclosure are described in a particular context, such as in multi-bit flip-flop circuits, master-slave latch circuits, digital logic, and inverter circuits and the like. Some embodiments may use other circuits, digital logic components, topologies, and applications that exhibit increased transistor efficiency and other characteristics based on a reduction in the number of transistors in a system or circuit.

[0011] Described herein are enhanced components, systems, and architectures related to multi-bit flip-flop circuits used in digital systems or circuits to perform multiple bit-level operations on logic signals. In an electronic system, a flip-flop circuit may store the logical state of an input to the flip-flop circuit, such as scan data during a test phase or input data during real-time operation. Flip-flops and latches are examples of logical components within a digital circuit system that may store state data (e.g., "0" or "1") based on an input (e.g., an input data signal) to the flip-flop at a time specified by a clock signal. Some example flip-flops include one or more inverters that may be triggered by a clock signal to store the state of an input data signal.

[0012] Multi-bit flip-flops may be included in a system to store such logical states among several different data inputs. Such multi-bit flip-flops may be tested by scan chain-linking several bits of the multi-bit flip-flop circuit or individual flip-flop circuits together. A scan data input may be provided to the first flip-flop circuit in the multi-bit flip-flop circuit and measured at the output node of the multi-bit flip-flop circuit to ensure the accuracy, efficiency, and power consumption of the multi-bit flip-flop circuit. However, the problem is that, although more power and area efficient than multiple single flip-flop circuits, multi-bit flip-flop circuits contain a large number of transistors for data storage and scan test purposes.

[0013] As disclosed herein, an example of a multi-bit flip-flop circuit is described that includes a reduced number of transistors compared to existing multi-bit flip-flop circuit topologies. The multi-bit flip-flop circuit can include an input sub-circuit, a master latch sub-circuit, and a slave latch sub-circuit, and an output inverter, as well as other components. In some examples, the slave latch sub-circuit for each flip-flop bit in the multi-bit flip-flop circuit includes two inverters and a transmission gate, which can utilize a reduced number of transistors in the multi-bit flip-flop circuit. Additionally, each input sub-circuit from the second bit or stage of the multi-bit flip-flop circuit to the last bit of the n-bit multi-bit flip-flop circuit can include a scan transmission gate for scanning data input instead of a scan input multiplexer, which can further reduce the number of transistors in the multi-bit flip-flop circuit. In this way, the transistor count of the multi-bit flip-flop circuit can be reduced by (n - 1)*2 transistors relative to the input sub-circuit, where n is the number of bits or stages in the multi-bit flip-flop circuit. Advantageously, this topology can reduce the delay within the flip-flop circuit during scan testing, the delay within the overall digital circuit implementing logic based on the data stored by the multi-bit flip-flop circuit, the power consumption of the multi-bit flip-flop circuit, and the design cost by avoiding a large number of transistors.

[0014] In an exemplary embodiment, a circuit device is provided. The circuit device includes a first flip-flop sub-circuit coupled to receive a clock signal and an input, and a second flip-flop sub-circuit coupled to receive the clock signal and coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit coupled to receive the clock signal and the input, a first latch sub-circuit coupled to receive the clock signal and coupled to the input sub-circuit, a first latch tri-state coupled to receive the clock signal and coupled to the first latch sub-circuit, a second latch sub-circuit coupled to receive the clock signal and coupled to the first latch tri-state, and a first output inverter coupled to the first latch tri-state and the second latch sub-circuit. The second latch sub-circuit includes a first transmission gate coupled to the first latch tri-state, the first output inverter, and the second flip-flop sub-circuit, a first inverter coupled to the first transmission gate, and a second inverter coupled to the first inverter, the first latch tri-state, and the first output inverter. The second flip-flop sub-circuit includes a second transmission gate coupled to receive the clock signal and coupled to the first transmission gate of the second latch sub-circuit, a first clock tri-state coupled to receive the clock signal and coupled to the second transmission gate, a third latch sub-circuit coupled to receive the clock signal and coupled to the clock tri-state, a second latch tri-state coupled to receive the clock signal and coupled to the third latch sub-circuit, a fourth latch sub-circuit coupled to receive the clock signal and coupled to the second latch tri-state, and a second output inverter coupled to the second latch tri-state and the fourth latch sub-circuit. The fourth latch sub-circuit includes a third transmission gate coupled to the second latch tri-state and the second output inverter, a third inverter coupled to the third transmission gate, and a fourth inverter coupled to the third inverter, the second latch tri-state, and the second output inverter.

[0015] In another exemplary embodiment, a circuit device is provided. The circuit device includes a first flip-flop sub-circuit coupled to receive a clock signal and an input, and a second flip-flop sub-circuit coupled to receive the clock signal and coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit coupled to receive the clock signal and the input, a first latch sub-circuit coupled to receive the clock signal and coupled to the input sub-circuit, a first latch tri-state coupled to receive the clock signal and coupled to the first latch sub-circuit, a second latch sub-circuit coupled to receive the clock signal and coupled to the first latch tri-state, and a first output inverter coupled to the first latch tri-state and the second latch sub-circuit. The second latch sub-circuit includes a first transmission gate coupled to the first latch tri-state, the first output inverter, and the second flip-flop sub-circuit, a first inverter coupled to the first transmission gate, and a second inverter coupled to the first inverter, the first latch tri-state, and the first output inverter.

[0016] In yet another exemplary embodiment, a circuit device is provided that includes a first flip-flop sub-circuit coupled to receive a clock signal and an input, and a second flip-flop sub-circuit coupled to receive the clock signal and coupled to the first flip-flop sub-circuit. The second flip-flop sub-circuit includes a first transmission gate coupled to receive the clock signal and coupled to a first latch sub-circuit, a first transmission gate coupled to receive the clock signal and coupled to the first flip-flop sub-circuit, a first clock tri-state coupled to receive the clock signal and coupled to the first transmission gate, a first latch sub-circuit coupled to receive the clock signal and coupled to the first clock tri-state, a first latch tri-state coupled to receive the clock signal and coupled to the first latch sub-circuit, a second latch sub-circuit coupled to receive the clock signal and coupled to the first latch tri-state, and a first output inverter coupled to the first latch tri-state and the second latch sub-circuit. The second latch sub-circuit includes a second transmission gate coupled to the first latch tri-state and the first output inverter, a first inverter coupled to the second transmission gate, and a second inverter coupled to the first inverter, the first latch tri-state, and the first output inverter.

[0017] Figure 1A and 1B FIG. 1 shows an example multi-bit flip-flop circuit in accordance with an embodiment. FIG. 1 includes a multi-bit flip-flop circuit 100 that includes flip-flop circuits 110-1, 110-2, and a clock buffer 111. Flip-flop circuit 110-1 further includes an input sub-circuit 120, a master latch sub-circuit 131, a latch clock tri-state 140, a slave latch sub-circuit 145, and an output inverter 155. Flip-flop circuit 110-2 further includes an input sub-circuit 160, a master latch sub-circuit 171, a latch clock tri-state 180, a slave latch sub-circuit 185, and an output inverter 195.

[0018] The multi-bit flip-flop circuit 100 can represent a two-bit flip-flop circuit that is capable of resolving multiple bit-level signals (input functional data 107 and input functional data 108) provided by a digital circuit, for example, based on a clock signal 101 provided by the clock buffer 111. Each bit of the multi-bit flip-flop circuit 100, or flip-flop circuits 110-1 and 110-2, can be used to store the state of an input signal (e.g., "0", "1") and provide the stored state data downstream to subsequent bits of the multi-bit flip-flop circuit 100. Thus, the multi-bit flip-flop circuit 100 can be used to provide power improvements and area reduction in a digital system, as well as other benefits.

[0019] The multi-bit flip-flop circuit 100 includes flip-flop circuits 110-1, 110-2, and a clock buffer 111. The flip-flop circuit 110-1 may include a set of inputs coupled to receive an inverted clock signal 102, a clock signal 103, scan data 104, a scan enable signal 105, an inverted scan enable signal 106, and input function data 107 from the clock buffer 111. The flip-flop circuit 110-1 may include an output to provide an output 109-1 to the flip-flop circuit 110-2. The flip-flop circuit 110-2 may be coupled to receive the inverted clock signal 102, the clock signal 103, the scan data 104, the scan enable signal 105, the inverted scan enable signal 106, input function data 108, and the output 109-1 from the flip-flop circuit 110-1. The flip-flop circuit 110-2 may be coupled to provide an output 109-2 to a downstream circuit or system, such as another flip-flop circuit of the multi-bit flip-flop circuit 100. The clock buffer 111 may be coupled to receive a clock signal 101 (e.g., from a timing or clock circuit) and output the inverted clock signal 102 and the clock signal 103.

[0020] Each of the input and output signals, such as the clock signal 101, the inverted clock signal 102, the clock signal 103, the scan data 104, the scan enable signal 105, the inverted scan enable signal 106, the input function data 107, the input function data 108, the output 109-1, and the output data 109-2, may be an electronic logic signal each including a value indicating a logic low state (i.e., “0”) or a logic high state (i.e., “1”). For example, when the clock signal 101 is high, the inverted clock signal 102 may be low and the clock signal 103 may be high. Similarly, when the scan enable signal 105 is high, the inverted scan enable signal 106 may be low. The state of the scan enable signal 105 may be controlled by, for example, a controller or another circuit. When the scan enable signal 105 is high, the multi-bit flip-flop circuit 100 may enter a scan mode through which the efficiency and accuracy of the components and their nodes of the flip-flop circuits 110-1 and 110-2 may be tested. When the scan enable signal 105 is low, the multi-bit flip-flop circuit 100 may enter a data mode through which the multi-bit flip-flop circuit 100 may store the state information of the input function data 107 and the input function data 108 for use by systems and digital circuits coupled to the multi-bit flip-flop circuit 100.

[0021] The logical state of signals within the multi-bit flip-flop circuit 100 and the operation of the multi-bit flip-flop circuit 100 can be based on the logical state of the clock signal 103 provided by the clock buffer 111 to the nodes of the multi-bit flip-flop circuit 100. The clock buffer 111 includes transistors 112, 113, 114, and 115. Transistors 112 and 114 can be p-channel (or p-type) metal-oxide-semiconductor field-effect transistors (MOSFETs) (also referred to as PMOS), and transistors 113 and 115 can be n-channel (or n-type) MOSFETs (also referred to as NMOS). Each of transistors 112, 113, 114, and 115 can include a drain, a source, and a gate. The gates of transistors 112 and 113 can be coupled together and coupled to receive the clock signal 101 from a timing or clock circuit. The drains of transistors 112 and 113 can also be coupled together and coupled to the gates of transistors 114 and 115, which can be coupled to receive the inverted clock signal 102 from transistors 112 and 113. The sources of transistors 112 and 114 can be coupled to receive power from an internal power supply (e.g., V dd )), and the sources of transistors 113 and 115 can be coupled to individual nodes. The drains of transistors 114 and 115 can also be coupled together and can be coupled to provide the clock signal 103 to the nodes of the flip-flop circuits 110-1 and 110-2. In fact, transistors 112 and 113 can form the first inverter of the clock buffer 111, and transistors 114 and 115 can form the second inverter of the clock buffer 111. Thus, the inverted clock signal 102 and the clock signal 103 can be generated by the clock buffer 111 and provided to the flip-flop circuits 110-1 and 110-2.

[0022] The trigger circuit 110-1 includes various components coupled to receive a signal from the clock buffer 111 and coupled to provide an output to the trigger circuit 110-2. Specifically, the trigger circuit 110-1 includes an input sub-circuit 120, a master latch sub-circuit 131, a latch clock tri-state 140, a slave latch sub-circuit 145, and an output inverter 155. The input sub-circuit 120 may include a set of inputs coupled to receive the inverted clock signal 102 and the clock signal 103 from the clock buffer 111, the scan data 104 from a controller or another circuit, the scan enable signal 105 and the inverted scan enable signal 106, and the input function data 107 from another circuit. The input sub-circuit 120 may include an output defined by a node between the transistor 127 and the transistor 128 as described below. The master latch sub-circuit 131 may include an input coupled to the output of the input sub-circuit 120 and a set of inputs coupled to the clock buffer 111. The master latch sub-circuit 131 may include an output defined by a node between the transistor 138 and 139 as described below and coupled to the gates of the transistors 133 and 136. The latch clock tri-state 140 may include a set of inputs coupled to the output of the master latch sub-circuit 131 and a set of inputs coupled to the clock buffer 111. The latch clock tri-state 140 may include an output defined by a node between the transistor 142 and the transistor 143 as described below. The slave latch sub-circuit 145 may include a set of inputs coupled to the output of the latch clock tri-state 140 and a set of inputs coupled to the clock buffer 111. The slave latch sub-circuit 145 may include an output defined by a node between the transistor 150 and the transistor 151 as described below. A set of the inputs of the slave latch sub-circuit 145 may also be coupled to the input of the output inverter 155. The output inverter 155 may include an input coupled to the output of the latch clock tri-state 140, and may include an output defined by a node between the transistor 156 and the transistor 157 as described below.

[0023] The input sub - circuit 120 may include transistors 121, 122, 123, 124, 125, 126, 127, 128, 129, and 130, which together may form an input scan multiplexer (MUX) and an input clock tri - state. Each of the transistors in the input sub - circuit 120 may be an NMOS or a PMOS and may each include a gate, a drain, and a source. In various examples, transistors 121, 122, 123, and 124 may form the input scan multiplexer, and transistors 125, 126, 127, 128, 129, and 130 may form the input clock tri - state. The gate of each of these transistors may be coupled to receive an input signal. The gates of transistors 121 and 124 may be coupled to receive scan data 104, the gates of transistors 122 and 130 may be coupled to receive an inverted scan enable signal 106, the gates of transistors 123 and 125 may be coupled to receive a scan enable signal 105, the gate of transistor 128 may be coupled to receive an inverted clock signal 102, the gate of transistor 127 may be coupled to receive a clock signal 103, and the gates of transistors 126 and 129 may be coupled to receive input function data 107. The source of transistor 121 may be coupled to receive power from a power supply. The drain of transistor 121 may be coupled to the source of transistor 122, and the drain of transistor 122 may be coupled to the drain of transistor 126 and the source of transistor 127. The source of transistor 124 may be coupled to a ground node, the drain of transistor 124 may be coupled to the source of transistor 123, and the drain of transistor 123 may be coupled to the source of transistor 128 and the drain of transistor 129. The source of transistor 125 may also be coupled to receive power from a power supply, and the drain of transistor 125 may be coupled to the source of transistor 126. The drain of transistor 126 may be coupled to the source of transistor 127. The drain of transistor 127 may be coupled to the drain of transistor 128, and these two drains may be further coupled to the master latch sub - circuit 131. The source of transistor 128 may be coupled to the drain of transistor 129. The source of transistor 129 may be coupled to the drain of transistor 130. The source of transistor 130 may be coupled to another ground node.

[0024] The master latch sub - circuit 131 represents a first or master control flip - flop (e.g., master latch), which can control the operation of the slave latch sub - circuit 145 or a second control flip - flop (e.g., slave latch) following the first control flip - flop. The master latch sub - circuit 131 can store the state value (e.g., "0" or "1") of the input functional data 107 or the scan data 104 (based on the state of the scan enable signal 105), and provide the state value to the latch clock tri - state 140 for further distribution to the slave latch sub - circuit 145 and the output inverter 155. The master latch sub - circuit 131 can be configured to store the subsequent state value of the input functional data 107 or the scan data 104 when the state of the input functional data 107 or the scan data 104 changes to a different state relative to its stored state. After latching the new state of the data input, the master latch sub - circuit 131 can provide the new state value to the slave latch sub - circuit 145 via the latch clock tri - state 140 for storage.

[0025] In this example, the master latch sub - circuit 131 includes a feedback tri - state 132 and an inverter 137, each of which includes a certain number of NMOS and PMOS transistors. The feedback tri - state 132 includes transistors 133, 134, 135, and 136, and the inverter 137 includes transistors 138 and 139. The feedback tri - state 132 and the inverter 137 are coupled to receive signals from the input sub - circuit 120. Transistor 133 includes a source coupled to receive power from the power supply, a gate coupled to the gate of transistor 136, and a drain coupled to the source of transistor 134. Transistor 134 includes a gate coupled to receive the inverted clock signal 102 and a drain coupled to the drain of transistor 135, both the gate and the drain being further coupled to the drains of transistors 127 and 128. Transistor 125 also includes a gate coupled to receive the clock signal 103 and a source coupled to the drain of transistor 136, and transistor 136 also includes a gate coupled to the gate of transistor 133 and a source coupled to the ground node. The gates of transistors 133 and 136 are coupled to the latch clock tri - state 140 at the gates of transistors 141 and 144 of the latch clock tri - state 140. Transistors 138 and 139 each include a gate coupled to the drains of transistors 127 and 128 and coupled to the drains of transistors 134 and 135. Transistor 138 also includes a source coupled to receive power from the power supply and a drain coupled to the drain of transistor 139. The source of transistor 139 is coupled to the ground node. The drains of transistors 138 and 139 are coupled to the gates of transistors 133 and 136, and thus, also coupled to the latch clock tri - state 140.

[0026] Latch clock tri-state 140 includes transistors 141, 142, 143, and 144. Transistors 141 and 142 may be PMOS transistors, while transistors 143 and 144 may be NMOS transistors. Transistor 141 may include a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 144 and further coupled to the gate of the master latch sub-circuit 131, and a drain coupled to the source of transistor 142. Transistor 142 may also include a gate coupled to receive the inverted clock signal 102 from the clock buffer 111 and a drain coupled to the drain of transistor 143, both the gate and the drain being coupled to the slave latch sub-circuit 145 and the output inverter 155. Transistor 143 may include a gate coupled to receive the clock signal 103 from the clock buffer 111 and a source coupled to the drain of transistor 144. The source of transistor 144 may be coupled to a ground node.

[0027] The slave latch sub-circuit 145 includes an inverter 146, a transmission gate 149, and an inverter 152, each of which includes a certain number of PMOS and NMOS transistors. Inverter 146 includes transistors 147 and 148, transmission gate 149 includes transistors 150 and 151, and inverter 152 includes transistors 153 and 154. Transistor 147 includes a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 148, and a drain coupled to the drain of transistor 148. Transistor 148 also includes a source coupled to a ground node. The gates of transistors 147 and 148 are coupled to the latch clock tri-state 140, the transmission gate 149, and the output inverter 155. The drains of transistors 147 and 148 are coupled to the gates of transistors 153 and 154 of inverter 152. Transistor 150 includes a gate coupled to receive the clock signal 103 from the clock buffer 111, a drain coupled to the drain of transistor 151, and a source coupled to the source of transistor 151. Transistor 151 includes a gate coupled to receive the inverted clock signal 102 from the clock buffer 111. The drains of transistors 150 and 151 are further coupled to the latch clock tri-state 140, inverter 146, and output inverter 155. The source is further coupled to the input sub-circuit 160 of the flip-flop circuit 110-2, or more specifically, to transistors 162 and 163 of the scan transmission gate 161 of the flip-flop circuit 110-2, and is coupled to transistors 153 and 154 of inverter 152. In some instances, the drains of transistors 150 and 151 may instead be coupled to the input sub-circuit 160 of the flip-flop circuit 110-2. Transistor 153 includes a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 154, and a drain coupled to the drain of transistor 154. Transistor 154 also includes a source coupled to a ground node. The gates of transistors 153 and 154 are coupled to transistors 147 and 148 of inverter 146.

[0028] The output inverter 155 includes transistors 156 and 157, which are coupled to receive signals from the latch clock tri-state 140 and the sub-latch sub-circuit 145 and are coupled to provide an output 109-1 downstream. Transistor 156 includes a gate coupled to the gate of transistor 157, a source coupled to receive power from a power supply, and a drain coupled to the drain of transistor 157. Transistor 157 also includes a source coupled to a ground node. The output 109-1 can be provided to one or more downstream systems or circuits via the drains of transistors 156 and 157.

[0029] The flip-flop circuit 110-2 can represent the second flip-flop of the multi-bit flip-flop circuit 100, and the second flip-flop includes various components that are coupled to receive signals from the clock buffer 111 and the flip-flop circuit 110-2 and are coupled to provide an output to another flip-flop sub-circuit. The flip-flop circuit 110-2 can include an input sub-circuit 160, a master latch sub-circuit 171, a latch clock tri-state 180, a sub-latch sub-circuit 185, and an output inverter 195. The input sub-circuit 160 can include a set of inputs that are coupled to receive the inverted clock signal 102 and the clock signal 103 from the clock buffer 111, the scan data 104 from a controller or another circuit, the scan enable signal 105 and the inverted scan enable signal 106, and the input function data 108 from another circuit. The input sub-circuit 160 can include an output defined by a node between transistors 167 and 168 as described below. The master latch sub-circuit 171 can include an input coupled to the output of the input sub-circuit 160 and a set of inputs coupled to the clock buffer 111. The master latch sub-circuit 171 can include an output defined by a node between transistors 178 and 179 as described below and coupled to the gates of transistors 173 and 176. The latch clock tri-state 180 can include an input coupled to the output of the master latch sub-circuit 171 and a set of inputs coupled to the clock buffer 111. The latch clock tri-state 180 can include an output defined by a node between transistors 182 and 183 as described below. The sub-latch sub-circuit 185 can include a set of inputs coupled to the output of the latch clock tri-state 180 and a set of inputs coupled to the clock buffer 111. A set of the inputs of the sub-latch sub-circuit 185 can also be coupled to the output inverter 195. The sub-latch sub-circuit 185 can include an output defined by a node between transistors 190 and 191 as described below. The output inverter 195 can include an input coupled to the output of the latch clock tri-state 180 and can include an output defined by a node between transistors 196 and 197 as described below.

[0030] The input sub - circuit 160 may include a scan transmission gate 161 including transistors 162 and 163, and an input clock tri - state 164 including transistors 165, 166, 167, 168, 169, and 170. Each of the transistors in the input sub - circuit 160 may be an NMOS or a PMOS, and each may include a gate, a drain, and a source. The gates of transistors 162 and 170 may be coupled to receive an inverted scan enable signal 106, the gates of transistors 163 and 165 may be coupled to receive a scan enable signal 105, the gates of transistors 166 and 169 may be coupled to receive input function data 108, the gate of transistor 167 may be coupled to receive a clock signal 103, and the gate of transistor 168 may be coupled to receive an inverted clock signal 102. The source of transistor 162 may be coupled to the drain of transistor 166 and the source of transistor 167. The drain of transistor 162 may be coupled to the drain of transistor 163, and these two drains may be coupled to receive a signal having the same state as the output 109 - 1 of the transmission gate 149 from the flip - flop circuit 110 - 1. The source of transistor 163 may be coupled to the source of transistor 168 and the drain of transistor 169. The source of transistor 165 may be coupled to receive power from a power supply, and the drain of transistor 165 may be coupled to the source of transistor 166. The drain of transistor 166 may be coupled to the source of transistor 167. The drain of transistor 167 may be coupled to the drain of transistor 168. The source of transistor 168 may be coupled to the drain of transistor 169. The source of transistor 169 may be coupled to the drain of transistor 170. The source of transistor 170 may be coupled to a ground node. The input sub - circuit 160 may be coupled to the main latch sub - circuit 171 via the drains of transistors 167 and 168.

[0031] The main latch sub - circuit 171 represents a first or main control flip - flop (e.g., a master latch), which may control the operation of a secondary latch sub - circuit 185 or a second control flip - flop (e.g., a slave latch) following the first control flip - flop. The main latch sub - circuit 171 may store a state value (e.g., “0” or “1”) of the input function data 108 or the scan data 104 (based on the state of the scan enable signal 105), and provide the state value to the latch clock tri - state 180 for further distribution to the secondary latch sub - circuit 185 and the output inverter 195. The main latch sub - circuit 171 may be configured to store a subsequent state value of the input function data 108 or the scan data 104 when the state of the input function data 108 or the scan data 104 changes to a different state relative to its stored state. After latching the new state of the data input, the main latch sub - circuit 171 may provide the new state value to the secondary latch sub - circuit 185 via the latch clock tri - state 180 for storage.

[0032] In this example, the master latch sub-circuit 171 includes a feedback tri-state 172 and an inverter 177, each of which includes a certain number of NMOS and PMOS transistors. The feedback tri-state 172 includes transistors 173, 174, 175, and 176, and the inverter 177 includes transistors 178 and 179. The feedback tri-state 172 and the inverter 177 are coupled to receive signals from the input sub-circuit 120. Transistor 173 includes a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 176, and a drain coupled to the source of transistor 174. Transistor 174 includes a gate coupled to receive the inverted clock signal 102 and a drain coupled to the drain of transistor 175, both the gate and the drain being further coupled to the drains of transistors 127 and 128. Transistor 125 also includes a gate coupled to receive the clock signal 103 and a source coupled to the drain of transistor 176, and transistor 176 further includes a gate coupled to the gate of transistor 173 and a source coupled to a ground node. The gates of transistors 173 and 176 are coupled to the latch clock tri-state 180 at the gates of transistors 181 and 184 of the latch clock tri-state 180. Transistors 178 and 179 each include a gate coupled to the drains of transistors 167 and 168 and coupled to the source of transistor 174 and coupled to the drain of transistor 175. Transistor 178 also includes a source coupled to receive power from a power supply and a drain coupled to the drain of transistor 179. The source of transistor 179 is coupled to a ground node. The drains of transistors 178 and 179 are coupled to the gates of transistors 173 and 176, and thus, also coupled to the latch clock tri-state 180.

[0033] The latch clock tri-state 180 includes transistors 181, 182, 183, and 184. Transistors 181 and 182 can be PMOS transistors, while transistors 183 and 184 can be NMOS transistors. Transistor 181 can include a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 184 and further coupled to the master latch sub-circuit 171, and a drain coupled to the source of transistor 182. Transistor 182 can also include a gate coupled to receive the inverted clock signal 102 from the clock buffer 111 and a drain coupled to the drain of transistor 183, both the gate and the drain being coupled to the slave latch sub-circuit 185 and the output inverter 195. Transistor 183 can include a gate coupled to receive the clock signal 103 from the clock buffer 111 and a source coupled to the drain of transistor 184. The source of transistor 184 can be coupled to a ground node.

[0034] The secondary latch sub-circuit 185 includes inverters 186, transmission gate 189, and inverter 192, each of which includes a certain number of PMOS and NMOS transistors. Inverter 186 includes transistors 187 and 188, transmission gate 189 includes transistors 190 and 191, and inverter 192 includes transistors 193 and 194. Transistor 187 includes a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 188, and a drain coupled to the drain of transistor 188. Transistor 188 also includes a source coupled to a ground node. The gates of transistors 187 and 188 are coupled to the latch clock tri-state 180, transmission gate 189, and output inverter 195. The drains of transistors 187 and 188 are coupled to the gates of transistors 193 and 194 of inverter 192. Transistor 190 includes a gate coupled to receive clock signal 103 from clock buffer 111, a drain coupled to the drain of transistor 191, and a source coupled to the source of transistor 191. Transistor 191 includes a gate coupled to receive an inverted clock signal 102 from clock buffer 111. The drains of transistors 190 and 191 are further coupled to the latch clock tri-state 180, inverter 186, and output inverter 195. The source can be further coupled to another flip-flop circuit (e.g., another flip-flop bit of the multi-bit flip-flop circuit 100) and to transistors 193 and 194 of inverter 192. In some instances, the drains of transistors 190 and 191 can instead be coupled to the said another flip-flop circuit. Transistor 193 includes a source coupled to receive power from a power supply, a gate coupled to the gate of transistor 194, and a drain coupled to the drain of transistor 194. Transistor 194 also includes a source coupled to a ground node. The gates of transistors 193 and 194 are coupled to transistors 187 and 188 of inverter 186.

[0035] Output inverter 195 includes transistors 196 and 197 coupled to receive signals from the latch clock tri-state 180 and the secondary latch sub-circuit 185 and coupled to provide output 109-2 downstream. Transistor 196 includes a gate coupled to the gate of transistor 197, a source coupled to receive power from a power supply, and a drain coupled to the drain of transistor 197. Transistor 197 also includes a source coupled to a ground node. Output 109-2 can be provided to one or more downstream systems or circuits via the drains of transistors 196 and 197.

[0036] In various examples, relative to existing multi-bit flip-flop circuit designs, the topology of the multi-bit flip-flop circuit 100 shown and described with respect to FIG. 1 can reduce overall power consumption because a single clock buffer (clock buffer 111) can be used for both flip-flop circuits 110-1 and 110-2, a shared clock buffer and scan inverters can be used and stitched together as the unit-level area of multiple flip-flop bits, and a design area with a reduced number of transistors can be used, particularly in the sub-latch sub-circuit and the input sub-circuit.

[0037] In some examples, other types of transistors can be used in place of or in addition to the NMOS and PMOS transistors shown and described herein. In one example, the master latch sub-circuit and the slave latch sub-circuit can each individually and / or relative to each other have different topologies. For example, each latch sub-circuit can include a different number of inverters, different types of transistors, or the like.

[0038] Figure 2 An example operating environment for performing logic with a multi-bit flip-flop circuit according to an embodiment is shown. Figure 2 An operating environment 200 is shown that includes a timing circuit 205, a logic circuit 210, a multi-bit flip-flop circuit 100 that includes a flip-flop circuit 110-1 and a flip-flop circuit 110-2, and a logic circuit 225.

[0039] The logic circuit 210 represents a digital circuit, a digital logic device, or a combination or variation of electronic and logic elements capable of performing logic steps in accordance with a clock signal, such as the clock signal (e.g., clock signal 101 of FIG. 1) generated by the timing circuit 205. The logic circuit 210 can generate a data signal, a test signal, a scan signal, or another signal (e.g., scan data 104, scan enable signal 105, input functional data 107, input functional data 108) and provide one or more of the signals to the flip-flop circuits 110-1 and 110-2 of the multi-bit flip-flop circuit 100. For example, the logic circuit 210 can provide the input functional data 107 and the scan data 104 to the flip-flop circuit 110-1 and provide the input functional data 108 to the flip-flop circuit 110-2.

[0040] The multi-bit flip-flop circuit 100 can represent a two-bit flip-flop circuit capable of storing multiple bit-level signals (input function data 107 and input function data 108) provided by the logic circuit 210 based on a clock signal (via the clock signal and / or the scan clock signal) provided by the timing circuit 205 and outputting multiple bit-level signals (outputs 109-1 and 109-2). Each bit of the multi-bit flip-flop circuit 100 or the flip-flop circuits 110-1 and 110-2 can be used to store the state of the input signal (e.g., "0", "1"), and provide the stored state data downstream to the subsequent bits of the multi-bit flip-flop circuit 100 and to other digital circuits, such as the logic circuit 225. Thus, the multi-bit flip-flop circuit 100 can be used to provide power improvement and area reduction of the digital system and other benefits.

[0041] The flip-flop circuits 110-1 and 110-2 can represent the bit flip-flops of the multi-bit flip-flop circuit 100 capable of resolving and storing the logical state of the signal. Each flip-flop circuit of the multi-bit flip-flop circuit 100 can include a data path and a scan path for respectively resolving data or testing the operation of the circuit. For example, when storing data, the flip-flop circuit 110-1 can be coupled to receive the input function data 107 from the logic circuit 210 and provide the output 109-1 to the logic circuit 225, and the flip-flop circuit 110-2 can be coupled to receive the input function data 108 from the logic circuit 210 and provide the output 109-2 to the logic circuit 225. When performing a scan of the multi-bit flip-flop circuit 100, the flip-flop circuit 110-1 can be coupled to receive the scan data 104 from the logic circuit 210 and provide the scan data output 201 to the flip-flop circuit 110-2. The flip-flop circuit 110-2 can then provide the scan data output 202 to the logic circuit 225. The flip-flop circuits 110-1 and 110-2 can also be configured to receive a clock signal from the timing circuit 205 (e.g., the clock buffer of the multi-bit flip-flop circuit 100 (e.g., the clock buffer 111)). The flip-flop circuit can store the value of the electronic signal and provide an output indicating the value to the subsequent flip-flop circuit and / or the logic circuit 225. In various examples, the flip-flop circuits 110-1 and 110-2 can employ various transistors and topologies such as those described above to perform such functions.

[0042] The logic circuit 225 also represents a digital circuit, a digital logic device, or a combination or variation of electronic and logic elements capable of performing logical steps according to a clock signal, such as the clock signal generated by the timing circuit 205.

[0043] Although some of the examples provided herein are described in the context of multi-bit flip-flop circuits, sub-circuits, systems, subsystems, components, devices, architectures, or environments, it should be understood that the gates, latches, flip-flops, logic elements, and other circuits, systems, and methods described herein are not limited to these embodiments and can be applied to a variety of other processes, systems, applications, devices, and the like, such as other circuits, logic devices, latches, transistors, and the like, for example, in situations where increased transistor resolution efficiency and other benefits are achieved. Accordingly, aspects of the present invention can be embodied in other systems, methods, and other configurable systems.

[0044] Unless the context clearly requires otherwise, throughout the description and claims, the words "comprising," "including," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, as "including but not limited to." As used herein, the term "connected," "coupled," or any variation thereof means any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical, or a combination thereof. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to the application as a whole and not to any particular part of the application. Where the context permits, the singular or plural words used in the above detailed description may also respectively include the plural or singular. The word "or" in reference to a list of two or more items covers all of the following interpretations of the listed items: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0045] The phrases "in some embodiments," "according to some embodiments," "in the illustrated embodiments," "in other embodiments," and the like generally mean that the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the technology of the present invention and may be included in more than one embodiment. Additionally, such phrases do not necessarily refer to the same embodiment or different embodiments.

[0046] The above-described specific embodiments of the examples of the technology are not intended to be exhaustive or to limit the technology to the exact forms disclosed above. While specific examples of the technology are described above for illustrative purposes, various equivalent modifications can be made within the scope of the technology, as will be recognized by those skilled in the relevant art. For example, although a process or blocks are presented in a given order, alternative embodiments can execute routines with steps or employ systems with blocks in a different order, and some processes or blocks can be deleted, moved, added, subdivided, combined, and / or modified to provide alternative or sub-combinations. Each of these processes or blocks can be implemented in a variety of different ways. Additionally, while processes or blocks are sometimes shown as being executed serially, these processes or blocks can instead be executed or implemented in parallel, or can be executed at different times. Further, any specific numbers mentioned herein are merely examples; alternative embodiments can employ different values or ranges.

[0047] The teachings of the technology provided herein can be applied to other systems, not necessarily the systems described above. The elements and acts of the various examples described above can be combined to provide additional embodiments of the technology. Some alternative embodiments of the technology can include not only additional elements of those embodiments mentioned above, but also fewer elements.

[0048] In view of the foregoing detailed description, these and other changes can be made to the technology. While the above description describes certain examples of the technology and describes the best mode contemplated, no matter how detailed the above appears in this document, the technology can be practiced in many ways. The details of the system can vary considerably in its specific implementation while still being covered by the technology disclosed herein. As noted above, the specific terms used when describing certain features or aspects of the technology should not be construed to imply that the term is redefined herein to be limited to any specific property, feature, or aspect of the technology associated with that term. In general, unless the specific embodiments section above clearly defines such terms, the terms used in the appended claims should not be construed to limit the technology to the specific examples disclosed in the specification. Thus, the actual scope of the technology not only covers the disclosed examples, but also includes all equivalent ways of practicing or implementing the technology under the claims.

[0049] To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates the aspects of the technology in any number of claim forms. For example, while only one aspect of the technology is recited as a computer-readable medium claim, other aspects may equally be embodied as a computer-readable medium claim or in other forms, such as in means-plus-function claims. Any claim intended to be treated under 35 U.S.C. § 112(f) will begin with the words "means for", but the use of the term "for" in any other context is not intended to invoke treatment under 35 U.S.C. § 112(f). Accordingly, the applicant reserves the right to seek additional claims after the filing of this application in the form of such additional claims in this application or in a continuing application.

Claims

1. A circuit device, comprising: A first flip-flop sub-circuit, which is coupled to receive a clock signal and an input; And A second flip-flop sub-circuit, which is coupled to receive the clock signal and is coupled to the first flip-flop sub-circuit; Wherein the first flip-flop sub-circuit includes: An input sub-circuit, which is coupled to receive the clock signal and the input; A first latch sub-circuit, which is coupled to receive the clock signal and is coupled to the input sub-circuit; A first latch tri-state, which is coupled to receive the clock signal and is coupled to the first latch sub-circuit; A second latch sub-circuit, which is coupled to receive the clock signal and is coupled to the first latch tri-state; and A first output inverter, which is coupled to the first latch tri-state and is coupled to the second latch sub-circuit; Wherein the second latch sub-circuit includes: A first transmission gate, which is coupled to the first latch tri-state, the first output inverter, and the second flip-flop sub-circuit; A first inverter, which is coupled to the first transmission gate; and A second inverter, which is coupled to the first inverter, the first latch tri-state, and the first output inverter; and Wherein the second flip-flop sub-circuit includes: A second transmission gate, which is coupled to the first transmission gate of the second latch sub-circuit; A first clock tri-state, which is coupled to receive the clock signal and is coupled to the second transmission gate; A third latch sub-circuit, which is coupled to receive the clock signal and is coupled to the first clock tri-state; A second latch tri-state, which is coupled to receive the clock signal and is coupled to the third latch sub-circuit; A fourth latch sub-circuit, which is coupled to receive the clock signal and is coupled to the second latch tri-state; and A second output inverter, which is coupled to the second latch tri-state and is coupled to the fourth latch sub-circuit; Wherein the fourth latch sub-circuit includes: A third transmission gate, which is coupled to the second latch tri-state and the second output inverter; A third inverter, which is coupled to the third transmission gate; and A fourth inverter, which is coupled to the third inverter, the second latch tri-state, and the second output inverter.

2. The circuit device according to claim 1, wherein the first flip-flop sub-circuit is the first flip-flop in a multi-bit flip-flop circuit, and wherein the second flip-flop sub-circuit is the second flip-flop in a multi-bit flip-flop circuit.

3. The circuit device according to claim 2, wherein the multi-bit flip-flop circuit includes multiple bits.

4. The circuit device according to claim 1, wherein the input sub-circuit of the first flip-flop sub-circuit includes an input scan multiplexer and a second clock tri-state, wherein the input scan multiplexer is coupled to receive the input, and wherein the second clock tri-state is coupled to the input scan multiplexer and is coupled to receive the clock signal.

5. The circuit device according to claim 1, wherein the first latch sub - circuit includes a first feedback tri - state and a fifth inverter, wherein the first feedback tri - state is coupled to receive the clock signal and is coupled to the input sub - circuit, and wherein the fifth inverter is coupled to the input sub - circuit.

6. The circuit device according to claim 1, wherein the third latch sub - circuit includes a second feedback tri - state and a sixth inverter, wherein the second feedback tri - state is coupled to receive the clock signal and is coupled to the first clock tri - state, and wherein the sixth inverter is coupled to the first clock tri - state.

7. The circuit device according to claim 1, wherein the first flip - flop sub - circuit and the second flip - flop sub - circuit include a plurality of n - type transistors and a plurality of p - type transistors.

8. A circuit device, comprising: A first flip - flop sub - circuit, which is coupled to receive a clock signal and an input; And A second flip - flop sub - circuit, which is coupled to receive the clock signal and is coupled to the first flip - flop sub - circuit; Wherein the first flip - flop sub - circuit includes: An input sub - circuit, which is coupled to receive the clock signal and the input; A first latch sub - circuit, which is coupled to receive the clock signal and is coupled to the input sub - circuit; A first latch tri - state, which is coupled to receive the clock signal and is coupled to the first latch sub - circuit; A second latch sub - circuit, which is coupled to receive the clock signal and is coupled to the first latch tri - state; and A first output inverter, which is coupled to the first latch tri - state and is coupled to the second latch sub - circuit; Wherein the second latch sub - circuit includes: A first transmission gate, which is coupled to the first latch tri - state, the first output inverter and the second flip - flop sub - circuit; A first inverter, which is coupled to the first transmission gate; and A second inverter, which is coupled to the first inverter, the first latch tri - state and the first output inverter.

9. The circuit device according to claim 8, wherein the second flip - flop sub - circuit includes: A second transmission gate, which is coupled to the first transmission gate of the second latch sub - circuit; A first clock tri - state, which is coupled to receive the clock signal and is coupled to the second transmission gate; A third latch sub - circuit, which is coupled to receive the clock signal and is coupled to the second transmission gate; A second latch tri - state, which is coupled to receive the clock signal and is coupled to the third latch sub - circuit; A fourth latch sub - circuit, which is coupled to receive the clock signal and is coupled to the second latch tri - state; And A second output inverter, which is coupled to the second latch tri - state and is coupled to the fourth latch sub - circuit; Wherein the fourth latch sub - circuit includes: A third transmission gate, which is coupled to the second latch tri - state and the second output inverter; A third inverter, which is coupled to the third transmission gate; And A fourth inverter, which is coupled to the third inverter, the second latch tri - state and the second output inverter.

10. The circuit device according to claim 9, wherein the first flip-flop sub-circuit is the first flip-flop in a multi-bit flip-flop circuit, and wherein the second flip-flop sub-circuit is the second flip-flop in the multi-bit flip-flop circuit.

11. The circuit device according to claim 10, wherein the multi-bit flip-flop circuit includes a plurality of bits.

12. The circuit device according to claim 8, wherein the input sub-circuit of the first flip-flop sub-circuit includes an input scan multiplexer and a clock tri-state, wherein the input scan multiplexer is coupled to receive the input, and wherein the clock tri-state is coupled to the input scan multiplexer and is coupled to receive the clock signal.

13. The circuit device according to claim 8, wherein the first latch sub-circuit includes a first feedback tri-state and a fifth inverter, wherein the first feedback tri-state is coupled to receive the clock signal and is coupled to the input sub-circuit, and wherein the fifth inverter is coupled to the input sub-circuit.

14. The circuit device according to claim 9, wherein the third latch sub-circuit includes a second feedback tri-state and a sixth inverter, wherein the second feedback tri-state is coupled to receive the clock signal and is coupled to the first clock tri-state, and wherein the sixth inverter is coupled to the first clock tri-state.

15. The circuit device according to claim 9, wherein the first flip-flop sub-circuit and the second flip-flop sub-circuit include a plurality of n-type transistors and a plurality of p-type transistors.

16. A circuit device, comprising: a first flip-flop sub-circuit, which is coupled to receive a clock signal and an input; and a second flip-flop sub-circuit, which is coupled to receive the clock signal and is coupled to the first flip-flop sub-circuit; wherein the second flip-flop sub-circuit includes: a first transmission gate, which is coupled to the first flip-flop sub-circuit; a first clock tri-state, which is coupled to receive the clock signal and is coupled to the first transmission gate; a first latch sub-circuit, which is coupled to receive the clock signal and is coupled to the first clock tri-state; a first latch tri-state, which is coupled to receive the clock signal and is coupled to the first latch sub-circuit; a second latch sub-circuit, which is coupled to receive the clock signal and is coupled to the first latch tri-state; and a first output inverter, which is coupled to the first latch tri-state and is coupled to the second latch sub-circuit; wherein the second latch sub-circuit includes: a second transmission gate, which is coupled to the first latch tri-state and the first output inverter; a first inverter, which is coupled to the second transmission gate; and a second inverter, which is coupled to the first inverter, the first latch tri-state, and the first output inverter.

17. The circuit device according to claim 16, wherein the first flip-flop sub-circuit includes: an input sub-circuit, which is coupled to receive the clock signal and the input; a third latch sub-circuit, which is coupled to receive the clock signal and is coupled to the input sub-circuit; A second latch tri-state, which is coupled to receive the clock signal and is coupled to the third latch sub-circuit; A fourth latch sub-circuit, which is coupled to receive the clock signal and is coupled to the second latch tri-state; And A second output inverter, which is coupled to the second latch tri-state and is coupled to the fourth latch sub-circuit; Wherein the fourth latch sub-circuit includes: A third transmission gate, which is coupled to the second latch tri-state, the second output inverter and the second flip-flop sub-circuit; A third inverter, which is coupled to the third transmission gate; And A fourth inverter, which is coupled to the third inverter, the second latch tri-state and the second output inverter.

18. The circuit device according to claim 17, wherein the first flip-flop sub-circuit is the first flip-flop in a multi-bit flip-flop circuit, and wherein the second flip-flop sub-circuit is the second flip-flop in a multi-bit flip-flop circuit.

19. The circuit device according to claim 17, wherein the input sub-circuit of the first flip-flop sub-circuit includes an input scan multiplexer and a second clock tri-state, wherein the input scan multiplexer is coupled to receive the input, and wherein the second clock tri-state is coupled to the input scan multiplexer and is coupled to receive the clock signal.

20. The circuit device according to claim 19, wherein: The first latch sub-circuit includes a first feedback tri-state coupled to receive the clock signal and coupled to the input sub-circuit and a fifth inverter coupled to the input sub-circuit; And The third latch sub-circuit includes a second feedback tri-state coupled to receive the clock signal and coupled to the second clock tri-state and a sixth inverter coupled to the second clock tri-state.

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