Clock data recovery circuit

Abstract

A clock data recovery circuit includes a phase detector circuit, a proportional path, an integration path, and an oscillator circuit. The phase detector circuit is used for receiving input data and detecting the input data according to an oscillation signal to output a detection result. The proportional path is used for outputting a proportional control signal according to the detection result. The proportional path includes a charge pump circuit and a variable capacitance element. The charge pump circuit generates a voltage control signal according to the detection result. The variable capacitance element generates a proportional control signal according to the voltage control signal. The integration path is used for outputting an integration control signal according to the detection result. The oscillator circuit is coupled to the proportional path and the integral path. The oscillator circuit is used for generating an oscillation signal according to the proportional control signal and the integral control signal.

Description

Technical Field

[0001] The present disclosure relates to a clock data recovery circuit, and more particularly to a clock data recovery circuit based on a phase-locked loop architecture. Background Art

[0002] For high-speed serial buses, generally, the information of the clock signal is embedded into the data stream to be transmitted through data encoding. Then, at the receiving end, the clock information is obtained through clock recovery, and the input data is sampled using the recovered clock signal. The purpose of clock recovery is to track the clock offset at the transmitting end to ensure correct data sampling. A clock data recovery (CDR) circuit can be implemented based on a phase-locked loops (PLL) architecture. However, in the current architecture of the clock data recovery circuit, the gain of the proportional path may be reduced due to the influence of parasitic capacitance, resulting in the clock data recovery circuit being unable to correctly sample the data. Summary of the Invention

[0003] The present disclosure provides a clock data recovery circuit that can improve the correctness of data sampling.

[0004] The clock data recovery circuit according to an embodiment of the present disclosure includes a phase detector circuit, a proportional path, an integral path, and an oscillator circuit. The phase detector circuit is configured to receive input data and detect the input data according to the oscillation signal to output a detection result. The proportional path is configured to output a proportional control signal according to the detection result. The proportional path includes a charge pump circuit and a variable capacitance element. The charge pump circuit generates a voltage control signal according to the detection result. The variable capacitance element generates a proportional control signal according to the voltage control signal. The integral path is configured to output an integral control signal according to the detection result. The oscillator circuit is coupled to the proportional path and the integral path. The oscillator circuit is configured to generate an oscillation signal according to the proportional control signal and the integral control signal.

[0005] To more easily understand the features and advantages of the present disclosure, the following specific embodiments are described in detail with reference to the accompanying drawings. Brief Description of the Drawings

[0006] Figure 1 A block diagram showing the clock data recovery circuit according to an embodiment of the present disclosure.

[0007] Figure 2 A circuit diagram showing the clock data recovery circuit according to another embodiment of the present disclosure.

[0008] Figure 3 Showing Figure 2 A circuit diagram of the proportional path and the oscillator circuit according to an embodiment.

[0009] Figure 4A Shows Figure 3 A schematic circuit diagram when the switch circuit of the embodiment is in the first conduction state.

[0010] Figure 4B Shows Figure 3 A schematic circuit diagram when the switch circuit of the embodiment is in the second conduction state.

[0011] Figure 5A A schematic diagram showing the variation of the capacitance value of the variable capacitance element and the voltage value of the voltage control signal according to an embodiment of the present disclosure.

[0012] Figure 5B A schematic diagram showing the variation of the frequency value of the oscillation signal and the voltage value of the voltage control signal according to an embodiment of the present disclosure.

[0013] Figure 6A A schematic diagram showing the variation of the capacitance value of the variable capacitance element and the voltage value of the voltage control signal according to another embodiment of the present disclosure.

[0014] Figure 6B A schematic diagram showing the variation of the frequency value of the oscillation signal and the voltage value of the voltage control signal according to another embodiment of the present disclosure. Detailed implementation manners

[0015] As used in the specification (including the claims) of the present disclosure, the term "coupling (or connection)" may refer to any direct connection means or indirect connection means. For example, if a first device is described as being coupled (or connected) to a second device, it should be construed that the first device can be directly connected to the second device or the first device can be indirectly connected to the second device via another device or a specific connection means. Throughout the specification (including the claims) of the present disclosure, terms such as "first" and "second" are used to name elements or distinguish different embodiments or scopes, rather than to limit the upper or lower limits of the number of elements or to limit the order of the elements. Additionally, elements / components / steps and embodiments using the same reference numerals in the drawings as much as possible represent the same or similar parts. The related descriptions of elements / components / steps using the same reference numerals or the same terms in different embodiments can be cross-referenced.

[0016] Figure 1 Shows a block schematic diagram of a clock data recovery circuit according to an embodiment of the present disclosure. Please refer to Figure 1 , the clock data recovery circuit 100 includes a phase detector circuit 110, a proportional path 120, an integration path 130, and an oscillator circuit 140. The oscillator circuit 140 is coupled to the proportional path 130 and the integration path 140.

[0017] The oscillator circuit 140 is used to generate an oscillation signal S3 according to the proportional control signal S1 and the integral control signal S2. The phase detector circuit 110 is used to receive the input data Din and detect the input data Din according to the oscillation signal S3 to output a detection result S4. The detection operation of the phase detector circuit 110 includes operations such as sampling and phase detection of the input data Din, for example.

[0018] The proportional path 120 is used to output the proportional control signal S1 according to the detection result S4. The proportional path 120 includes a charge pump circuit 122 and a variable capacitance element 124. The charge pump circuit 122 can generate a voltage control signal Vpctrl according to the detection result S4. The voltage control signal Vctrl can be used to adjust the capacitance value of the variable capacitance element 124 to prevent the gain of the proportional path 120 from being reduced due to the influence of parasitic capacitance. The integral path 130 is used to output the integral control signal S2 according to the detection result S4.

[0019] Figure 2 A circuit schematic diagram of a clock data recovery circuit showing another embodiment of the present disclosure. Please refer to Figure 2 In this embodiment, the phase detector circuit 210 includes a sampling circuit 212 and a phase detector 214. The sampling circuit 212 samples the input data Din according to the oscillation signal S3. Then, the phase detector 214 performs phase detection on the sampling result according to the oscillation signal S3 to output a detection result S4. In the embodiment, the phase detector 214 is, for example, a bang-bang phase detector.

[0020] The proportional path 220 includes a charge pump circuit 222 and a variable capacitance element 224. The charge pump circuit 222 includes a switch circuit 310 and a voltage dividing circuit 320. The voltage dividing circuit 320 is used to divide the difference between the first voltage VDD and the second voltage GND. It can generate a voltage control signal Vpctrl with different voltage values according to the conduction state of the switch circuit 310. The capacitance value of the variable capacitance element 224, which is used as the proportional control signal S1, will change according to the voltage value of the voltage control signal Vpctrl. The detection result S4 output by the phase detector circuit 210 includes a first switch control signal UP and a second switch control signal DN. The first switch control signal UP and the second switch control signal DN are output to the switch circuit 310 to control the conduction states of the first switch element SW1 and the second switch element SW2, respectively.

[0021] The integration path 230 includes a demultiplexer 232, a decoder 234, an accumulator 236, and a modulator 238. The detection result S4 output by the phase detector circuit 210 includes clock information and data information. The demultiplexer 232 decelerates the output signal of the phase detector circuit 210 into multiple signals, and then the decoder 234 performs decoding. After the output signal of the decoder 234 passes through the accumulator 236, the modulator 238 is used to [improve] the resolution of the signal. In an embodiment, the modulator 238 is, for example, a delta-sigma modulator.

[0022] The oscillator circuit 240 includes a current source 242, an oscillator 244, and a variable capacitance element 242. The integration control signal S2 of the integration path 230 can be output to the digital circuit 250. The digital circuit 250 adjusts the current provided by the current source 242 to the oscillator 244 according to the integration control signal S2, so as to achieve the frequency tracking and locking of the input data Din.

[0023] In an embodiment, the digital circuit 250 can be implemented as a logic circuit on an integrated circuit. For example, the related functions of the digital circuit 250 can be implemented by the following hardware: one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), or various logic blocks, modules, and circuits in other processing units. The related functions of the digital circuit 250 can be implemented as hardware circuits such as various logic blocks, modules, and circuits in an integrated circuit by using a hardware description language (HDL) (for example, Verilog HDL or VHSIC hardware description language (VHDL)) or other suitable programming languages.

[0024] The detailed operations and circuit structures of the scaling path 220 and the oscillator circuit 240 can be further referred to Figure 3 . Figure 3 shown Figure 2 in the circuit schematic diagrams of the scaling path and the oscillator circuit of the embodiment. Please refer to Figure 2 and Figure 3 Note: There seems to be a word missing in the translation of the first paragraph where it says "the modulator 238 is used to [improve] the resolution of the signal" as the original text is not clear about what exactly the modulator does to the signal resolution. I've added "improve" in square brackets for the sake of a more complete translation., in this embodiment, the oscillator 244 is, for example, a four stage feedforward ring oscillator circuit. The structure of the oscillator 244 is not used to limit the present disclosure.

[0025] The switching circuit 222 includes a first switching element SW1 and a second switching element SW2. The first switching element SW1 has a first end, a second end, and a control end. The first end of the first switching element SW1 is coupled to the first voltage VDD. The second end of the first switching element SW1 is coupled to the first end of the second switching element SW2. The control end of the first switching element SW1 is coupled to the first switching control signal DN. The first switching control signal DN is used to control the on-state of the first switching element SW1. The second switching element SW2 has a first end, a second end, and a control end. The first end of the second switching element SW2 is coupled to the second end of the first switching element SW1. The second end of the second switching element SW2 is coupled to the second voltage GND. The control end of the second switching element SW2 is coupled to the second switching control signal UP. Wherein, the first voltage VDD is greater than the second voltage GND.

[0026] The voltage dividing circuit 320 includes a first resistor element R1, a second resistor element R2, and a third resistor element R3. In an embodiment, the resistance value of the third resistor element R3 can be designed to be greater than or equal to the resistance values of the first resistor element R1 and the second resistor element R2, and the resistance value of the first resistor element R1 can be designed to be equal to the resistance value of the second resistor element R2. For example, when the resistance value of the first resistor element R1 is equal to the resistance value of the second resistor element R2, the resistance value of the third resistor element R3 can be K times the resistance value of the first resistor element R1 or the second resistor element R2, where K is an integer greater than or equal to 1.

[0027] Specifically, the first resistor element R1 has a first end and a second end. The first end of the first resistor element R1 is coupled to the first voltage VDD. The second end (node A) of the first resistor element R1 is coupled to the first end of the second resistor element R2. The second resistor element R2 has a first end and a second end. The first end of the second resistor element R2 is coupled to the second end of the first resistor element R1. The second end of the second resistor element R2 is coupled to the second voltage GND. The third resistor element R3 has a first end and a second end. The first end of the third resistor element R3 is coupled to the second end of the first switching element SW1 or the first end of the second switching element SW2. The second end of the third resistor is coupled to the second end of the first resistor element R1 or the first end of the second resistor element R2.

[0028] The voltage dividing circuit 320 is used to divide the difference between the first voltage VDD and the second voltage GND, and generate a voltage control signal Vpctrl at node A. In this embodiment, the voltage dividing circuit 320 can generate voltage control signals Vpctrl with different voltage values according to the conduction state of the switching circuit 310. The voltage control signal Vpctrl is output to the variable capacitance element 224 to adjust the capacitance value of the variable capacitance element 224.

[0029] Figure 4A Show Figure 3 A schematic circuit diagram when the switching circuit of the embodiment is in the first conduction state. Figure 4B Show Figure 3 A schematic circuit diagram when the switching circuit of the embodiment is in the second conduction state. Please refer to Figures 3 to 4B , in Figure 4A , the switching circuit 310 is in the first conduction state, that is, the first switching element SW1 is conducting while the second switching element SW2 is not conducting. When the switching circuit 310 is in the first conduction state, the voltage dividing circuit 310 provides a voltage control signal Vpctrl with a first voltage value V1. Wherein, assuming that the resistance value of the first resistance element R1 is equal to the resistance value of the second resistance element R2, and the resistance value of the third resistance element R3 is K times the resistance value of the first resistance element R1 or the second resistance element R2, the first voltage value V1 can be calculated as:

[0030]

[0031] Wherein, VDD is the voltage value of the first voltage. In addition, the first voltage variable K CP , DN is defined as the first voltage value V1 minus one-half of VDD. Therefore, the first voltage variable K CP，DN at node A can be calculated as:

[0032]

[0033] On the other hand, in Figure 4B , the switching circuit 310 is in the second conduction state, that is, the first switching element SW1 is not conducting while the second switching element SW2 is conducting. When the switching circuit 310 is in the second conduction state, the voltage dividing circuit 310 provides a voltage control signal Vpctrl with a second voltage value V2. The second voltage value V2 is less than the first voltage value V1. Wherein, also assuming that the resistance value of the first resistance element R1 is equal to the resistance value of the second resistance element R2, and the resistance value of the third resistance element R3 is K times the resistance value of the first resistance element R1 or the second resistance element R2, the second voltage value V2 can be calculated as:

[0034]

[0035] In addition, the second voltage variable KCP, UP of node A is defined as the second voltage value V2 minus half of VDD. Therefore, the second voltage variable K of node A CP，UP can be calculated as:

[0036]

[0037] Therefore, the voltage dividing circuit 320 can generate voltage control signals Vpctrl with different voltage values V1 and V2 according to the conduction state of the switch circuit 310 to adjust the capacitance value of the variable capacitance element 224.

[0038] Next, the variable capacitance element 224 will be described. Please go back to Figure 3 . In Figure 3 , the variable capacitance element 224 includes a plurality of capacitors C1, which are connected in parallel between the charge pump circuit 222 and the oscillator 244.

[0039] Specifically, in this embodiment, the capacitor C1 is, for example, a PCAP variable capacitor. The PCAP variable capacitor is a variable capacitor with a MOS transistor structure, and its working principle depends on the parasitic capacitance in the MOS transistor structure. The structure of the PCAP variable capacitor is, for example, a modification of the general MOS transistor structure to enhance the parasitic capacitance. By applying a voltage to the PCAP variable capacitor, its capacitance value can be changed. Therefore, by applying a voltage control signal Vpctrl to one end of the capacitor C1, its voltage value can adjust the capacitance value of the capacitor C1.

[0040] Figure 5A The schematic diagram showing the change of the capacitance value of the variable capacitance element according to the embodiment of the present disclosure with respect to the voltage value of the voltage control signal is shown. Figure 5B The schematic diagram showing the change of the frequency value of the oscillation signal according to the embodiment of the present disclosure with respect to the voltage value of the voltage control signal is shown. Please refer to Figure 5A and Figure 5B . In Figure 5A , the abscissa is the voltage value of the voltage control signal Vpctrl, and the ordinate is the equivalent capacitance value Cpcap of the variable capacitance element 224; in Figure 5B , the abscissa is the voltage value of the voltage control signal Vpctrl, and the ordinate is the frequency value f of the oscillation signal S3.

[0041] Taking the capacitor C1 as a PCAP variable capacitor as an example, the change of the equivalent capacitance value Cpcap of the variable capacitance element 224 with respect to the voltage value of the voltage control signal is in a linear relationship, for example, proportional, that is, the larger the voltage value, the larger the capacitance value Cpcap, as shown in Figure 5A .

[0042] On the other hand, since the frequency of the oscillation signal S3 generated by the oscillator circuit 244 is proportional to the reciprocal of the resistance-capacitance value (the product of the resistance value and the capacitance value) of the entire circuit, the change in the frequency value f of the oscillation signal S3 with respect to the voltage value of the voltage control signal Vpctrl is also linear, for example, inversely proportional, that is, the larger the voltage value, the smaller the frequency value f, as Figure 5B shown.

[0043] In Figure 3 the embodiment, the capacitor C1 is taken as an example of a PCAP variable capacitor, but the present disclosure is not limited thereto. In the embodiment, the capacitor C1 can also be implemented with an NCAP variable capacitor.

[0044] Figure 6A Schematic diagram showing the change of the capacitance value of the variable capacitance element in another embodiment of the present disclosure with respect to the voltage value of the voltage control signal. Figure 6B Schematic diagram showing the change of the frequency value of the oscillation signal in another embodiment of the present disclosure with respect to the voltage value of the voltage control signal. Please refer to Figure 6A and Figure 6B In Figure 6A , the abscissa is the voltage value of the voltage control signal Vpctrl, and the ordinate is the equivalent capacitance value Cncap of the variable capacitance element 224 implemented with an NCAP variable capacitor; in Figure 5B , the abscissa is the voltage value of the voltage control signal Vpctrl, and the ordinate is the frequency value f of the oscillation signal S3. [[ID=II]]

[0045] Taking the capacitor C1 as an example of an NCAP variable capacitor, the change in the equivalent capacitance value Cncap of the variable capacitance element 224 with respect to the voltage value of the voltage control signal Vpctrl is also linear, for example, inversely proportional, that is, the larger the voltage value, the smaller the capacitance value Cncap, as Figure 6A shown.

[0046] Similarly, since the frequency of the oscillation signal S3 generated by the oscillator circuit 244 is proportional to the reciprocal of the resistance-capacitance value of the entire circuit, the change in the frequency value f of the oscillation signal S3 with respect to the voltage value of the voltage control signal Vpctrl is also linear, for example, directly proportional, that is, the larger the voltage value, the larger the frequency value f, as Figure 6B shown.

[0047] In summary, in the embodiments of the present disclosure, the scaling path includes a charge pump circuit and a variable capacitance element. The charge pump circuit generates a voltage control signal according to the detection result of the phase detector circuit to adjust the capacitance value of the variable capacitance element, thereby adjusting the frequency of the oscillation signal. In this way, the influence of parasitic capacitance on the gain of the scaling path can be reduced to improve the correctness of data sampling of the clock data recovery circuit. In addition, the charge pump circuit in the embodiments of the present disclosure is a voltage-mode charge pump, which has a simple structure and can reduce the chip area it occupies.

[0048] Although the present disclosure has been disclosed in the embodiments, the embodiments are not intended to limit the present disclosure. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be defined by the appended claims.

Claims

1. A clock data recovery circuit, comprising: A phase detector circuit for receiving input data and detecting the input data according to an oscillation signal to output a detection result; A proportional path for outputting a proportional control signal according to the detection result, wherein the proportional path includes a charge pump circuit and a variable capacitance element, the charge pump circuit generates a voltage control signal according to the detection result, and the variable capacitance element generates a proportional control signal according to the voltage control signal; An integration path for outputting an integration control signal according to the detection result; And An oscillator circuit coupled to the proportional path and the integration path and for generating an oscillation signal according to the proportional control signal and the integration control signal.

2. The clock data recovery circuit according to claim 1, wherein the charge pump circuit includes a switching circuit and a voltage dividing circuit, and the voltage dividing circuit generates the voltage control signal with different voltage values according to the conduction state of the switching circuit.

3. The clock data recovery circuit according to claim 2, wherein the switching circuit has a first conduction state and a second conduction state, and When the switching circuit is in the first conduction state, the voltage dividing circuit provides the voltage control signal with a first voltage value, and when the switching circuit is in the second conduction state, the voltage dividing circuit provides the voltage control signal with a second voltage value, wherein the second voltage value is less than the first voltage value.

4. The clock data recovery circuit according to claim 3, wherein the switching circuit includes: A first switching element having a first end, a second end and a control end, wherein the first end of the first switching element is coupled to a first voltage, and the control end of the first switching element is coupled to a first switching control signal; And A second switching element having a first end, a second end and a control end, wherein the first end of the second switching element is coupled to the second end of the first switching element, the second end of the second switching element is coupled to a second voltage, and the control end of the second switching element is coupled to a second switching control signal, wherein the first voltage is greater than the second voltage.

5. The clock data recovery circuit according to claim 4, wherein the detection result includes the first switching control signal and the second switching control signal, respectively used to control the conduction states of the first switching element and the second switching element.

6. The clock data recovery circuit according to claim 4, wherein the voltage dividing circuit includes: A first resistor element having a first end and a second end, wherein the first end of the first resistor element is coupled to the first voltage; A second resistor element having a first end and a second end, wherein the first end of the second resistor element is coupled to the second end of the first resistor element, and the second end of the second resistor element is coupled to the second voltage; And A third resistor element having a first end and a second end, wherein the first end of the third resistor element is coupled to the second end of the first switching element, and the second end of the third resistor element is coupled to the second end of the first resistor element.

7. The clock data recovery circuit according to claim 6, wherein a resistance value of the third resistor element is greater than or equal to resistance values of the first resistor element and the second resistor element, and the resistance value of the first resistor element is equal to the resistance value of the second resistor element.

8. The clock data recovery circuit according to claim 1, wherein the variable capacitance element includes a plurality of capacitors connected in parallel between the charge pump circuit and the oscillator circuit.

9. The clock data recovery circuit according to claim 1, wherein a capacitance value of the variable capacitance element is changed according to a voltage value of the voltage control signal.

10. The clock data recovery circuit according to claim 9, wherein the capacitance value of the variable capacitance element has a linear relationship with respect to a change in the voltage value of the voltage control signal.

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