Process method for improving single particle resistance of trench type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention discloses a process method for improving single particle resistance of a trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which is characterized in that on the basis of a trench-type MOSFET process, the radiation resistance of a device product is improved through design and process optimization, so that the device product is adapted to a space environment of ionizing radiation in space, and the high reliability index of the device product is improved. According to the invention, an oxide layer SPACER side wall is formed at the source electrode by utilizing the polycrystalline height of the trench gate, high-energy large-dose ion implantation is realized at the extraction position of the body region, the resistance of the base region is reduced, and the single-particle burning resistance of the device is improved. Through the design and process technology, the adjustable SPACER self-alignment injection of the injection body region is realized, the single particle burnout resistance of the device is reinforced, the influence on the channel is reduced, the requirements of the anti-radiation performance index and the static parameter stability of the MOSFET device are met, and the MOSFET device is enabled to adapt to the environmental requirements of the aerospace field.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and particularly to a process method for improving the single-event immunity of trench MOSFETs. Background Art

[0002] Trench MOSFET is a new type of discrete power MOSFET power device. Compared with bipolar power devices, it has the advantages of low conduction loss, high operating frequency, voltage-controlled device, and simple control circuit, and is increasingly valued by the industrial community.

[0003] Compared with planar MOSFET, trench MOSFET can achieve smaller cell size and higher current density, improve the current capacity and switching performance of the device, and has more obvious advantages especially in the field of medium and low voltage power MOSFETs.

[0004] With the exploration of the space field by humans, electronic components not only need excellent electrical performance but also need to cope with the harsh environment in space, such as gamma rays, solar wind, etc. In the space ionization radiation environment, the radiation effects generated by the device mainly include total dose radiation effect, single-event burnout, and single-event gate rupture. Therefore, radiation hardening design is required for the device. Summary of the Invention

[0005] The purpose of the present invention is to provide a process method for improving the single-event immunity of trench MOSFETs to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a process method for improving the single-event immunity of trench MOSFETs, including:

[0007] Growing a first silicon oxide layer on a silicon epitaxial wafer and implementing P-well implantation, and performing a high-temperature drive-in process on the P-type well implantation;

[0008] Then depositing a second silicon dioxide layer and a first silicon nitride layer to form a three-layer thin film structure of thermal silicon oxide - deposited silicon dioxide - deposited silicon nitride, and digging a trench groove on the wafer;

[0009] Filling the trench groove with a third silicon dioxide, and then grinding to remove the excess third silicon dioxide on the surface; rinsing the third silicon dioxide filled in the trench groove, and retaining a part of the third silicon dioxide at the bottom of the trench groove;

[0010] Growing a gate oxide layer on the sidewall of the trench groove, and in-situ polycrystalline by chemical vapor deposition and etching off the polycrystalline on the silicon surface;

[0011] Strip the first silicon nitride layer, etch the second silicon dioxide layer, and form an oxide layer SPACER structure on the sidewalls of the polycrystal;

[0012] Use high energy and high dose SEB to implant boron ions to reduce the base resistance of the parasitic triode; Through N+ lithography and ion implantation, source injection and activation are achieved;

[0013] Perform deposition and planarization of the dielectric, carry out the first step of dielectric hole etching and silicon hole etching, use hole injection to inject P-type high-concentration impurities into the silicon surface at the bottom of the hole, and P-type medium-concentration doping into the deep body region; Finally, thermal activation is carried out by rapid annealing to form the body region lead-out;

[0014] Use tungsten filling and polishing to achieve metal lead-out of the contact hole; Through metal deposition, lithography and etching, metal interconnection is achieved to complete the overall device.

[0015] In one embodiment, the thickness of the first silicon oxide layer is The P-well implantation is formed by ion implantation process, in which B element is implanted, the energy is 50 - 120 KeV, and the dose is 1E13 - 5E13 atoms / cm 2 。

[0016] In one embodiment, the thickness of the second silicon dioxide layer is The thickness of the first silicon nitride layer is The depth of the trench groove varies according to actual needs, and the corresponding array has a strip-shaped gate trench structure and a square-shaped gate trench structure, and the depth range is 0.5 - 1 μm.

[0017] In one embodiment, the thickness of the third silicon dioxide layer retained at the bottom of the trench groove is

[0018] In one embodiment, the growth of the gate oxide layer uses a low-temperature wet oxygen process, and the thickness is The growth temperature is 700 - 1000 °C.

[0019] In one embodiment, the high energy and high dose SEB implantation of boron ions includes: the implantation energy is 150 - 300 KeV, and the implantation dose is 1E14 - 5E14 atoms / cm 2 。

[0020] In one embodiment, the N+ lithography and ion implantation include: the implanted element is As / P, the implantation energy is 60 - 100 KeV, and the implantation dose is 5E15 - 1E16 atoms / cm 2 。

[0021] A process method for improving the single - event immunity of trench - type MOSFETs provided by the present invention has the following beneficial effects:

[0022] (1) The well region implantation and high - temperature drive - in processes are set before the gate oxide process to avoid the influence of high temperature on the quality of the gate oxide;

[0023] (2) By using high - density plasma chemical vapor deposition process, chemical mechanical polishing and wet process, the thickness of the oxide layer at the bottom of the trench is increased to enhance the single - event gate - rupture resistance of the MOSFET device;

[0024] (3) Using the polycrystalline SPACER structure to achieve high - energy and high - dose implantation in the body region, reducing the base resistance and improving the hole extraction ability, thereby enhancing the single - event burnout resistance of the MOSFET;

[0025] (4) For the total - dose resistance requirement of the gate oxide itself, a low - temperature wet - oxygen process needs to be used in the process.

[0026] By optimizing the process steps and process flow, the present invention can improve the single - event immunity of trench - type MOSFET products with a limited increase in process difficulty and manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of P - well implantation and drive - in structure;

[0028] Figure 2 is a schematic diagram of forming a trench groove structure by TR lithography and etching;

[0029] Figure 3 is a schematic diagram of the bottom oxidation thickening structure of the trench groove;

[0030] Figure 4 is a schematic diagram of gate oxide growth and gate polycrystalline back - etching;

[0031] Figure 5 is a schematic diagram of removing silicon nitride and forming a SPACER structure;

[0032] Figure 6 is a schematic diagram of SEB implantation and activation structure;

[0033] Figure 7 is a schematic diagram of N + implantation and activation;

[0034] Figure 8 is a schematic diagram of dielectric deposition and surface planarization;

[0035] Figure 9 is a schematic diagram of via etching and via implantation activation structure;

[0036] Figure 10It is a schematic diagram of device interconnection after metal lithography / etching. Specific Embodiments

[0037] The following further elaborates in detail a process method for enhancing the single - event immunity of trench - type MOSFETs proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0038] The radiation - resistant trench - type MOSFET device is a three - terminal discrete device. The front side of the wafer is divided into two parts: the source region (Source) and the gate region (Gate). These two regions are isolated from the outside by the trench method or field oxide isolation; the drain region (Drain) of the device is on the back side of the wafer. The gate is led out to the die edge through the polycrystal in the trench, and then led out through contact holes and metal interconnections on it; the drain only needs to be thinned on the back side and plated with metal for connection. As understood by those skilled in the art, the present invention will not describe it.

[0039] The process of the present invention is a process processing technology proposed for the source electrode of the wafer, mainly for the cell region, and a trench isolation ring is used to achieve junction termination in the entire die region.

[0040] The present invention provides a process method for enhancing the single - event immunity of trench - type MOSFETs. Based on the excellent on - resistance characteristics of the trench - gate structure, radiation - resistance performance is strengthened, and the single - event burnout resistance of trench - type MOSFET products is effectively improved by improving some designs and processes.

[0041] Specifically, the radiation - resistant trench - type MOSFET process processing is completed through the following method:

[0042] Taking the N - type device as an example, the P - type device can be obtained by corresponding methods. Grow the first silicon oxide layer 2 on the silicon epitaxial wafer Epi 1, where the thickness of the first silicon oxide layer 2 is Through the ion implantation process, P - well (PW) implantation is realized, where B element is implanted, the energy is 50 - 120 KeV, and the dose is 1E13 - 5E13 atoms / cm 2 ; Perform a high - temperature drive - in process on the P - type well implantation to form as Figure 1 shown;

[0043] Then deposit the second silicon oxide layer 3 and the first silicon nitride layer 4 by chemical vapor deposition to form a three - layer thin - film structure of thermal silicon oxide - deposited silicon oxide - deposited silicon nitride on the silicon surface. The thickness of the second silicon oxide layer is The thickness of the first silicon nitride layer 4 is A trench groove 5 with a certain inclination angle and a certain depth is dug on the wafer through the TR trench lithography and etching process. The depth of the trench groove 5 is 0.5 - 1 μm, as Figure 2 shown. The etching depth varies according to actual requirements, and corresponding arrays have strip-shaped gate trench structures, square-grid gate trench structures, etc.

[0044] After the trench groove process is completed, the trench groove 5 is filled with the third silicon dioxide 6 by means of high-density plasma chemical vapor deposition, and then the excess third silicon dioxide on the surface is removed by chemical mechanical polishing. The third silicon dioxide filled in the trench groove 5 is rinsed by the wet process of hydrofluoric acid, and a part of the third silicon dioxide is retained at the bottom of the trench groove 5 to ensure the single-event gate rupture resistance of the trench MOSFET; the thickness of the retained third silicon dioxide is as Figure 3 shown.

[0045] After the trench groove bottom thickening process is completed, a gate oxide layer 7 is grown on the sidewalls of the trench groove 5 by means of low-temperature wet oxygen process, and in-situ polycrystal 8 is deposited by chemical vapor deposition. Considering the requirements of anti-radiation characteristics, the gate oxide layer is generally grown by the low-temperature wet oxygen process, and the thickness is The growth temperature is 700 - 1000 °C. The polysilicon on the silicon surface is etched off by the gate polysilicon back-etching process, as shown in Figure 4 .

[0046] The first silicon nitride layer 4 used as a hard mask layer is removed by the phosphoric acid process, and the second silicon dioxide layer 3 is etched by dry etching of the oxide layer to form an oxide layer SPACER structure 9 on the sidewalls of the polycrystal 8, as shown in Figure 5 .

[0047] High-energy and high-dose SEB is used to inject boron ions. The injection energy is 150 - 300 keV, and the injection dose is 1E14 - 5E14 ions / cm 2 , as shown in Figure 6 . This process step can not only achieve body region concentration enhancement, reduce the base resistance of the parasitic triode, but also use the polysilicon sidewall to avoid the influence of injection on the channel.

[0048] Through N+ lithography and ion implantation, source injection and activation are achieved. The implanted element is As / P, the injection energy is 60 - 100 keV, and the injection dose is 5E15 - 1E16 ions / cm 2 , as Figure 7 shown.

[0049] So far, the processing of the front-end device process has been completed, and then the deposition and planarization of the dielectric 10 are carried out by chemical vapor deposition, as shown in Figure 8 .

[0050] Using hole lithography, the first step is to etch the dielectric holes and silicon holes. P-type high-concentration impurities are implanted into the silicon surface at the bottom of the holes by hole implantation, and P-type medium-concentration doping is performed in the deep body region; finally, thermal activation is carried out by rapid annealing to form the body region lead-out, as Figure 9 shown.

[0051] Using tungsten filling and polishing, the metal lead-out of the contact holes is realized. Through metal deposition, lithography and etching, metal interconnection is realized to complete the overall device as Figure 10 shown.

[0052] The present invention proposes a design and process manufacturing technology for improving the single-event immunity of trench MOSFETs, which performs radiation hardening on the basis of achieving excellent electrical performance to better meet the usage environment in the space field.

[0053] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the claims.

Claims

1. A process method for improving the single-event immunity of trench MOSFETs, characterized in that, Including: Growing a first silicon oxide layer on a silicon epitaxial wafer and implementing P-well implantation, and performing a high-temperature drive-in process on the P-type well implantation; Depositing a second silicon dioxide layer and a first silicon nitride layer again to form a three-layer thin film structure of thermal silicon oxide - deposited silicon dioxide - deposited silicon nitride, and digging a trench groove on the wafer; Filling the trench groove with a third silicon dioxide, and then grinding to remove the excess third silicon dioxide on the surface; rinsing the third silicon dioxide filled in the trench groove, and retaining a part of the third silicon dioxide at the bottom of the trench groove; Growing a gate oxide layer on the sidewall of the trench groove, in-situ polycrystal depositing by chemical vapor deposition and etching the polycrystal on the silicon surface; Stripping the first silicon nitride layer, etching the second silicon dioxide layer, and forming an oxide layer SPACER structure on the sidewall of the polycrystal; Injecting boron ions by using high energy and high dose SEB to reduce the base region resistance of the parasitic triode; realizing source injection and activation through N+ lithography and ion implantation; Performing deposition and planarization treatment of the dielectric, performing the first step of dielectric hole etching and silicon hole etching, injecting P-type high-concentration impurities into the silicon surface at the bottom of the hole by hole injection, and doping P-type medium concentration into the deep body region; finally, performing thermal activation to form a body region lead-out by rapid annealing; Realizing contact hole metal lead-out by tungsten filling and grinding; realizing metal interconnection through metal deposition, lithography and etching, and completing the overall device.

2. The process method for improving the single-event immunity of a trench MOSFET according to claim 1, characterized in that The thickness of the first silicon oxide layer is The P-well implantation is formed by an ion implantation process, in which element B is implanted with an energy of 50 - 120 keV and a dose of 1E13 - 5E13 atoms / cm 2 .

3. The process method for improving the single-event immunity of a trench MOSFET as described in claim 1, wherein, The thickness of the second silicon dioxide layer is The thickness of the first silicon nitride layer is The depth of the trench varies according to actual requirements. The corresponding array has a strip-shaped gate trench structure and a checkerboard-shaped gate trench structure, and the depth ranges from 0.5 to 1 μm.

4. The process method for improving the single-event immunity of a trench MOSFET as described in claim 1, wherein The thickness of the third silicon dioxide retained at the bottom of the trench is 5. The process method for improving the single-event immunity of a trench MOSFET as described in claim 1, characterized in that, The gate oxide layer is grown using a low-temperature wet oxygen process and has a thickness of The growth temperature is 700 to 1000 °C.

6. The process method for improving the single-event immunity of a trench MOSFET according to claim 1, characterized in that, The high-energy and high-dose SEB boron ion implantation includes: an implantation energy of 150 - 300 keV and an implantation dose of 1E14 - 5E14 ions / cm 2 .

7. The process method for improving the single-event immunity of a trench MOSFET according to claim 1, wherein The above-mentioned N+ lithography and ion implantation include: the implanted element is As / P, the implantation energy is 60-100 keV, and the implantation dose is 5E15-1E16 atoms / cm 2 .

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