Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device, which comprises at least one MOSFET, and the MOSFET comprises a first electrode, a substrate, an epitaxial layer, a current expansion layer, a first doping layer, a second doping layer, a second electrode, a gate, a gate dielectric layer, a bottom shielding layer and an edge shielding layer. The doping concentration of the current expansion layer meets a high-concentration condition; along the second direction, the bottom shielding layer surrounds part of the side wall of the groove; along the first direction, the length of the first part of the edge shielding layer on the epitaxial layer is greater than the length of the second part of the edge shielding layer on the current expansion layer, and the length of the first part of the bottom shielding layer on the epitaxial layer is greater than the length of the second part of the bottom shielding layer on the current expansion layer. Therefore, the JFET effect between the edge shielding layer and the bottom shielding layer and the JFET effect between the first doping layer and the bottom shielding layer are improved, and the device has the good conduction characteristic while the good shielding effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology, wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have advantages over silicon (Si) in terms of physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. The power devices prepared from them, such as diodes, transistors, and power modules, have more excellent electrical properties, which can overcome the defects of silicon-based materials that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature. It is also one of the breakthrough paths to surpass Moore's Law. Therefore, it is widely used in new energy fields, such as photovoltaic fields or energy storage fields.

[0003] refer to Figure 1 As shown, a metal oxide semiconductor field effect transistor (MOSFET) structure based on SiC material is provided. A bottom P-type masking layer 10 is provided under the gate dielectric layer 40 to achieve a masking effect on the electric field at the bottom of the gate dielectric layer 40; deep P-type masking layers 20 are provided on both sides of the gate 30 to achieve a masking effect on the electric field at the corner of the gate 30 trench. However, there is a tradeoff between the masking effect of the electric field at the corner of the gate 30 trench and the conduction characteristics of the device, that is, when the masking effect of the electric field at the corner of the gate 30 trench is improved, the conduction characteristics of the device deteriorate.

[0004] Therefore, how to achieve good masking effect and good conduction characteristics of the device is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In view of this, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can achieve good masking effect while the device has good conduction characteristics.

[0006] To achieve the above objectives, this application has the following technical solutions:

[0007] The present application provides a semiconductor device, wherein the semiconductor device includes at least one metal oxide semiconductor field effect transistor (MOSFET), wherein the MOSFET includes:

[0008] A first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, and a second electrode are stacked in sequence; the substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of the first conductivity type, the first doped layer is of the second conductivity type; the doping concentration of the current spreading layer meets a high concentration condition;

[0009] A trench that penetrates the first doping layer and the second doping layer to the current spreading layer, the surface of the trench being covered by a gate dielectric layer, and the trench being filled with a gate; the gate dielectric layer and the gate extend along a second direction, the second direction being perpendicular to a third direction, and the third direction being perpendicular to the surface where the first electrode is located;

[0010] A bottom shielding layer, the bottom shielding layer being disposed on a side of the trench close to the first electrode, the bottom shielding layer extending along the second direction; the bottom shielding layer being of a second conductivity type; along the second direction, the bottom shielding layer surrounds a part of the sidewall of the trench, and the bottom shielding layer penetrates at least the current spreading layer and a part of the thickness of the epitaxial layer;

[0011] An edge shielding layer penetrates the second doping layer, the first doping layer, the current spreading layer and a part of the thickness of the epitaxial layer, the edge shielding layer extending along the second direction; the edge shielding layer being of a second conductivity type; along a first direction, at least two of the edge shielding layers are respectively disposed on two sides of the gate; the first direction is perpendicular to the second direction and the third direction;

[0012] Along the first direction, the length of the edge shielding layer located in a first part of the epitaxial layer is greater than the length of the edge shielding layer located in a second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

[0013] Optionally, along the first direction, the distance between the edge shielding layer and the gate in the first part of the epitaxial layer is less than the distance between the edge shielding layer and the gate in the second part of the current spreading layer;

[0014] Along the first direction, the bottom shielding layer extends from the first part of the epitaxial layer towards the edge shielding layer.

[0015] Optionally, the trench includes a first-stage trench and a second-stage trench, and the second-stage trench is located on a side of the first-stage trench close to the first electrode;

[0016] Along the first direction, the length of the second-stage trench is less than the length of the first-stage trench;

[0017] The first-stage trench penetrates at least the first doping layer and the second doping layer to the current spreading layer;

[0018] The second-stage trench is located in the current spreading layer.

[0019] Optionally, the bottom shielding layer is disposed on a side of the second-level trench close to the first electrode; along the second direction, the bottom shielding layer surrounds the sidewall of the second-level trench.

[0020] Optionally, the bottom shielding layer surrounds the bottom of the first-level trench and at least part of the sidewalls of the first-level trench located in the current spreading layer and the first doping layer;

[0021] Along the second direction, the length of the bottom shielding layer surrounding at least part of the sidewalls of the first-level trench located in the current spreading layer and the first doping layer is less than a length threshold.

[0022] Optionally, along the first direction, the bottom shielding layer surrounds one sidewall of the first-level trench located in the current spreading layer and the first doping layer.

[0023] Optionally, along the first direction, the bottom shielding layer surrounds both sidewalls of the first-level trench located in the current spreading layer and the first doping layer.

[0024] Optionally, the MOSFET includes a first shielding layer; the first shielding layer is of a second conductivity type; the first shielding layer is located between the epitaxial layer and the second electrode, and the first shielding layer surrounds the gate dielectric layer in the first direction; the first shielding layer extends along the first direction, and along the second direction, the length of the first shielding layer is less than a length threshold.

[0025] Optionally, along the first direction, the length of the first shielding layer is the same as the length of the epitaxial layer;

[0026] Along the second direction, the length of the bottom shielding layer is the same as the length of the gate; along the first direction, the first shielding layer further surrounds the bottom shielding layer.

[0027] Optionally, along the third direction, the sidewall of the trench is an inclined sidewall, and a side of the inclined sidewall away from the bottom shielding layer is inclined toward the edge shielding layer.

[0028] The present application provides a method for manufacturing a semiconductor device, including:

[0029] Successively forming an epitaxial layer and a current spreading layer on a substrate; the doping concentration of the current spreading layer satisfies a high-concentration condition;

[0030] Ion implantation is performed on the current spreading layer and the epitaxial layer to form a first doped layer, a second doped layer and an edge shielding layer, respectively, wherein the substrate, the epitaxial layer, the current spreading layer and the second doped layer are of the first conductivity type, and the first doped layer and the edge shielding layer are of the second conductivity type;

[0031] Etching the first doping layer and the second doping layer to the current spreading layer to form a trench;

[0032] Ion implantation is performed on the bottom of the trench and a portion of the sidewalls of the trench to form a bottom shielding layer; the bottom shielding layer extends along the second direction, the second direction is perpendicular to the third direction, and the third direction is perpendicular to the surface of the substrate; the bottom shielding layer is of the second conductivity type; along the second direction, the bottom shielding layer surrounds a portion of the sidewalls of the trench and penetrates at least the current spreading layer and a portion of the thickness of the epitaxial layer;

[0033] forming a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extending along a second direction;

[0034] forming a first electrode on a side of the substrate away from the epitaxial layer, and forming a second electrode on a side of the second doped layer away from the substrate;

[0035] An edge shielding layer penetrates the second doped layer, the first doped layer, the current spreading layer, and a partial thickness of the epitaxial layer, and the edge shielding layer extends along the second direction; along the first direction, at least two edge shielding layers are respectively arranged on both sides of the gate; the first direction is perpendicular to the second direction and the third direction;

[0036] Along the first direction, the length of the edge shielding layer located in the first part of the epitaxial layer is greater than the length of the edge shielding layer located in the second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

[0037] The present application provides a method for manufacturing a semiconductor device, comprising:

[0038] forming an epitaxial layer on a substrate, and performing ion implantation on the epitaxial layer to form an edge shielding layer located at a first portion of the epitaxial layer;

[0039] forming a current spreading layer on the surface of the epitaxial layer; the doping concentration of the current spreading layer meets a high concentration condition;

[0040] Ion implantation is performed on the current spreading layer to respectively form a first doped layer, a second doped layer, and an edge shielding layer located in the second part of the current spreading layer. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conduction type, and the first doped layer and the edge shielding layer are of a second conduction type;

[0041] The first doped layer and the second doped layer are etched to the current spreading layer to form trenches;

[0042] Ion implantation is performed on the bottom of the trench and part of the sidewalls of the trench to form a bottom shielding layer; the bottom shielding layer extends along the second direction, the second direction is perpendicular to the third direction, and the third direction is the direction perpendicular to the surface where the substrate is located; the bottom shielding layer is of a second conduction type; along the second direction, the bottom shielding layer surrounds part of the sidewalls of the trench, and the bottom shielding layer at least penetrates the current spreading layer and part of the thickness of the epitaxial layer;

[0043] A gate dielectric layer and a gate are formed in the trench; the gate dielectric layer and the gate extend along the second direction;

[0044] A first electrode is formed on the side of the substrate away from the epitaxial layer, and a second electrode is formed on the side of the second doped layer away from the substrate;

[0045] The edge shielding layer penetrates the second doped layer, the first doped layer, the current spreading layer, and part of the thickness of the epitaxial layer, and the edge shielding layer extends along the second direction; along the first direction, at least two edge shielding layers are respectively disposed on both sides of the gate; the first direction is perpendicular to the second direction and the third direction;

[0046] Along the first direction, the length of the edge shielding layer located in the first part of the epitaxial layer is greater than the length of the edge shielding layer located in the second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

[0047] The present application provides a semiconductor device, the semiconductor device includes at least one metal oxide semiconductor field effect transistor MOSFET, the MOSFET includes: a first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, a second electrode, a gate, a gate dielectric layer, a bottom shield layer and an edge shield layer; wherein the first electrode, the substrate, the epitaxial layer, the current spreading layer, the first doped layer, the second doped layer and the second electrode are stacked in sequence, the substrate, the epitaxial layer, the current spreading layer and the second doped layer are of the first conductivity type, the first doped layer is of the second conductivity type, the doping concentration of the current spreading layer meets the high concentration condition, that is, the doping concentration of the current spreading layer is high; the MOSFET includes a first doped layer and a second doped layer. The bottom shielding layer is provided at the bottom of the gate dielectric layer in the second direction, thereby realizing electric field masking at the bottom of the gate dielectric layer by using the bottom shielding layer. Along the second direction, the bottom shielding layer surrounds part of the sidewall of the trench, and the bottom shielding layer at least passes through the current spreading layer and the epitaxial layer of part of the thickness, that is, the bottom shielding layer is not only provided at the bottom of the trench along the second direction, but also extends to the current spreading layer and the epitaxial layer of part of the thickness. The edge shielding layer extends through the second doped layer, the first doped layer, the current spreading layer and the epitaxial layer of a part of the thickness, and extends along the second direction. The edge shielding layer is of the second conductive type. Along the first direction, at least two edge shielding layers are respectively arranged on both sides of the gate. The first direction is perpendicular to the second direction and the third direction, that is, the edge shielding layers are arranged on both sides of the gate, thereby providing electric field shielding for the gate at the trench. Along the first direction, the length of the first part of the edge shielding layer located in the epitaxial layer is greater than the length of the second part of the edge shielding layer located in the current spreading layer, and the bottom shielding layer is located in the epitaxial layer. The length of the first part is greater than the length of the second part of the bottom shielding layer located in the current spreading layer. That is to say, since the doping concentration of the current spreading layer of the first conductive type meets the high concentration condition, the edge shielding layer and the bottom shielding layer of the second conductive type have little effect on the lateral expansion of the current spreading layer when penetrating the current spreading layer, thereby improving the JFET effect between the edge shielding layer and the bottom shielding layer, and the first doped layer and the bottom shielding layer, and improving the conduction characteristics of the device. That is to say, by providing a current spreading layer that meets the high concentration condition, an edge shielding layer located in the first part of the epitaxial layer having a length greater than that of the second part located in the current spreading layer, and a bottom shielding layer, it is possible to achieve better conduction characteristics of the device while having better masking effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0049] Figure 1 Shows a schematic structural diagram of a metal oxide semiconductor field effect transistor structure based on SiC material;

[0050] Figure 2 Shows a top view structural diagram of a semiconductor device provided by an embodiment of the present application;

[0051] Figure 3 Shows Figure 2 A schematic cross-sectional structural diagram of the semiconductor device shown along the AA' direction;

[0052] Figure 4 Shows Figure 2 A schematic cross-sectional structural diagram of the semiconductor device shown along the BB' direction;

[0053] Figure 5 Shows a top view structural diagram of another semiconductor device provided by an embodiment of the present application;

[0054] Figure 6 Shows Figure 2 A schematic cross-sectional structural diagram of the semiconductor device shown along the BB' direction;

[0055] Figure 7 Shows a top view structural diagram of yet another semiconductor device provided by an embodiment of the present application;

[0056] Figure 8 Shows Figure 7 A schematic cross-sectional structural diagram of the semiconductor device shown along the BB' direction;

[0057] Figure 9 Shows a schematic diagram of the blocking characteristic current-voltage (I-V) change curves of a traditional structure MOSFET and a MOSFET provided by the present application;

[0058] Figure 10 Shows a schematic diagram of the electric field distribution at breakdown of a traditional structure MOSFET and a MOSFET provided by the present application;

[0059] Figure 11A schematic diagram showing the current-voltage (IV) change curves of the on-state characteristics of a conventional MOSFET and the MOSFET provided by the present application is shown;

[0060] Figure 12 A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0061] Figures 13 - 18 A schematic structural diagram of a semiconductor device manufactured according to a method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0062] Figure 19 A schematic flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0063] Figures 20 - 22 A schematic structural diagram of manufacturing a semiconductor device according to another method for manufacturing a semiconductor device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0064] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0065] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0066] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0067] refer to Figure 1The figure shows a metal oxide semiconductor field effect transistor (MOSFET) structure based on SiC material. The high electric field of the drift layer 50 leads to a high electric field on the gate dielectric layer 40, which is exacerbated at the corners of the gate 30 trench. This causes the gate dielectric layer 40 to quickly break down under high drain voltages. In addition, this structure has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit. A bottom P-type shielding layer 10 can be provided below the gate dielectric layer 40, and deep P-type shielding layers 20 can be provided on both sides of the gate 30. A certain distance between the deep P-type shielding layer 20 and the gate 30 serves as a current path, thereby achieving a shielding effect on the electric field at the bottom of the gate dielectric layer 40 and the electric field at the corners of the gate 30 trench. However, due to ion scattering, the deep P-type shielding layers 20 on both sides of the gate 30 have a relatively large lateral expansion, which aggravates the junction field effect transistor (JFET) effect between the bottom P-type shielding layer 10 and the deep P-type shielding layers 20 on both sides of the gate 30, degrading the device's conduction characteristics. In addition, there is a tradeoff between the masking effect of the electric field at the corner of the gate trench 30 and the device conduction characteristics. That is, the masking effect of the electric field at the corner of the gate trench is improved, but the device conduction characteristics are deteriorated.

[0068] Therefore, how to achieve good masking effect and good conduction characteristics of the device is a technical problem that needs to be solved urgently.

[0069] Based on this, the present application provides a semiconductor device. The semiconductor device includes at least one metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes: a first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, a second electrode, a gate, a gate dielectric layer, a bottom shielding layer, and an edge shielding layer. Among them, the first electrode, the substrate, the epitaxial layer, the current spreading layer, the first doped layer, the second doped layer, and the second electrode are sequentially stacked. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conduction type, the first doped layer is of a second conduction type, and the doping concentration of the current spreading layer satisfies a high-concentration condition, that is, the doping concentration of the current spreading layer is relatively high. The MOSFET includes a trench that penetrates the first doped layer and the second doped layer to the current spreading layer. The surface of the trench is covered by the gate dielectric layer, and the trench is filled with the gate. The gate dielectric layer and the gate extend along a second direction, and the second direction is perpendicular to a third direction, where the third direction is the direction perpendicular to the surface where the first electrode is located. The bottom shielding layer is disposed on one side of the trench close to the first electrode. The bottom shielding layer extends along the second direction. The bottom shielding layer is of the second conduction type, that is, the bottom shielding layer can be disposed at the bottom of the gate dielectric layer in the second direction, so as to achieve the masking of the electric field at the bottom of the gate dielectric layer by using the bottom shielding layer. Along the second direction, the bottom shielding layer surrounds part of the sidewalls of the trench. The bottom shielding layer at least penetrates the current spreading layer and part of the thickness of the epitaxial layer, that is, the bottom shielding layer is not only disposed at the bottom of the trench in the second direction but also surrounds part of the sidewalls of the trench, so as to effectively improve the electric field aggregation effect of the gate at the trench corner by using the bottom shielding layer on the trench sidewalls and the trench bottom. The edge shielding layer penetrates the second doped layer, the first doped layer, the current spreading layer, and part of the thickness of the epitaxial layer. The edge shielding layer extends along the second direction. The edge shielding layer is of the second conduction type. Along a first direction, at least two edge shielding layers are respectively disposed on both sides of the gate. The first direction is perpendicular to the second direction and the third direction, that is, the edge shielding layer is disposed on both sides of the gate, so as to provide electric field masking for the gate at the trench. Along the first direction, the length of the edge shielding layer located in the first part of the epitaxial layer is greater than the length of the edge shielding layer located in the second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer. That is to say, since the doping concentration of the current spreading layer of the first conduction type satisfies the high-concentration condition, when the edge shielding layer and the bottom shielding layer of the second conduction type penetrate the current spreading layer, the lateral expansion effect on the current spreading layer is relatively small, thereby improving the JFET effect between the edge shielding layer and the bottom shielding layer, the first doped layer and the bottom shielding layer, and enhancing the on-state characteristics of the device. That is to say, by setting a current spreading layer that satisfies the high-concentration condition, an edge shielding layer whose length in the first part of the epitaxial layer is greater than the length in the second part of the current spreading layer, and a bottom shielding layer, it is possible to achieve good masking effect while the device has good on-state characteristics.

[0070] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0071] refer to Figure 2 As shown, it is a schematic diagram of the top view structure of a semiconductor device provided in an embodiment of the present application. The semiconductor device provided in an embodiment of the present application includes at least one metal oxide semiconductor field effect transistor (MOSFET), that is, the semiconductor device may include one or more MOSFETs.

[0072] The MOSFET extends in three directions (a first direction, a second direction, and a third direction) that are perpendicular to each other. Figure 2 The MOSFET shown is a schematic diagram of a top view structure, including a first direction and a second direction perpendicular to each other. The MOSFET can be cross-sectioned along the AA' and BB' directions to obtain Figures 3 - 4 , the AA' direction and the BB' direction are parallel to the first direction, Figure 3 and Figure 4 The third direction is perpendicular to the first direction.

[0073] The MOSFET includes a first electrode 210 , a substrate 110 , an epitaxial layer 120 , a current spreading layer 130 , a first doping layer 140 , a second doping layer 150 , a second electrode 220 , a gate 310 , a gate dielectric layer 320 , a bottom shielding layer 410 and an edge shielding layer 420 .

[0074] In the embodiment of the present application, the first electrode 210, the substrate 110, the epitaxial layer 120, the current spreading layer 130, the first doping layer 140, the second doping layer 150, and the second electrode 220 are stacked in sequence. Figure 3 or Figure 4 The third direction is perpendicular to the surface of the first electrode 110. Along the third direction, the substrate 110 is located on the first electrode 210, the epitaxial layer 120 is located on the substrate 110, the current spreading layer 130 is located on the epitaxial layer 120, the first doped layer 140 is located on the current spreading layer 130, the second doped layer 150 is located on the first doped layer 140, and the second electrode 220 is located on the second doped layer 150.

[0075] Specifically, the first electrode 210 or the second electrode 220 is made of a material with good conductivity, such as a metal material. As an example, the first electrode 210 is a drain electrode, and the second electrode 220 is a source electrode.

[0076] In the embodiment of the present application, the substrate 110 , the epitaxial layer 120 , the current spreading layer 130 and the second doped layer 150 are of the first conductivity type, and the first doped layer 140 is of the second conductivity type.

[0077] As an example, the first conduction type is N-type and the second conduction type is P-type, that is, the substrate 110, the epitaxial layer 120, the current spreading layer 130, and the second doping layer 150 are N-type, and the first doping layer 140 is P-type.

[0078] The material of the substrate 110 can be a wide bandgap semiconductor material, such as SiC, GaN, Ga2O3, C, or AlN. The epitaxial layer 110 can be formed on the substrate 110 by an epitaxial process. The current spreading layer 130 can be formed by ion implanting a part of the thickness of the epitaxial layer 110, or the current spreading layer 130 can be formed on the surface of the epitaxial layer 110 by an epitaxial process. The first doping layer 140 and the second doping layer 150 can be sequentially formed by ion implanting a part of the thickness of the current spreading layer 130.

[0079] The doping concentration of the current spreading layer 130 satisfies a high concentration condition, that is, the doping concentration of the current spreading layer 130 is relatively high. When ion implanting the current spreading layer 130 subsequently, the lateral expansion of ions caused by ion implantation scattering can be weakened.

[0080] As a possible implementation manner, the high concentration condition is that the doping concentration of the current spreading layer 130 is greater than a concentration threshold, and the concentration threshold is determined according to the actual situation. For example, the concentration threshold is 4e16 cm -3 , and this concentration threshold is the common doping concentration of the current spreading layer included in the current MOSFET.

[0081] As another possible implementation manner, the high concentration condition is that the doping concentration of the current spreading layer 130 is greater than the doping concentration of the epitaxial layer 120, that is, the doping concentration of the current spreading layer 130 is relatively high and the doping concentration of the epitaxial layer 120 is relatively low, so as to use the epitaxial layer 120 as a breakdown voltage layer and the current spreading layer 130 as a film layer for weakening the lateral expansion of ion implantation scattering.

[0082] In the embodiment of the present application, the MOSFET includes: a trench that penetrates through the first doping layer 140 and the second doping layer 150 to the current spreading layer 130, that is, the trench can extend to the current spreading layer 130, as shown in Figure 3 or Figure 4 shown.

[0083] The surface of the trench is covered by a gate dielectric layer 320, that is, the sidewalls and the bottom of the trench are covered by the gate dielectric layer 320. The trench is filled with a gate 310, that is, the gate dielectric layer 320 isolates the gate 310 from the first doping layer 140, the second doping layer 150, and the current spreading layer 130.

[0084] As an example, the material of the gate dielectric layer 320 can be silicon oxide, and the material of the gate 310 can be polysilicon.

[0085] The gate dielectric layer 320 and the gate 310 extend along the second direction, which is perpendicular to the third direction. Figure 2 shown.

[0086] As an example, the length of the gate 310 and the gate dielectric layer 320 along the second direction is the same as the length of the current spreading layer 130 , that is, the gate 310 and the gate dielectric layer 320 may span the entire current spreading layer 130 .

[0087] In an embodiment of the present application, the bottom shielding layer 410 is of the second conductive type, and the bottom shielding layer 410 is arranged on the side of the trench close to the first electrode 210. The bottom shielding layer 410 is arranged on the side of the gate dielectric layer 320 close to the first electrode 210, that is, the bottom shielding layer 410 is arranged below the gate dielectric layer 320. Based on the different conductive types of the bottom shielding layer 410 and the current spreading layer 130 or the epitaxial layer 120, combined with the bottom shielding layer 410 being arranged below the gate dielectric layer 320, the electric field shielding of the trench bottom and the trench corner is achieved by using the bottom shielding layer 410.

[0088] The bottom shielding layer 410 extends along the second direction, that is, the bottom shielding layer 410 and the gate 310 or the gate dielectric layer 320 extend in the same direction, thereby achieving an electric field shielding effect.

[0089] The bottom shield layer 410 at least penetrates the current spreading layer 130 and a portion of the thickness of the epitaxial layer 120, that is, the bottom shield layer 410 is at least disposed on the current spreading layer 130 and the epitaxial layer 120. Along the second direction, the bottom shield layer 410 surrounds a portion of the sidewalls of the trench, that is, the bottom shield layer 410 is not only disposed along the second direction at the bottom of the trench but also surrounds a portion of the sidewalls of the trench. The bottom shield layer 410 on the trench sidewalls and bottom effectively improves the electric field concentration effect of the gate 310 at the trench corner, thereby further achieving an electric field shielding effect.

[0090] In an embodiment of the present application, the MOSFET may be provided with an edge shielding layer 420. The edge shielding layer 420 is of the second conductivity type, which is different from the conductivity type of the current spreading layer 130 or the epitaxial layer 120, thereby achieving an electric field shielding effect.

[0091] The edge shielding layer 420 penetrates the second doping layer 150, the first doping layer 140, the current spreading layer 130 and a portion of the thickness of the epitaxial layer 120, that is, the edge shielding layer 420 is located between the epitaxial layer 120 and the second electrode 220. Figure 3 and Figure 4As shown. Along the first direction, at least two edge shielding layers 420 are respectively disposed on both sides of the gate 310. The distance between the edge shielding layer 420 and the gate 310 is greater than the distance threshold, that is, the distance between the edge shielding layer 420 and the gate 310 is relatively far, avoiding the narrow channel caused by a relatively close distance. That is to say, by disposing the edge shielding layer 420 that does not contact the gate on both sides of the gate 310, further electric field shielding of the trench bottom and corners is achieved, that is, the trench is further protected.

[0092] The edge shielding layer 420 extends along the second direction. The distance between the edge shielding layer 420 and the positive projection of the bottom shielding layer 410 in the first direction is greater than or equal to 0, that is, the positive projections of the edge shielding layer 420 and the bottom shielding layer 410 in the first direction do not overlap. That is to say, when the edge shielding layer 420 extends in the second direction, it will not extend to the position where the bottom shielding layer 410 is located. The edge shielding layer 420 and the bottom shielding layer 410 are not in the same cross-section. Therefore, there is no serious JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, further improving the on-state characteristics of the device.

[0093] In the embodiment of the present application, both the edge shielding layer 420 and the bottom shielding layer 410 penetrate through the current spreading layer 130 and a part of the thickness of the epitaxial layer 120. Therefore, both the edge shielding layer 420 and the bottom shielding layer 410 include a first part located in the epitaxial layer 120 and a second part located in the current spreading layer 130. Along the first direction, the length of the first part of the edge shielding layer 420 located in the epitaxial layer 120 is greater than the length of the second part of the edge shielding layer 420 located in the current spreading layer 130, and the length of the first part of the bottom shielding layer 410 located in the epitaxial layer 120 is greater than the length of the second part of the bottom shielding layer 410 located in the current spreading layer 130. Refer to Figure 3 or Figure 4 As shown. That is to say, since the doping concentration of the current spreading layer 130 of the first conductivity type satisfies the high-concentration condition, when the edge shielding layer 420 and the bottom shielding layer 410 of the second conductivity type penetrate through the current spreading layer 130, the lateral expansion effect on the current spreading layer 130 is relatively small. That is, the high doping concentration of the current spreading layer 130 can weaken the lateral expansion caused by ion implantation scattering during the formation of the edge shielding layer 420 and the bottom shielding layer 410, thereby improving the JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, the first doping layer 140 and the bottom shielding layer 410, and improving the on-state characteristics of the device.

[0094] That is to say, by providing a current spreading layer 120 that meets high concentration conditions, an edge shielding layer 420 located in the first portion of the epitaxial layer 120 having a length greater than that of the second portion located in the current spreading layer 130, and a bottom shielding layer 410, it is possible to achieve better masking effects while also achieving better conduction characteristics of the device.

[0095] In the embodiment of the present application, the doping concentration of the current spreading layer 130 meets the high concentration condition, and the doping concentration of the epitaxial layer 120 is less than the doping concentration of the current spreading layer 130. Therefore, the lateral expansion of the edge shielding layer 420 and the bottom shielding layer 410 in the current spreading layer 130 is weakened, but the lateral expansion in the epitaxial layer 120 is not weakened. Therefore, along the first direction, the distance between the edge shielding layer 420 located in the first portion of the epitaxial layer 120 and the gate 310 is less than the distance between the edge shielding layer 420 located in the second portion of the current spreading layer 130 and the gate 310, that is, the edge shielding layer 420 located in the first portion of the epitaxial layer 120 is closer to the gate 310, with reference to FIG. Figure 3 or Figure 4 As shown, the edge shielding layer 420 located on the left side of the gate 310 forms an L-shaped structure, and the edge shielding layer 420 located on the right side of the gate 310 forms an inverted L-shaped structure, thereby further shielding the bottom and corner of the trench from the electric field; accordingly, along the first direction, the first portion of the bottom shielding layer 410 located on the epitaxial layer 120 extends toward the edge shielding layer 420, that is, the first portion of the bottom shielding layer 410 located on the epitaxial layer 120 is closer to the edge shielding layer 420, with reference to FIG. Figure 3 or Figure 4 As shown, the bottom shielding layer 410 around the left sidewall of the trench forms an inverted L-shaped structure, and the bottom shielding layer 410 around the right sidewall of the trench forms an L-shaped structure, thereby further shielding the trench bottom and corners from electric fields.

[0096] In the embodiment of the present application, the trench includes a first-level trench 610 and a second-level trench 620, forming a two-level trench structure. The second-level trench 620 is located on the side of the first-level trench 610 close to the first electrode 210, that is, the second-level trench 620 is located below the first-level trench 610. Along the first direction, the length of the second-level trench 620 is less than the length of the first-level trench 610; the first-level trench 610 at least penetrates the first doping layer 140 and the second doping layer 150 to the current spreading layer 130; the second-level trench 620 is located in the current spreading layer 130, with reference to FIG. Figure 3 or Figure 4 shown.

[0097] That is to say, the corner of the first-level trench 610 is arranged in the current spreading layer 130, and the corner of the second-level trench 620 can also be arranged in the current spreading layer 130. The first-level trench 610 and the second-level trench 620 are both provided with the gate 310, and both the first-level trench 610 and the second-level trench 620 have corners, so that the two-level trench structure can have 4 corners. The 4 corners can disperse the electric field lines of the electric field, thereby reducing the peak electric field inside the gate dielectric layer 320, reducing the probability of breakdown of the gate dielectric layer 320, improving the high-voltage spike tolerance in the circuit, and ultimately improving the reliability of the gate dielectric layer 320.

[0098] The thickness of the current spreading layer 130 is greater than the height of the second-level trench 620, that is, the current spreading layer 130 has enough space to realize the arrangement of the second-level trench 620 in the current spreading layer 130.

[0099] In the embodiment of the present application, the bottom shielding layer 410 is arranged on the side of the second-level trench 620 close to the first electrode 110, that is, the bottom shielding layer 410 is arranged below the second-level trench 620, as shown in Figure 3 or Figure 4 shown. Along the second direction, the bottom shielding layer 410 surrounds the side wall of the second-level trench 620, that is, the bottom shielding layer 410 completely wraps the second-level trench 620, thereby effectively improving the electric field aggregation effect at the corner of the gate 310 trench and further improving the electric field shielding effect.

[0100] In the embodiment of the present application, in addition to surrounding the side wall of the second-level trench 620, along the first direction, the bottom shielding layer 410 can also surround the bottom of the first-level trench 610 and at least part of the side wall of the first-level trench 610 located in the current spreading layer 130 and the first doping layer 140, that is, the bottom shielding layer 410 realizes the contact between the bottom shielding layer 410 and the first doping layer 140 both of which are of the second conductive type by surrounding at least part of the side wall of the first-level trench 610 located in the first doping layer 140, and finally realizes the grounding of the bottom shielding layer 410 by using the first doping layer 140.

[0101] Refer to Figure 2 shown. Along the second direction, the length of the bottom shielding layer 410 surrounding at least part of the side wall of the first-level trench 610 located in the current spreading layer 130 and the first doping layer 140 is less than the length threshold, that is to say, the length of the bottom shielding layer 410 in contact with the first doping layer 140 is small in the second direction, so as to avoid the influence on the on-state characteristics of the device caused by the too large area of the bottom shielding layer 410 in contact with the first doping layer 140.

[0102] As a possible implementation, along the first direction, the bottom shielding layer 410 is located around the first-level trench 610 on one side wall of the current spreading layer 130 and the first doping layer 140. Refer to Figure 5 and Figure 6 as shown. Figure 5 The top view structural schematic diagram of another semiconductor device provided by the embodiment of the present application is shown.

[0103] Figure 6 Shown is Figure 5 the cross-sectional structural schematic diagram of the semiconductor device shown along the BB' direction. Figure 5 The cross-section of the semiconductor device shown along the AA' direction is Figure 3 . Refer to Figure 5 or Figure 6 as shown. Along the first direction, if the bottom shielding layer 410 is disposed on one side of the side wall of the first-level trench 610, the contact between the bottom shielding layer 410 and the first doping layer 140 can be achieved, and the grounding of the bottom shielding layer 410 can be achieved.

[0104] The bottom shielding layer 410 can be disposed on any one side of the side wall of the first-level trench 610, and can be specifically set according to the actual situation. Refer to Figure 5 as shown. The bottom shielding layer 410 can be disposed on the left or right side of the side wall of the first-level trench 610.

[0105] As another possible implementation, along the first direction, the bottom shielding layer 410 is located around the first-level trench 610 on both side walls of the current spreading layer 130 and the first doping layer 140. Refer to Figure 2 and Figure 4 as shown. That is to say, if the bottom shielding layer 410 is disposed on both sides of the side wall of the first-level trench 610, the contact area between the bottom shielding layer 410 and the first doping layer 140 can be increased, and the grounding effect of the bottom shielding layer 410 can be further improved.

[0106] In the embodiment of the present application, the MOSFET can be provided with a first shielding layer 430. The first shielding layer 430 is located between the epitaxial layer 120 and the second electrode 220. That is to say, along the second direction, the first shielding layer 430 cuts off the current spreading layer 130, the first doping layer 140, and the second doping layer 150, so that the current spreading layer 130, the first doping layer 140, and the second doping layer in some regions are discontinuous in the second direction. Refer to Figure 7 and Figure 8 as shown. Figure 7 The top view structural schematic diagram of yet another semiconductor device provided by the embodiment of the present application is shown. Figure 8 Shown is Figure 7 the cross-sectional structural schematic diagram of the semiconductor device shown along the BB' direction. Figure 7The cross-section of the semiconductor device shown along the AA' direction is Figure 3 .

[0107] The MOSFET may be provided with at least one first shielding layer 430, as shown in Figure 7 . The first shielding layer 430 is of a second conductivity type, different from the conductivity type of the current spreading layer 130 or the epitaxial layer 120, so as to achieve an electric field shielding effect. The first shielding layer 430 is in contact with the edge shielding layer 420 and the bottom shielding layer 410, so as to ground the edge shielding layer 420 and the bottom shielding layer 410. The first shielding layer 430 surrounds the gate dielectric layer 320 in a first direction, that is, the first shielding layer 430 realizes the electric field shielding at the bottom and corners of the trench by surrounding the gate dielectric layer 320. The first shielding layer 430 extends along the first direction, and the first direction is perpendicular to the second direction and the third direction, that is, the first shielding layer 430 is arranged crosswise with respect to the gate 310 or the gate dielectric layer 320. Along the second direction, the length of the first shielding layer 430 is less than a length threshold, as shown in Figure 7 , that is, the length of the first shielding layer 430 is small in the second direction, so as to avoid the influence on the conduction characteristics of the device caused by the too large area of the first shielding layer 430.

[0108] As a possible implementation manner, along the first direction, the length of the first shielding layer 430 is equal to the length of the epitaxial layer 120, that is, the first shielding layer 430 spans the entire length of the epitaxial layer 120, and the first shielding layer 420 completely cuts off the current spreading layer 130, the first doping layer 140 and the second doping layer 150 in the second direction. Along the second direction, the length of the bottom shielding layer 410 is equal to the length of the gate 310. Along the first direction, the first shielding layer 430 also surrounds the bottom shielding layer 410, that is, the first shielding layer 430 does not cut off the bottom shielding layer 410 in the second direction, and the first shielding layer 430 directly surrounds the bottom shielding layer 410 to ground the bottom shielding layer 410. That is to say, the bottom shielding layer 410 without interruption is adopted in the second direction to protect the bottom and corners of the trench, or the first shielding layer 430 that spans the entire epitaxial layer 120 and surrounds the bottom shielding layer 410 can be arranged in the second direction, so as to improve the electric field masking effect.

[0109] As another possible implementation manner, as shown in Figure 8As shown, along the first direction, the length of the first shielding layer 430 is equal to the length of the epitaxial layer 120, that is, the first shielding layer 430 spans the entire length of the epitaxial layer 120. The first shielding layer 420 completely separates the current spreading layer 130, the first doping layer 140, and the second doping layer 150 in the second direction. Along the second direction, the length of the bottom shielding layer 410 is less than the length of the gate 310. Along the first direction, the area where the first shielding layer 430 is provided is not provided with the bottom shielding layer 410, that is, the first shielding layer 430 separates the bottom shielding layer 410 in the second direction, and the first shielding layer 430 does not surround the bottom shielding layer 410. That is to say, the first shielding layer 430 and the bottom shielding layer 410 achieve the grounding of the bottom shielding layer 410 by using the contacting side surfaces.

[0110] In an embodiment of the present application, along the third direction, the side wall of the trench is an inclined side wall, and the side of the inclined side wall away from the bottom shielding layer 410 is inclined toward the edge shielding layer 420. That is to say, the intersection point of the extension lines of the inclined side walls of the trench is on the side of the epitaxial layer 120, so as to achieve that the trench is wider at the top and narrower at the bottom, which is beneficial to setting the bottom shielding layer 410 on the side wall of the trench.

[0111] In an embodiment of the present application, the MOSFET further includes an interlayer dielectric layer 160, and the interlayer dielectric layer 160 is disposed between the gate 310 and the second electrode 220.

[0112] When the trench includes a first-stage trench 610 and a second-stage trench 620, the side walls of both the first-stage trench 610 and the second-stage trench 620 are inclined side walls, as shown in Figure 3 or Figure 4 shown.

[0113] As an example, a MOSFET with a traditional structure includes an edge shielding layer, a bottom shielding layer, a first doping layer, a current spreading layer, and a single trench. The depth of the edge shielding layer is 1.5 μm and the doping concentration is 2e18 cm -3 ; the doping concentration of the bottom shielding layer is 2e18 cm -3 ; the depth of the first doping layer is 0.7 μm and the doping concentration is 1.5e17 cm -3 ; the depth of the current spreading layer is 1 μm and the doping concentration is 4e16 cm -3 ; the depth of the trench is 0.9 μm. The MOSFET provided by the present application includes an edge shielding layer 420, a bottom shielding layer 410, a first doping layer 140, a current spreading layer 130, and a two-stage gate trench. The depth of the edge shielding layer 420 is 1.8 μm and the doping concentration is 2e18 cm -3 ; the doping concentration of the bottom shielding layer 410 is 2e18 cm -3 ; the depth of the first doping layer 140 is 0.7 μm and the doping concentration is 1.5e17 cm-3 The depth of the current spreading layer 130 is 1.4 μm and the doping concentration is 8e16 cm -3 The depth of the first-level trench 610 is 0.9 μm, and the depth of the second-level trench 620 is 0.3 μm. That is, compared to conventional structures, the edge shielding layer 420 of the MOSFET provided in the present embodiment is increased in depth, the depth and doping concentration of the current spreading layer 130 are increased, and the depth of the trench is also increased.

[0114] refer to Figures 9 - 11 As shown, Figure 9 The figure shows the blocking characteristic current-voltage (IV) curves of the conventional MOSFET and the MOSFET provided by the present application. Figure 10 As shown, Figure 10 The diagram shows the electric field distribution of the MOSFET with a conventional structure and the MOSFET provided by the present application during breakdown. Figure 11 As shown, Figure 11 A schematic diagram of the current-voltage (IV) change curve of the conduction characteristics of a traditional MOSFET and the MOSFET provided by the present application is shown. Figures 9 - 11 The simulation results show that the blocking and conduction characteristics of the MOSFET provided by this application are better than those of the traditional structure. The breakdown voltage and gate oxide peak electric field at 1200V of the traditional structure are 1504V and 0.88MV / cm respectively, while the breakdown voltage and gate oxide peak electric field at 1200V of the MOSFET provided by this application are 1778V and 0.70MV / cm respectively, which are improved by 18.2% and 20.5% respectively. The specific on-resistance of the traditional structure is 5.60mΩ·cm 2 The specific on-resistance of the MOSFET provided in this application is 4.68mΩ·cm 2 , an increase of 16.4%.

[0115] Based on the semiconductor device provided in the above embodiment, the present application also provides a method for manufacturing a semiconductor device, referring to Figure 12 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0116] The method for manufacturing a semiconductor device provided in an embodiment of the present application includes the following steps:

[0117] S101 , forming an epitaxial layer and a current spreading layer in sequence on a substrate, wherein the doping concentration of the current spreading layer meets a high concentration condition.

[0118] In an embodiment of the present application, the material of the substrate 110 may be a wide-bandgap semiconductor material, such as SiC, GaN, Ga2O3, C, or AlN. An epitaxial layer 120 and a current spreading layer 130 may be sequentially formed on the substrate 110, refer to Figure 13 as shown.

[0119] Specifically, the epitaxial layer 120 may be formed on the substrate 110 by an epitaxial process. The current spreading layer 130 may be formed by ion-implanting a partial thickness of the epitaxial layer 110, or the current spreading layer 130 may be formed on the surface of the epitaxial layer 110 by an epitaxial process.

[0120] In an embodiment of the present application, the substrate 110, the epitaxial layer 120, and the current spreading layer 130 are of a first conduction type.

[0121] As an example, the first conduction type is N-type, that is, the substrate 110, the epitaxial layer 120, and the current spreading layer 130 are N-type.

[0122] The doping concentration of the current spreading layer 130 satisfies a high-concentration condition, that is, the doping concentration of the current spreading layer 130 is relatively high. When ion-implanting the current spreading layer 130 subsequently, the lateral expansion of ions caused by ion-implantation scattering can be weakened.

[0123] As a possible implementation manner, the high-concentration condition is that the doping concentration of the current spreading layer 130 is greater than a concentration threshold, and the concentration threshold is determined according to actual conditions. For example, the concentration threshold is 4e16 cm -3 , and this concentration threshold is the common doping concentration of the current spreading layer included in the current MOSFET.

[0124] As another possible implementation manner, the high-concentration condition is that the doping concentration of the current spreading layer 130 is greater than the doping concentration of the epitaxial layer 120, that is, the doping concentration of the current spreading layer 130 is relatively high and the doping concentration of the epitaxial layer 120 is relatively low, so as to implement using the epitaxial layer 120 as a voltage-resistant layer and the current spreading layer 130 as a film layer for weakening the lateral expansion of ion-implantation scattering.

[0125] S102: Ion-implant the current spreading layer and the epitaxial layer to respectively form a first doped layer, a second doped layer, and an edge shielding layer. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conduction type, and the first doped layer and the edge shielding layer are of a second conduction type.

[0126] In an embodiment of the present application, after forming the current spreading layer 130, the current spreading layer 130 and the epitaxial layer 120 may be ion-implanted to respectively form a first doped layer 140, a second doped layer 150, and an edge shielding layer 420, refer to Figure 14 as shown.

[0127] Specifically, the second doping layer 150 is of the first conductivity type, and the first doping layer 140 and the edge shielding layer 420 are of the second conductivity type; the edge shielding layer 420 is located between the epitaxial layer 120 and the subsequently formed second electrode 220.

[0128] The first doping layer 140 and the second doping layer 150 can be formed by ion-implanting a partial thickness of the current spreading layer 130 in sequence.

[0129] When ion-implanting the current spreading layer 130 and the epitaxial layer 120, the edge shielding layer 420 is also formed.

[0130] The edge shielding layer 420 penetrates through the second doping layer 150, the first doping layer 140, the current spreading layer 130, and a partial thickness of the epitaxial layer 120, as shown in the reference Figure 14 shown.

[0131] S103, etching the first doping layer and the second doping layer to the current spreading layer to form a trench.

[0132] In an embodiment of the present application, after forming the first doping layer 140 and the second doping layer 150, the first doping layer 140 and the second doping layer 150 can be etched to the current spreading layer 130 to form a trench.

[0133] As a possible implementation, the trench includes a first-stage trench 610 and a second-stage trench 620. The second-stage trench 620 is located on the side of the first-stage trench 610 close to the first electrode 210, that is, the second-stage trench 620 is located below the first-stage trench 610. The first doping layer 140 and the second doping layer 150 can be etched to the current spreading layer 130 to form the first-stage trench 610 through a dry etching process, and then sidewalls are formed on the sidewalls of the first-stage trench 610 by depositing and etching silicon oxide. The position of the second-stage trench 620 is defined by the sidewalls, and the current spreading layer 130 is etched again with the sidewalls as a mask to form the second-stage trench 620, as shown in the reference Figure 15 shown.

[0134] S104, ion-implanting the bottom of the trench and a partial sidewall of the trench to form a bottom shielding layer; the bottom shielding layer extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is the direction perpendicular to the surface where the substrate is located; the bottom shielding layer is of the second conductivity type; along the second direction, the bottom shielding layer surrounds a partial sidewall of the trench, and the bottom shielding layer at least penetrates the current spreading layer and a partial thickness of the epitaxial layer.

[0135] In an embodiment of the present application, after forming the trench, ion implantation can be performed on the bottom of the trench and a part of the sidewalls of the trench to form the bottom shielding layer 410. The bottom shielding layer 410 extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is the direction perpendicular to the surface where the substrate 110 is located; the bottom shielding layer 410 is of a second conductivity type.

[0136] As a possible implementation, the trench includes a first-level trench 610 and a second-level trench 620. Ion implantation can be performed on the bottom of the second-level trench 620 and the sidewalls of the second-level trench 620 to form the bottom shielding layer 410, as shown in Figure 17 the figure. Ion implantation can also be simultaneously performed on the bottom of the first-level trench 610 and a part of the sidewalls of the first-level trench 610 to form the bottom shielding layer 410.

[0137] Specifically, silicon oxide 601 can be deposited in the trench, and the silicon oxide 601 can be etched to form an ion implantation mask on the sidewalls of the trench. Using this ion implantation mask as a mask, ion implantation is performed on the bottom of the trench and the sidewalls of the trench, as shown in Figure 16 the figure.

[0138] The bottom shielding layer 410 at least penetrates the current spreading layer 130 and a part of the thickness of the epitaxial layer 120, that is, the bottom shielding layer 410 is at least disposed in the current spreading layer 130 and the epitaxial layer 120. Along the second direction, the bottom shielding layer 410 surrounds a part of the sidewalls of the trench, that is, the bottom shielding layer 410 is not only disposed at the bottom of the trench along the second direction, but also surrounds a part of the sidewalls of the trench, so as to effectively improve the electric field concentration effect of the gate 310 at the trench corner by using the bottom shielding layer 410 on the trench sidewalls and the trench bottom, thereby further realizing the electric field shielding effect.

[0139] S105, forming a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extend along the second direction.

[0140] In an embodiment of the present application, after forming the trench, a gate dielectric layer 320 and a gate 310 are formed in the trench; the gate dielectric layer 320 and the gate 310 extend along the second direction.

[0141] As a possible implementation, the trench includes a first-level trench 610 and a second-level trench 620. The gate dielectric layer 320 is formed by a thermal oxidation process, and then polysilicon is deposited and etched to form the gate 310.

[0142] An interlayer dielectric layer 160 is deposited and etched on the gate 310, as shown in Figure 18 the figure.

[0143] S106, forming a first electrode on the side of the substrate away from the epitaxial layer, and forming a second electrode on the side of the second doping layer away from the substrate.

[0144] In the embodiment of the present application, a first electrode 210 is formed on a side of the substrate 110 away from the epitaxial layer 120, and a second electrode 220 is formed on a side of the second doping layer 150 away from the substrate 110. Figure 3 or Figure 4 shown.

[0145] Specifically, the first electrode 210 or the second electrode 220 is made of a material with good conductivity, such as a metal material. As an example, the first electrode 210 is a drain electrode, and the second electrode 220 is a source electrode.

[0146] Along the first direction, at least two edge shielding layers 420 are respectively arranged on both sides of the gate 310, and the distance between the edge shielding layer 420 and the gate 310 is greater than the distance threshold, that is, the distance between the edge shielding layer 420 and the gate 310 is relatively far, thereby avoiding the narrowing of the channel caused by the close distance. In other words, by arranging the edge shielding layer 420 on both sides of the gate 310 that does not contact the gate, further electric field shielding of the bottom and corners of the groove is achieved, that is, the groove is further protected.

[0147] The edge shielding layer 420 extends along the second direction, and the distance between the orthographic projections of the edge shielding layer 420 and the bottom shielding layer 410 in the first direction is greater than or equal to 0, that is, the orthographic projections of the edge shielding layer 420 and the bottom shielding layer 410 in the first direction do not overlap. In other words, when the edge shielding layer 420 extends in the second direction, it does not extend to the position where the bottom shielding layer 410 is located. The edge shielding layer 420 and the bottom shielding layer 410 do not exist on the same cross-section. Therefore, there is no serious JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, further improving the conduction characteristics of the device.

[0148] In the embodiment of the present application, both the edge shield layer 420 and the bottom shield layer 410 penetrate the current spreading layer 130 and a portion of the thickness of the epitaxial layer 120. Therefore, both the edge shield layer 420 and the bottom shield layer 410 include a first portion located in the epitaxial layer 120 and a second portion located in the current spreading layer 130. Along the first direction, the length of the first portion of the edge shield layer 420 located in the epitaxial layer 120 is greater than the length of the second portion of the edge shield layer 420 located in the current spreading layer 130. The length of the first portion of the bottom shield layer 410 located in the epitaxial layer 120 is greater than the length of the second portion of the bottom shield layer 410 located in the current spreading layer 130. Figure 3 or Figure 4As shown. That is to say, since the doping concentration of the current spreading layer 130 of the first conductivity type satisfies the high-concentration condition, when the edge shielding layer 420 and the bottom shielding layer 410 of the second conductivity type penetrate the current spreading layer 130, the lateral spreading effect on the current spreading layer 130 is small. That is, the high doping concentration of the current spreading layer 130 can weaken the lateral spreading caused by ion implantation scattering during the formation of the edge shielding layer 420 and the bottom shielding layer 410, thereby improving the JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, the first doping layer 140 and the bottom shielding layer 410, and improving the on-state characteristics of the device.

[0149] Based on the semiconductor device provided in the above embodiments, the embodiments of the present application further provide a manufacturing method of a semiconductor device. Refer to Figure 19 As shown, it is a schematic flow chart of another manufacturing method of a semiconductor device provided by the embodiments of the present application.

[0150] The manufacturing method of the semiconductor device provided by the embodiments of the present application includes the following steps:

[0151] S201, forming an epitaxial layer on a substrate, and performing ion implantation on the epitaxial layer to form an edge shielding layer in a first part of the epitaxial layer.

[0152] In the embodiments of the present application, the material of the substrate 110 may be a wide-bandgap semiconductor material, such as SiC, GaN, Ga2O3, C, or AlN. An epitaxial layer 120 may be formed on the substrate 110. Refer to Figure 20 As shown.

[0153] Specifically, the epitaxial layer 120 may be formed on the substrate 110 by an epitaxial process. The substrate 110 and the epitaxial layer 120 are of the first conductivity type.

[0154] After forming the epitaxial layer 120, ion implantation may be performed on the epitaxial layer 120 to form an edge shielding layer 420 in a first part of the epitaxial layer 120. Refer to Figure 21 As shown.

[0155] S202, forming a current spreading layer on the surface of the epitaxial layer; the doping concentration of the current spreading layer satisfies the high-concentration condition.

[0156] In the embodiments of the present application, after forming the edge shielding layer 420 in a first part of the epitaxial layer 120, a current spreading layer 130 is continuously formed on the surface of the epitaxial layer 120. Refer to Figure 22 As shown. The current spreading layer 130 may be formed on the surface of the epitaxial layer 110 by an epitaxial process.

[0157] In the embodiments of the present application, the substrate 110, the epitaxial layer 120, and the current spreading layer 130 are of the first conductivity type.

[0158] As an example, the first conductivity type is N-type, that is, the substrate 110 , the epitaxial layer 120 and the current spreading layer 130 are N-type.

[0159] The doping concentration of the current spreading layer 130 meets the high concentration condition, that is, the doping concentration of the current spreading layer 130 is relatively high. When ions are subsequently implanted into the current spreading layer 130 , ion lateral diffusion caused by ion implantation scattering can be weakened.

[0160] As a possible implementation, the high concentration condition is that the doping concentration of the current spreading layer 130 is greater than a concentration threshold. The concentration threshold is determined according to actual conditions. For example, the concentration threshold is 4e16cm -3 , the concentration threshold is the commonly used doping concentration of the current spreading layer included in the current MOSFET.

[0161] As another possible implementation method, the high concentration condition is that the doping concentration of the current spreading layer 130 is greater than the doping concentration of the epitaxial layer 120, that is, the doping concentration of the current spreading layer 130 is higher and the doping concentration of the epitaxial layer 120 is lower, thereby realizing that the epitaxial layer 120 is used as a voltage-resistant layer and the current spreading layer 130 is used as a film layer to weaken the ion injection scattering and transverse diffusion.

[0162] S203, ion implantation is performed on the current spreading layer to form a first doped layer, a second doped layer and an edge shielding layer located in the second part of the current spreading layer, wherein the substrate, the epitaxial layer, the current spreading layer and the second doped layer are of the first conductivity type, and the first doped layer and the edge shielding layer are of the second conductivity type.

[0163] In the embodiment of the present application, after the current spreading layer 130 is formed, ion implantation can be performed on the current spreading layer 130 to form a first doping layer 140, a second doping layer 150 and an edge shielding layer 420 located in the second portion of the current spreading layer 130, respectively. Figure 14 shown.

[0164] Specifically, the second doped layer 150 is of the first conductivity type, and the first doped layer 140 and the edge shielding layer 420 are of the second conductivity type; the edge shielding layer 420 is located between the epitaxial layer 120 and the second electrode 220 formed subsequently.

[0165] The first doping layer 140 and the second doping layer 150 may be sequentially formed by ion implantation into a portion of the thickness of the current spreading layer 130 .

[0166] When ion implantation is performed on the current spreading layer 130, an edge shielding layer 420 is also formed at the second portion of the current spreading layer 130. By first implanting ions into the epitaxial layer 120 to form the first portion of the edge shielding layer 420, and then forming the current spreading layer 130 and implanting ions into the current spreading layer 130 to form the second portion of the edge shielding layer 420, the morphology of the edge shielding layer 420 can be better controlled.

[0167] The edge shielding layer 420 penetrates the second doping layer 150, the first doping layer 140, the current spreading layer 130 and a portion of the thickness of the epitaxial layer 120. Figure 14 shown.

[0168] S204 , etching the first doping layer and the second doping layer to the current spreading layer to form a trench.

[0169] In the embodiment of the present application, after the first doping layer 140 and the second doping layer 150 are formed, the first doping layer 140 and the second doping layer 150 may be etched to the current spreading layer 130 to form a trench.

[0170] As a possible implementation, the trench includes a first-level trench 610 and a second-level trench 620. The second-level trench 620 is located on a side of the first-level trench 610 close to the first electrode 210, that is, the second-level trench 620 is located below the first-level trench 610. The first-level trench 610 can be formed by etching the first doped layer 140 and the second doped layer 150 to the current spreading layer 130 through a dry etching process. Then, silicon oxide is deposited and etched to form a sidewall on the sidewall of the first-level trench 610. The position of the second-level trench 620 is defined by the sidewall. The current spreading layer 130 is etched again using the sidewall as a mask to form the second-level trench 620. Figure 15 shown.

[0171] S205, ion implantation is performed on the bottom of the trench and part of the sidewalls of the trench to form a bottom shielding layer; the bottom shielding layer extends along a second direction, the second direction is perpendicular to a third direction, and the third direction is perpendicular to the surface direction of the substrate; the bottom shielding layer is of the second conductive type; along the second direction, the bottom shielding layer surrounds part of the sidewalls of the trench, and the bottom shielding layer at least penetrates the current spreading layer and part of the thickness of the epitaxial layer.

[0172] In an embodiment of the present application, after forming the trench, ion implantation may be performed on the trench bottom and portions of the trench sidewalls to form a bottom shielding layer 410. The bottom shielding layer 410 extends along a second direction, which is perpendicular to a third direction, which is perpendicular to the surface of the substrate 110. The bottom shielding layer 410 is of the second conductivity type.

[0173] As a possible implementation, the trench includes a first-level trench 610 and a second-level trench 620. Ion implantation can be performed on the bottom and sidewalls of the second-level trench 620 to form a bottom shielding layer 410. Refer to Figure 17 as shown. Ion implantation can also be simultaneously performed on the bottom and a partial sidewall of the first-level trench 610 to form the bottom shielding layer 410.

[0174] Specifically, silicon oxide 601 can be deposited in the trench, and the silicon oxide 601 can be etched to form an ion implantation mask on the sidewalls of the trench. Using this ion implantation mask as a mask, ion implantation is performed on the bottom and sidewalls of the trench. Refer to Figure 16 as shown.

[0175] The bottom shielding layer 410 at least penetrates the current spreading layer 130 and a partial thickness of the epitaxial layer 120, that is, the bottom shielding layer 410 is at least disposed in the current spreading layer 130 and the epitaxial layer 120. Along the second direction, the bottom shielding layer 410 surrounds a partial sidewall of the trench, that is, the bottom shielding layer 410 is not only disposed at the bottom of the trench along the second direction, but also surrounds a partial sidewall of the trench, so as to effectively improve the electric field aggregation effect of the gate 310 at the trench corner by using the bottom shielding layer 410 on the trench sidewall and the trench bottom, thereby further achieving the electric field shielding effect.

[0176] S206. A gate dielectric layer and a gate are formed in the trench; the gate dielectric layer and the gate extend along the second direction.

[0177] In the embodiment of the present application, after the trench is formed, a gate dielectric layer 320 and a gate 310 are formed in the trench; the gate dielectric layer 320 and the gate 310 extend along the second direction.

[0178] As a possible implementation, the trench includes a first-level trench 610 and a second-level trench 620. The gate dielectric layer 320 is formed by a thermal oxidation process, and then polysilicon is deposited and etched to form the gate 310.

[0179] An interlayer dielectric layer 160 is deposited and etched on the gate 310. Refer to Figure 18 as shown.

[0180] S207. A first electrode is formed on the side of the substrate away from the epitaxial layer, and a second electrode is formed on the side of the second doped layer away from the substrate.

[0181] In the embodiment of the present application, a first electrode 210 is formed on the side of the substrate 110 away from the epitaxial layer 120, and a second electrode 220 is formed on the side of the second doped layer 150 away from the substrate 110. Refer to Figure 3 or Figure 4 as shown.

[0182] Specifically, the first electrode 210 or the second electrode 220 is made of a material with good electrical conductivity, such as a metal material. As an example, the first electrode 210 is a drain electrode and the second electrode 220 is a source electrode.

[0183] Along the first direction, at least two edge shielding layers 420 are respectively disposed on both sides of the gate 310. The distance between the edge shielding layer 420 and the gate 310 is greater than a distance threshold, that is, the distance between the edge shielding layer 420 and the gate 310 is relatively far, avoiding the narrowing of the channel due to a relatively close distance. That is to say, by disposing edge shielding layers 420 that do not contact the gate on both sides of the gate 310, further electric field shielding of the trench bottom and corners is achieved, that is, the trench is further protected.

[0184] The edge shielding layer 420 extends along the second direction. The distance between the edge shielding layer 420 and the positive projection of the bottom shielding layer 410 in the first direction is greater than or equal to 0, that is, the positive projections of the edge shielding layer 420 and the bottom shielding layer 410 in the first direction do not overlap. That is to say, when the edge shielding layer 420 extends in the second direction, it will not extend to the position where the bottom shielding layer 410 is located. The edge shielding layer 420 and the bottom shielding layer 410 are not in the same cross-section. Therefore, there is no relatively serious JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, further improving the on-state characteristics of the device.

[0185] In the embodiment of the present application, both the edge shielding layer 420 and the bottom shielding layer 410 penetrate the current spreading layer 130 and a part of the thickness of the epitaxial layer 120. Therefore, both the edge shielding layer 420 and the bottom shielding layer 410 include a first part located in the epitaxial layer 120 and a second part located in the current spreading layer 130. Along the first direction, the length of the first part of the edge shielding layer 420 located in the epitaxial layer 120 is greater than the length of the second part of the edge shielding layer 420 located in the current spreading layer 130, and the length of the first part of the bottom shielding layer 410 located in the epitaxial layer 120 is greater than the length of the second part of the bottom shielding layer 410 located in the current spreading layer 130. Refer to Figure 3 or Figure 4 As shown. That is to say, since the doping concentration of the current spreading layer 130 of the first conductivity type satisfies the high-concentration condition, when the edge shielding layer 420 and the bottom shielding layer 410 of the second conductivity type penetrate the current spreading layer 130, the lateral expansion effect on the current spreading layer 130 is small. That is, the high doping concentration of the current spreading layer 130 can weaken the lateral expansion caused by ion implantation scattering during the formation of the edge shielding layer 420 and the bottom shielding layer 410, thereby improving the JFET effect between the edge shielding layer 420 and the bottom shielding layer 410, the first doping layer 140 and the bottom shielding layer 410, and improving the on-state characteristics of the device.

[0186] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for method embodiments, since they are basically similar to structural embodiments, they are described relatively simply, and for the relevant parts, reference can be made to the description of the structural embodiments.

[0187] The above description is only a preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes at least one metal-oxide-semiconductor field-effect transistor (MOSFET), and the MOSFET includes: A first electrode, a substrate, an epitaxial layer, a current spreading layer, a first doped layer, a second doped layer, and a second electrode stacked in sequence; the substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductivity type, and the first doped layer is of a second conductivity type; the doping concentration of the current spreading layer satisfies a high-concentration condition; A trench penetrating through the first doped layer and the second doped layer to the current spreading layer, the surface of the trench being covered by a gate dielectric layer, and the trench being filled with a gate; the gate dielectric layer and the gate extend along a second direction, the second direction being perpendicular to a third direction, and the third direction being perpendicular to the surface where the first electrode is located; A bottom shielding layer disposed on a side of the trench close to the first electrode, the bottom shielding layer extending along the second direction; the bottom shielding layer is of a second conductivity type; along the second direction, the bottom shielding layer surrounds a part of the sidewall of the trench, and the bottom shielding layer at least penetrates through the current spreading layer and a part of the thickness of the epitaxial layer; An edge shielding layer penetrates through the second doped layer, the first doped layer, the current spreading layer, and a part of the thickness of the epitaxial layer, the edge shielding layer extending along the second direction; the edge shielding layer is of a second conductivity type; along a first direction, at least two edge shielding layers are respectively disposed on two sides of the gate; the first direction is perpendicular to the second direction and the third direction; Along the first direction, the length of the edge shielding layer located in a first part of the epitaxial layer is greater than the length of the edge shielding layer located in a second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

2. The semiconductor device according to claim 1, wherein, Along the first direction, the distance between the edge shielding layer located in the first part of the epitaxial layer and the gate is less than the distance between the edge shielding layer located in the second part of the current spreading layer and the gate; Along the first direction, the bottom shielding layer extends from the first part of the epitaxial layer towards the edge shielding layer.

3. The semiconductor device according to claim 1, characterized in that, The trench includes a first-stage trench and a second-stage trench, and the second-stage trench is located on a side of the first-stage trench close to the first electrode; Along the first direction, the length of the second-stage trench is less than the length of the first-stage trench; The first-stage trench at least penetrates through the first doped layer and the second doped layer to the current spreading layer; The second-stage trench is located in the current spreading layer.

4. The semiconductor device according to claim 3, wherein, The bottom shielding layer is disposed on a side of the second-stage trench close to the first electrode; along the second direction, the bottom shielding layer surrounds the sidewall of the second-stage trench.

5. The semiconductor device according to claim 4, characterized in that, The bottom shielding layer surrounds the bottom of the first-stage trench and at least a part of the sidewall of the first-stage trench located in the current spreading layer and the first doped layer; Along the second direction, the length of the bottom shielding layer around at least a part of the sidewalls of the current spreading layer and the first doped layer located around the first-level trench is less than a length threshold.

6. The semiconductor device according to claim 5, wherein, Along the first direction, the bottom shielding layer is around one sidewall of the current spreading layer and the first doped layer located around the first-level trench.

7. The semiconductor device according to claim 5, wherein Along the first direction, the bottom shielding layer is around both sidewalls of the current spreading layer and the first doped layer located around the first-level trench.

8. The semiconductor device according to claim 4, wherein, The MOSFET includes a first shielding layer; the first shielding layer is of a second conductive type; the first shielding layer is located between the epitaxial layer and the second electrode, and the first shielding layer surrounds the gate dielectric layer in the first direction; the first shielding layer extends along the first direction, and along the second direction, the length of the first shielding layer is less than a length threshold.

9. The semiconductor device according to claim 8, wherein Along the first direction, the length of the first shielding layer is the same as the length of the epitaxial layer. Along the second direction, the length of the bottom shielding layer is the same as the length of the gate; along the first direction, the first shielding layer also surrounds the bottom shielding layer.

10. The semiconductor device according to any one of claims 1-9, characterized in that, Along the third direction, the sidewall of the trench is an inclined sidewall, and the side of the inclined sidewall away from the bottom shielding layer is inclined towards the edge shielding layer.

11. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming an epitaxial layer and a current spreading layer on a substrate in sequence. The doping concentration of the current spreading layer satisfies a high-concentration condition. Performing ion implantation on the current spreading layer and the epitaxial layer to respectively form a first doped layer, a second doped layer, and an edge shielding layer. The substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductive type, and the first doped layer and the edge shielding layer are of a second conductive type. Etching the first doped layer and the second doped layer to the current spreading layer to form a trench. Performing ion implantation on the bottom of the trench and a part of the sidewalls of the trench to form a bottom shielding layer; the bottom shielding layer extends along the second direction, the second direction is perpendicular to the third direction, and the third direction is the direction perpendicular to the surface where the substrate is located. The bottom shielding layer is of a second conductive type; along the second direction, the bottom shielding layer surrounds a part of the sidewalls of the trench, and the bottom shielding layer at least penetrates the current spreading layer and a part of the thickness of the epitaxial layer. Forming a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extend along the second direction. Forming a first electrode on the side of the substrate away from the epitaxial layer, and forming a second electrode on the side of the second doped layer away from the substrate. The edge shielding layer penetrates the second doped layer, the first doped layer, the current spreading layer, and a part of the thickness of the epitaxial layer, and the edge shielding layer extends along the second direction; along the first direction, at least two of the edge shielding layers are respectively disposed on both sides of the gate; the first direction is perpendicular to the second direction and the third direction. Along the first direction, the length of the edge shielding layer located in the first part of the epitaxial layer is greater than the length of the edge shielding layer located in the second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

12. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming an epitaxial layer on a substrate, performing ion implantation on the epitaxial layer to form an edge shielding layer in the first part of the epitaxial layer; Forming a current spreading layer on the surface of the epitaxial layer; The doping concentration of the current spreading layer satisfies a high-concentration condition; Performing ion implantation on the current spreading layer to respectively form a first doped layer, a second doped layer, and an edge shielding layer in the second part of the current spreading layer, wherein the substrate, the epitaxial layer, the current spreading layer, and the second doped layer are of a first conductivity type, and the first doped layer and the edge shielding layer are of a second conductivity type; Etching the first doped layer and the second doped layer to the current spreading layer to form a trench; Performing ion implantation on the bottom of the trench and a part of the sidewalls of the trench to form a bottom shielding layer; the bottom shielding layer extends along the second direction, the second direction is perpendicular to the third direction, and the third direction is the direction perpendicular to the surface where the substrate is located; The bottom shielding layer is of a second conductivity type; along the second direction, the bottom shielding layer surrounds a part of the sidewalls of the trench, and the bottom shielding layer at least penetrates through the current spreading layer and a part of the thickness of the epitaxial layer; Forming a gate dielectric layer and a gate in the trench; the gate dielectric layer and the gate extend along the second direction; Forming a first electrode on the side of the substrate away from the epitaxial layer, and forming a second electrode on the side of the second doped layer away from the substrate; The edge shielding layer penetrates through the second doped layer, the first doped layer, the current spreading layer, and a part of the thickness of the epitaxial layer, and the edge shielding layer extends along the second direction; along the first direction, at least two of the edge shielding layers are respectively arranged on both sides of the gate; the first direction is perpendicular to the second direction and the third direction; Along the first direction, the length of the edge shielding layer located in the first part of the epitaxial layer is greater than the length of the edge shielding layer located in the second part of the current spreading layer, and the length of the bottom shielding layer located in the first part of the epitaxial layer is greater than the length of the bottom shielding layer located in the second part of the current spreading layer.

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