Combined structure of semiconductor deep groove element and manufacturing method thereof
The formation of deep groove insulation and capacitive components through the same process step solves the problems of complex production and load effects in the prior art, and achieves the improvement of isolation voltage and capacitance value.
Patent Information
- Application Number
- CN202410108334.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2025-07-29
AI Technical Summary
The prior art cannot simultaneously form deep groove insulating elements and capacitance elements in the same process step, resulting in complex production process and serious load effects, and the inability to effectively increase the isolation voltage and capacitance value per unit area.
Using the etching, oxidation growth and deposition process steps, deep groove rings and deep groove round holes are formed through the same process steps, and polysilicon material is filled in the dielectric side wall layer, combined with deep groove ring units arranged in concentric multi-layers to form deep groove insulation and capacitive components.
The production steps are reduced, the load effect is reduced, and the isolation voltage and capacitance value per unit area are increased.
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Figure CN120390458A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a combined structure of semiconductor deep trench elements and a manufacturing method thereof, and particularly to a combined structure of semiconductor deep trench elements that can increase the isolation voltage and the capacitance value per unit area and a manufacturing method thereof. Background Art
[0002] Please refer to Figure 1 , which is a schematic diagram showing a known semiconductor deep trench element. Due to the requirements of their respective electrical parameters, the known semiconductor deep trench elements cannot share the same manufacturing process steps to be completed simultaneously. The general method can only complete the deep trench insulating element 101 or the capacitive element 102 respectively with different manufacturing process steps. Therefore, if two structures are to be formed, it is necessary to consume twice the number of photomasks and the manufacturing process, and it is necessary to consider whether the double manufacturing process causes a serious loading effect.
[0003] In view of this, the present invention provides a combined structure of semiconductor deep trench elements and a manufacturing method thereof, which can solve the above problems and increase the isolation voltage and the capacitance value per unit area. Summary of the Invention
[0004] In one aspect, the present invention provides a combined structure of semiconductor deep trench elements formed in a semiconductor substrate. The combined structure of the semiconductor deep trench elements includes: a deep trench insulating element surrounding a high voltage region and electrically insulating the high voltage region from the outside of the deep trench insulating element. The deep trench insulating element includes at least one deep trench ring unit. Each of the at least one deep trench ring units includes: a deep trench ring formed by etching the semiconductor substrate in a vertical direction in an etching process step, and the deep trench ring is polygonal when viewed from a top view; a first dielectric sidewall layer formed in and completely covering the bottom and side surfaces inside the deep trench ring in an oxidation growth process step; and a first polysilicon filling region formed by filling the internal space of the first dielectric sidewall layer with polysilicon material in a deposition process step; and a deep trench capacitor element including a plurality of deep trench capacitor units and a cathode. Each of the plurality of deep trench capacitor units includes: a deep trench round hole formed by etching the semiconductor substrate in a vertical direction in the same etching process step as the deep trench ring, and the deep trench round hole is circular when viewed from a top view; a second dielectric sidewall layer formed in and completely covering the bottom and side surfaces inside the deep trench round hole in the same oxidation growth process step as the first dielectric sidewall layer; a second polysilicon filling region formed by filling the internal space of the second dielectric sidewall layer with polysilicon material in the same deposition process step as the first polysilicon filling region; and an anode formed and connected on the second polysilicon filling region to be one of the positive electrode connection points of the deep trench capacitor element; wherein the cathode is formed on the semiconductor substrate outside the plurality of deep trench capacitor units to be the negative electrode connection point of the deep trench capacitor element.
[0005] In one embodiment, the arrangement of the plurality of deep trench capacitor units when viewed from a top view is a projection of body-centered cubic packing on a horizontal plane, a projection of face-centered cubic packing on a horizontal plane, or a projection of hexagonal close packing on a horizontal plane.
[0006] In one embodiment, the number of the at least one deep trench ring unit is plural, and it is concentric multi-layer arranged when viewed from a top view.
[0007] In one embodiment, the deep trench capacitor element further includes a first N-type well region formed in the semiconductor substrate. The first N-type well region is electrically connected to the cathode and is connected to the outside of the second dielectric sidewall layer of each of the plurality of deep trench capacitor units.
[0008] In one embodiment, the deep trench capacitor element further includes a first N-type buried region formed below the first N-type well region in the semiconductor substrate. The first N-type buried region is electrically connected to the first N-type well region and is connected to the outside of the second dielectric sidewall layer of each of the plurality of deep trench capacitor units.
[0009] In one embodiment, the deep trench capacitor unit further includes a first shallow trench isolation region formed at the uppermost end outside the deep trench round hole.
[0010] In one embodiment, the deep trench isolation element further includes a second N-type well region formed in the semiconductor substrate, and the second N-type well region surrounds the outside of the at least one deep trench ring unit.
[0011] In one embodiment, the deep trench isolation element further includes a second N-type buried region formed below the second N-type well region in the semiconductor substrate, and the second N-type buried region surrounds the outside of the at least one deep trench ring unit.
[0012] In one embodiment, the deep trench ring unit further includes two second shallow trench isolation regions respectively formed at the uppermost ends outside both sides of the deep trench ring.
[0013] In another aspect, the present invention provides a manufacturing method of a combined structure of a semiconductor deep trench element, including: in an etching process step, etching a semiconductor substrate in a vertical direction to simultaneously form a deep trench ring and a deep trench round hole, wherein the deep trench ring is polygonal when viewed from a top view, and the deep trench round hole is circular when viewed from a top view; in an oxidation growth process step, simultaneously forming a first dielectric sidewall layer and a second dielectric sidewall layer, wherein the first dielectric sidewall layer is formed on and completely covers the bottom surface and side surface inside the deep trench ring, and the second dielectric sidewall layer is formed on and completely covers the bottom surface and side surface inside the deep trench round hole; in a deposition process step, filling the internal space of the first dielectric sidewall layer with a polysilicon material to form a first polysilicon filling region, and filling the internal space of the second dielectric sidewall layer with a polysilicon material to form a second polysilicon filling region; and forming an anode and connecting it to the second polysilicon filling region; wherein, the deep trench ring, the first dielectric sidewall layer and the first polysilicon filling region form a deep trench ring unit, and at least one of the deep trench ring units constitutes a deep trench isolation element; wherein the deep trench isolation element surrounds a high voltage region and electrically insulates the high voltage region from the outside of the deep trench isolation element; wherein the deep trench round hole, the second dielectric sidewall layer, the second polysilicon filling region and the anode form a deep trench capacitor unit, and a plurality of the deep trench capacitor units and a cathode form a deep trench capacitor element; wherein the anode is used as one of the positive electrode connection points of the deep trench capacitor element; wherein the cathode is formed on the semiconductor substrate outside the plurality of deep trench capacitor units and is used as the negative electrode connection point of the deep trench capacitor element.
[0014] In one embodiment, the manufacturing method further includes: simultaneously forming a first N-type well region and a second N-type well region in the same manufacturing step; wherein the first N-type well region is formed in the semiconductor substrate, the first N-type well region is electrically connected to the cathode, and is externally connected to the second dielectric sidewall layer of each of the plurality of deep trench capacitor units; wherein the second N-type well region is formed in the semiconductor substrate, and the second N-type well region surrounds the outside of at least one of the deep trench ring units.
[0015] In one embodiment, the manufacturing method further includes: simultaneously forming a first N-type buried region and a second N-type buried region in the same manufacturing step; wherein the first N-type buried region is formed below the first N-type well region in the semiconductor substrate, is electrically connected to the first N-type well region, and the first N-type buried region is externally connected to the second dielectric sidewall layer of each of the plurality of deep trench capacitor units; wherein the second N-type buried region is formed below the second N-type well region in the semiconductor substrate, and the second N-type buried region surrounds the outside of at least one of the deep trench ring units.
[0016] In one embodiment, the manufacturing method further includes: simultaneously forming a first shallow trench isolation region and two second shallow trench isolation regions in the same manufacturing step; wherein the first shallow trench isolation region is formed at the uppermost end outside the deep trench round hole; wherein the two second shallow trench isolation regions are respectively formed at the uppermost ends outside the two sides of the deep trench ring.
[0017] In one embodiment, the manufacturing method further includes: in a chemical mechanical polishing manufacturing step, after the first polysilicon filling region and the second polysilicon filling region are formed, planarizing an upper surface of the semiconductor substrate.
[0018] In one embodiment, the manufacturing method further includes: in a chemical mechanical polishing manufacturing step, after the first shallow trench isolation region and the two second shallow trench isolation regions are formed, planarizing an upper surface of the semiconductor substrate.
[0019] The advantages of the present invention are that the present invention can achieve the effects of reducing the manufacturing steps by half and reducing the loading effect, increasing the isolation voltage, and increasing the capacitance value per unit area.
[0020] The following is described in detail through specific embodiments to more easily understand the purpose, technical content, features, and achieved effects of the present invention. Description of the Drawings
[0021] Figure 1 is a schematic diagram showing a known semiconductor deep trench element.
[0022] Figure 2A is a top view schematic diagram of a deep trench insulating element showing a combined structure of a semiconductor deep trench element according to an embodiment of the present invention.
[0023] Figure 2BIt is a top view schematic diagram of a deep trench capacitor element showing the combined structure of semiconductor deep trench elements according to another embodiment of the present invention.
[0024] Figure 2C It is a cross-sectional schematic diagram showing the combined structure of semiconductor deep trench elements according to an embodiment of the present invention.
[0025] Figure 3 It is a top view schematic diagram of a deep trench insulating element showing the combined structure of semiconductor deep trench elements according to another embodiment of the present invention.
[0026] Figure 4A It is a top view schematic diagram of a deep trench capacitor element showing the combined structure of semiconductor deep trench elements according to another embodiment of the present invention.
[0027] Figure 4B It is a top view schematic diagram of a deep trench capacitor element showing the combined structure of semiconductor deep trench elements according to still another embodiment of the present invention.
[0028] Figure 4C It is a top view schematic diagram of a deep trench capacitor element showing the combined structure of semiconductor deep trench elements according to yet another embodiment of the present invention.
[0029] Figure 5 It is a step flow schematic diagram of a manufacturing method showing the combined structure of semiconductor deep trench elements according to an embodiment of the present invention.
[0030] Figure 6A - Figure 6K It is a cross-sectional schematic diagram of a manufacturing method showing the combined structure of semiconductor deep trench elements according to an embodiment of the present invention.
[0031] Symbol Explanation in the Figures
[0032] 101: Deep trench insulating element
[0033] 102: Capacitor element
[0034] 20: Combined structure of semiconductor deep trench elements
[0035] 200a: Deep trench ring unit
[0036] 200b: Deep trench capacitor unit
[0037] 201: Semiconductor substrate
[0038] 202: P-type epitaxial layer
[0039] 203a, 203b: N-type well regions
[0040] 204a, 204b: N-type buried regions
[0041] 205a, 205b: Dielectric sidewall layers
[0042] 206a, 206b: Polysilicon filling regions
[0043] 207, 207a, 207b: Shallow trench isolation regions
[0044] 208a, 208b: Anodes
[0045] 209a, 209b: Cathodes
[0046] 210: High-voltage region
[0047] 211a: Deep trench ring
[0048] 211b: Deep trench round hole
[0049] 30: Deep trench isolation element
[0050] 40: Deep trench capacitor element
[0051] 50: Manufacturing method of a combined structure of semiconductor deep trench elements
[0052] 501 - 518: Steps Detailed implementation manners
[0053] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are all schematic, mainly intended to show the process steps and the up-and-down order relationship between layers, and the shapes, thicknesses, and widths are not drawn to scale.
[0054] Figure 2A is a top view schematic diagram of a deep trench isolation element of a combined structure of semiconductor deep trench elements according to an embodiment of the present invention. As Figure 2A shown, the number of at least one deep trench ring unit is multiple, and it is viewed as concentric multi-layer arrangement from the top view. Figure 3 is a top view schematic diagram of a deep trench isolation element of a combined structure of semiconductor deep trench elements according to another embodiment of the present invention. In one embodiment, as Figure 2A or Figure 3 shown, the deep trench ring is viewed as a polygonal ring from the top view. Figure 2B is a top view schematic diagram of a deep trench capacitor element of a combined structure of semiconductor deep trench elements according to another embodiment of the present invention. As Figure 2B shown, the deep trench capacitor element has multiple deep trench round holes; among them, the deep trench round holes are viewed as circular from the top view.
[0055] Figure 2C is a cross-sectional schematic diagram of a combined structure of semiconductor deep trench elements according to an embodiment of the present invention. As Figure 2CAs shown, the combined structure 20 of the semiconductor deep trench element of the present invention is formed in the semiconductor substrate 201. The combined structure 20 of the semiconductor deep trench element includes a deep trench insulating element 30 and a deep trench capacitive element 40. As Figure 2A shown, the deep trench insulating element 30 surrounds the high voltage region 210, and electrically insulates the high voltage region 210 enclosed inside the deep trench insulating element 30 from the outside of the deep trench insulating element 30. Referring again to Figure 2C , the deep trench insulating element 30 includes at least one deep trench ring unit 200a. Each of the at least one deep trench ring unit 200a includes a deep trench ring 211a, a dielectric sidewall layer 205a, and a polysilicon filling region 206a.
[0056] The deep trench ring 211a is formed by etching the semiconductor substrate 201 in the vertical direction by, for example but not limited to, an etching process step. The dielectric sidewall layer 205a is formed by, for example but not limited to, an oxidation growth process step on and completely covering the bottom surface and side surface inside the deep trench ring 211a. The polysilicon filling region 206a is formed by, for example but not limited to, a deposition process step of filling the internal space of the dielectric sidewall layer 205a with a polysilicon material. The deep trench insulating element 30 further includes an N-type well region 203a, which is formed in the semiconductor substrate 201. The N-type well region 203a surrounds the outside of the at least one deep trench ring unit 200a. The deep trench insulating element 30 further includes an N-type buried region 204a, which is formed below the N-type well region 203a in the semiconductor substrate 201. The N-type buried region 204a surrounds the outside of the at least one deep trench ring unit 200a. The deep trench ring unit 200a further includes two shallow trench insulating regions 207a, which are respectively formed at the uppermost ends outside both sides of the deep trench ring 211a.
[0057] As Figure 2C shown, the deep trench capacitive element 40 includes a plurality of deep trench capacitive units 200b and a cathode 209. Each of the plurality of deep trench capacitive units 200b includes a deep trench round hole 211b, a dielectric sidewall layer 205b, and a polysilicon filling region 206b. The deep trench round hole 211b and the deep trench ring 211a are formed by etching the semiconductor substrate 201 in the vertical direction by the same etching process step at the same time. As Figure 2B shown, the deep trench round hole 211b is circular when viewed from a top view. Referring again to Figure 2C , the dielectric sidewall layer 205b and the dielectric sidewall layer 205a are formed by the same oxidation growth process step at the same time on and completely covering the bottom surface and side surface inside the deep trench round hole 211b.
[0058] The polysilicon filling region 206b and the polysilicon filling region 206a are formed simultaneously in the same deposition process step by filling the internal space of the dielectric sidewall layer 205b with a polysilicon material. The anode 208b is formed and connected to the polysilicon filling region 206b to serve as one of the positive electrode connection points of the deep trench capacitor element 40. The cathode 209b is formed on the semiconductor substrate 201 outside the plurality of deep trench capacitor cells 200b to serve as the negative electrode connection point of the deep trench capacitor element 40. The deep trench capacitor element 40 further includes an N-type well region 203b, which is formed in the semiconductor substrate 201. The N-type well region 203b is electrically connected to the cathode 209b and is connected to the outside of the dielectric sidewall layer 205b of each of the plurality of deep trench capacitor cells 200b. The deep trench capacitor element 40 further includes an N-type buried region 204b, which is formed below the N-type well region 203b in the semiconductor substrate 201. The N-type buried region 204b is electrically connected to the N-type well region 203b and is connected to the outside of the dielectric sidewall layer 205b of each of the plurality of deep trench capacitor cells 200b. The deep trench capacitor cell 200b further includes a shallow trench isolation region 207b, which is formed at the uppermost end outside the deep trench round hole 211b.
[0059] Figure 4A is a top view schematic diagram of a deep trench capacitor element showing a combined structure of semiconductor deep trench elements according to another embodiment of the present invention. As Figure 4A shown, in one embodiment, the plurality of deep trench capacitor cells 200b are arranged in a body-centered cubic packing as viewed from the top view, which is a projection on a horizontal plane. Figure 4B is a top view schematic diagram of a deep trench capacitor element showing a combined structure of semiconductor deep trench elements according to yet another embodiment of the present invention. As Figure 4B shown, in another embodiment, the plurality of deep trench capacitor cells 200b are arranged in a face-centered cubic packing as viewed from the top view, which is a projection on a horizontal plane. Figure 4C is a top view schematic diagram of a deep trench capacitor element showing a combined structure of semiconductor deep trench elements according to still another embodiment of the present invention. As Figure 4C shown, in yet another embodiment, the plurality of deep trench capacitor cells 200b are arranged in a hexagonal close packing as viewed from the top view, which is a projection on a horizontal plane. By the above various arrangement methods, the capacitance value per unit area of the trench capacitor can be increased.
[0060] Figure 5 is a step flow schematic diagram of a manufacturing method of a combined structure of semiconductor deep trench elements according to an embodiment of the present invention. Figure 6A - Figure 6K is a cross-sectional schematic diagram of a manufacturing method of a combined structure of semiconductor deep trench elements according to an embodiment of the present invention. As Figure 5 and Figure 6AAs shown, the manufacturing method 50 of the combined structure of the semiconductor deep trench element of the present invention includes, in step 501, forming a photomask for the N-type buried regions 204a and 204b. Then, in step 502, N-type ions are implanted to simultaneously form the N-type buried regions 204a and 204b. After that, as Figure 5 and Figure 6B shown, in step 503, a P-type epitaxial layer 202 is formed. Then, as Figure 5 and Figure 6C shown, in step 504, a photomask for the N-type well regions 203a and 203b is formed. Subsequently, in step 505, N-type ions are implanted to simultaneously form the N-type well regions 203a and 203b.
[0061] After that, as Figure 5 and Figure 6D shown, in step 506, a photomask for the deep trench rings 211a and the deep trench round holes 211b is formed. Then, in step 507, the semiconductor substrate is etched in the vertical direction by an etching process step to simultaneously form the deep trench rings 211a and the deep trench round holes 211b. After that, as Figure 5 and Figure 6E shown, in step 508, dielectric sidewall layers 205a and 205b are simultaneously formed by an oxidation growth process step. Subsequently, as Figure 5 and Figure 6F shown, in step 509, the internal spaces of the dielectric sidewall layer 205a and the internal space of the dielectric sidewall layer 205b are simultaneously filled with a polysilicon material by a deposition process step to simultaneously form polysilicon filling regions 206a and 206b. Then, as Figure 5 and Figure 6G shown, in step 510, the upper surface of the semiconductor substrate 201 is planarized by a chemical mechanical polishing process step. After that, as Figure 5 and Figure 6H shown, in step 511, a photomask for the shallow trench isolation regions 207a and 207b is formed. Subsequently, in step 512, grooves for the shallow trench isolation regions 207a and 207b are simultaneously formed by an etching step. Then, as Figure 5 and Figure 6I shown, in step 513, the shallow trench isolation region 207 is simultaneously formed by a deposition process step.
[0062] After that, as Figure 5 and Figure 6J shown, in step 514, the upper surface of the semiconductor substrate 201 is planarized by a chemical mechanical polishing process step to simultaneously form the shallow trench isolation regions 207a and 207b. Subsequently, as Figure 5 and Figure 6KAs shown, in step 515, a photomask for anodes 208a, 208b and cathodes 209a, 209b is formed. Then, in step 516, anodes 208a, 208b and cathodes 209a, 209b are simultaneously formed by a deposition process step such that anode 208b is connected to the polysilicon filling region 206b. Thereafter, in step 517, the upper surface of the semiconductor substrate is planarized by a chemical mechanical polishing process step to form anodes 208a, 208b and cathodes 209a, 209b. Subsequently, in step 518, the photomask for anodes 208a, 208b and cathodes 209a, 209b is removed.
[0063] In summary, the present invention can simultaneously fabricate the deep trench insulating element 30 and the deep trench capacitive element 40, so that the manufacturing steps can be reduced by half and the loading effect can be reduced. Moreover, since the present invention adopts the concentric multi-layer arranged deep trench ring units, the isolation voltage can be increased. Furthermore, the arrangement mode of the deep trench capacitive units of the present invention can increase the capacitance value per unit area.
[0064] The present invention has been described with respect to the preferred embodiments above. However, the above description is only for facilitating the understanding of the content of the present invention by those skilled in the art, and is not used to limit the scope of the rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the components; another example is that the lithography technology is not limited to the photomask technology and can also include electron beam lithography technology. All of these can be obtained by analogy according to the teachings of the present invention. In addition, the described embodiments are not limited to being applied alone and can also be combined, for example but not limited to using two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any implementation form of the present invention does not necessarily achieve all the purposes or advantages, and therefore, any item of the claimed rights should not be limited thereto.
Claims
1. A combined structure of semiconductor deep trench elements, formed in a semiconductor substrate, the combined structure of the semiconductor deep trench elements comprising: A deep trench insulating element surrounding a high voltage region and electrically insulating the high voltage region from the outside of the deep trench insulating element, wherein the deep trench insulating element includes at least one deep trench ring unit, and each of the at least one deep trench ring unit includes: A deep trench ring formed by etching the semiconductor substrate vertically in an etching process step, and the deep trench ring is polygonal when viewed from a top view; A first dielectric sidewall layer formed in and completely covering the bottom and side surfaces inside the deep trench ring in an oxidation growth process step; and A first polysilicon filling region formed by filling the internal space of the first dielectric sidewall layer with polysilicon material in a deposition process step; And A deep trench capacitor element including a plurality of deep trench capacitor units and a cathode, and each of the plurality of deep trench capacitor units includes: A deep trench round hole formed by etching the semiconductor substrate vertically in the same etching process step as the deep trench ring, and the deep trench round hole is circular when viewed from a top view; A second dielectric sidewall layer formed in and completely covering the bottom and side surfaces inside the deep trench round hole in the same oxidation growth process step as the first dielectric sidewall layer; A second polysilicon filling region formed by filling the internal space of the second dielectric sidewall layer with polysilicon material in the same deposition process step as the first polysilicon filling region; and An anode formed and connected on the second polysilicon filling region for serving as one of the positive electrode connection points of the deep trench capacitor element; Wherein, the cathode is formed on the semiconductor substrate outside the plurality of deep trench capacitor units for serving as the negative electrode connection point of the deep trench capacitor element.
2. The combined structure of the semiconductor deep trench element as described in claim 1, wherein, The arrangement of the plurality of deep trench capacitor units when viewed from a top view is the projection of body-centered cubic packing on a horizontal plane, the projection of face-centered cubic packing on a horizontal plane, or the projection of hexagonal close packing on a horizontal plane.
3. The combined structure of the semiconductor deep trench element as described in claim 1, wherein, The number of the at least one deep trench ring unit is plural, and is concentric multi-layer arranged when viewed from a top view.
4. The combined structure of the semiconductor deep trench element as described in claim 1, wherein, The deep trench capacitor element further includes a first N-type well region formed in the semiconductor substrate, the first N-type well region is electrically connected to the cathode and is connected to the outside of the second dielectric sidewall layer of each of the plurality of deep trench capacitor units.
5. The combined structure of the semiconductor deep trench element as described in claim 4, wherein, The deep trench capacitor element further includes a first N-type buried region formed below the first N-type well region in the semiconductor substrate, the first N-type buried region is electrically connected to the first N-type well region and is connected to the outside of the second dielectric sidewall layer of each of the plurality of deep trench capacitor units.
6. The combined structure of the semiconductor deep trench element as described in claim 1, wherein, The deep trench capacitor unit further includes a first shallow trench insulation region formed at the uppermost end outside the deep trench round hole.
7. The combined structure of the semiconductor deep trench element as described in claim 1, wherein, The deep trench insulating element further includes a second N-type well region formed in the semiconductor substrate, and the second N-type well region surrounds the outside of the at least one deep trench ring unit.
8. The combined structure of the semiconductor deep trench element according to claim 7, wherein, The deep trench insulating element further includes a second N-type buried region formed below the second N-type well region in the semiconductor substrate, and the second N-type buried region surrounds the outside of the at least one deep trench ring unit.
9. The combined structure of the semiconductor deep trench element according to claim 1, wherein, The deep trench ring unit further includes two second shallow trench insulation regions respectively formed at the uppermost ends outside both sides of the deep trench ring.
10. A manufacturing method of a combined structure of a semiconductor deep trench element, comprising: In an etching process step, etching a semiconductor substrate in a vertical direction to simultaneously form a deep trench ring and a deep trench round hole, wherein the deep trench ring is polygonal as viewed from a top view, and the deep trench round hole is circular as viewed from a top view; In an oxidation growth process step, simultaneously forming a first dielectric sidewall layer and a second dielectric sidewall layer, wherein the first dielectric sidewall layer is formed on and completely covers the bottom surface and side surface inside the deep trench ring, and the second dielectric sidewall layer is formed on and completely covers the bottom surface and side surface inside the deep trench round hole; In a deposition process step, filling the internal space of the first dielectric sidewall layer with polysilicon material to form a first polysilicon filling area, and filling the internal space of the second dielectric sidewall layer with polysilicon material to form a second polysilicon filling area; and Forming an anode and connecting it to the second polysilicon filling area; Among them, The deep trench ring, the first dielectric sidewall layer and the first polysilicon filling area form a deep trench ring unit, and at least one of the deep trench ring units constitutes a deep trench insulating element; Wherein the deep trench insulating element surrounds a high voltage area and electrically insulates the high voltage area from the outside of the deep trench insulating element; Wherein the deep trench round hole, the second dielectric sidewall layer, the second polysilicon filling area and the anode form a deep trench capacitor unit, and a plurality of the deep trench capacitor units and a cathode form a deep trench capacitor element; Wherein the anode is used as one of the positive electrode connection points of the deep trench capacitor element; Wherein the cathode is formed on the semiconductor substrate outside a plurality of the deep trench capacitor units and is used as the negative electrode connection point of the deep trench capacitor element.
11. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 10, wherein, The plurality of the deep trench capacitor units are arranged in a body-centered cubic packing projection on a horizontal plane, a face-centered cubic packing projection on a horizontal plane or a hexagonal closest packing projection on a horizontal plane as viewed from a top view.
12. The manufacturing method of the combined structure of the semiconductor deep trench element as described in claim 10, wherein, The number of at least one of the deep trench ring units is multiple, and is arranged in a concentric multi-layer arrangement as viewed from a top view.
13. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 10, wherein, Further comprising: Simultaneously forming a first N-type well region and a second N-type well region in the same process step; Wherein the first N-type well region is formed in the semiconductor substrate, the first N-type well region is electrically connected to the cathode, and is externally connected to the second dielectric sidewall layer of each of the plurality of the deep trench capacitor units; Wherein the second N-type well region is formed in the semiconductor substrate, and the second N-type well region surrounds the outside of at least one of the deep trench ring units.
14. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 13, wherein, Further comprising: Simultaneously forming a first N-type buried region and a second N-type buried region in the same process step; Wherein the first N-type buried region is formed below the first N-type well region in the semiconductor substrate, is electrically connected to the first N-type well region, and is externally connected to the second dielectric sidewall layer of each of the plurality of the deep trench capacitor units; Wherein the second N-type buried region is formed below the second N-type well region in the semiconductor substrate, and the second N-type buried region surrounds the outside of at least one of the deep trench ring units.
15. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 10, wherein, Further comprising: Simultaneously forming a first shallow trench insulation region and two second shallow trench insulation regions in the same process step; Wherein the first shallow trench insulation region is formed at the uppermost end outside the deep trench round hole; Wherein the two second shallow trench isolation regions are respectively formed at the uppermost ends outside both sides of the deep trench ring.
16. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 10, wherein, Further comprising: After the first polysilicon filling region and the second polysilicon filling region are formed, planarize an upper surface of the semiconductor substrate by a chemical mechanical polishing process step.
17. The manufacturing method of the combined structure of the semiconductor deep trench element according to claim 15, wherein, Further comprising: After the first shallow trench isolation region and the two second shallow trench isolation regions are formed, planarize an upper surface of the semiconductor substrate by a chemical mechanical polishing process step.