Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method of the display panel, the display panel comprises a driving circuit layer, flat layers and an anode layer, the flat layers comprise a first flat layer and a second flat layer, the first flat layer is provided with a first hole, the second flat layer is provided with a second hole, the second hole and the first hole are arranged in an aligned manner, and the anode layer is arranged between the first hole and the second hole. The second flat layer at least partially covers the hole wall of the first hole, the bottom of the hole wall of the first hole is provided with a first slope angle, and the slope of the hole wall of the first hole is reduced by limiting the first slope angle within 40 degrees, so that the stress borne by the second flat layer at the first hole is reduced; therefore, the risk that the second flat layer cracks at the first hole can be reduced, the risk that the anode cracks at the first hole and the second hole can be reduced, and the production yield of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Art

[0002] Display panels that use non-polarizer technology have higher requirements for the flatness of the anode layer. Before forming the anode layer, a new flat layer is added on top of the existing flat layer to improve the flatness below the anode layer. Compared to traditional display panels, the anode layer of display panels that use non-polarizer technology must pass through at least two flat layers before it can be electrically connected to the metal layer below the anode layer. Usually, a sleeve hole that passes through at least two flat layers is set below the anode layer, and part of the anode layer passes through the sleeve hole and is electrically connected to the metal layer.

[0003] Due to the thick thickness of the two flat layers, the step difference between the anode layer and the metal layer is too large, and the stress between different flat layers is not matched. The sleeve hole passing through the two flat layers is prone to cracking, causing cracks in the anode layer attached to the inner wall of the sleeve hole, resulting in a reduced production yield of the display panel.

[0004] Therefore, it is necessary to provide a display panel and a method for manufacturing the display panel to improve this defect. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a method for manufacturing the display panel, which can reduce the risk of cracks in the planar layer and the anode layer.

[0006] In order to achieve the above-mentioned objective, according to a first aspect of the present application, a display panel is provided, comprising:

[0007] A driving circuit layer, including a pixel driving circuit;

[0008] a flat layer disposed on the driving circuit layer, the flat layer comprising a first flat layer and a second flat layer disposed on the first flat layer, the first flat layer being provided with a first hole, the second flat layer being provided with a second hole, the second hole being aligned with the first hole;

[0009] an anode layer, disposed on the second flat layer, the anode layer comprising an anode, the anode being electrically connected to the pixel driving circuit through the second hole and the first hole in sequence;

[0010] The bottom of the hole wall of the first hole has a first slope angle, the first slope angle is greater than 0 degree and less than or equal to 40 degrees, and the second flat layer at least partially covers the hole wall of the first hole.

[0011] Optionally, the orthographic projection of the second hole on the driving circuit layer is within the orthographic projection range of the first hole on the driving circuit layer, and the second flat layer completely covers the hole wall of the first hole.

[0012] Optionally, there is a first distance in the horizontal direction between the bottom of the hole wall of the first hole and the bottom of the hole wall of the second hole. The first flat layer has a first thickness, and the ratio of the first thickness to the first distance is greater than or equal to 2 / 3 and less than or equal to 2.

[0013] Optionally, the first flat layer has a first thickness, and the first thickness is greater than or equal to 1 micron and less than or equal to 3 microns;

[0014] There is a first distance between the bottom of the hole wall of the first hole and the bottom of the hole wall of the second hole. The first distance is greater than or equal to 1 micron and less than or equal to 5 microns.

[0015] Optionally, the first slope angle is greater than or equal to 20 degrees.

[0016] Optionally, the bottom of the hole wall of the second hole has a second slope angle, and the second slope angle is greater than or equal to 40 degrees and less than or equal to 70 degrees.

[0017] Optionally, the thickness of the second flat layer is greater than or equal to 2 microns and less than or equal to 3 microns.

[0018] Optionally, the flat layer further includes a third flat layer, and the third flat layer is disposed on a side of the first flat layer away from the second flat layer;

[0019] Wherein, the display panel further includes a connection layer, the connection layer is disposed between the first flat layer and the third flat layer, the connection layer includes a connection portion, and the anode is electrically connected to the pixel driving circuit through the second hole, the first hole, and the connection portion penetrating through the third flat layer in sequence.

[0020] According to a second aspect of the present application, there is provided a method for manufacturing a display panel, and the method for manufacturing the display panel includes:

[0021] Form a driving circuit layer, and the driving circuit layer includes a pixel driving circuit;

[0022] Form a layer of first flat material on the driving circuit layer;

[0023] Perform patterning on the first flat material to form a first hole and obtain a first flat layer;

[0024] Form a layer of second flat material on the first flat layer;

[0025] Pattern the second flat material to form a second hole and obtain a second flat layer;

[0026] Form an anode layer on the second flat layer, the anode layer including an anode;

[0027] Wherein, the second hole is arranged in alignment with the first hole, the bottom of the hole wall of the first hole has a first slope angle, the first slope angle is greater than 0 degrees and less than or equal to 40 degrees, the second flat layer at least partially covers the hole wall of the first hole, and the anode is electrically connected to the pixel driving circuit through the second hole.

[0028] Optionally, the step of patterning the first flat material to form a first hole and obtain a first flat layer includes:

[0029] Pattern the first flat material to form a third hole and a reserved portion connected to the inner wall of the third hole;

[0030] Heat the first flat material to cause the reserved portion to flow towards the center of the third hole to form the first hole.

[0031] Optionally, the step of patterning the first flat material to form a third hole and a reserved portion connected to the inner wall of the third hole includes:

[0032] Cover a photomask above the first flat material, the photomask having a first light-transmitting region, a first non-light-transmitting region, and a second light-transmitting region, the first non-light-transmitting region surrounding the second light-transmitting region, and the first light-transmitting region surrounding the first non-light-transmitting region;

[0033] Expose the first flat material, the width of the first light-transmitting region being less than the exposure accuracy;

[0034] Develop the first flat material, a portion of the first flat material corresponding to the second light-transmitting region forming the third hole, and a portion of the first flat material corresponding to the first non-light-transmitting region forming the reserved portion.

[0035] In the display panel according to the embodiment of the present application, the display panel includes a driving circuit layer, a flat layer, and an anode layer. The flat layer includes a first flat layer and a second flat layer. The first flat layer is provided with a first hole, the second flat layer is provided with a second hole, the second hole is arranged in alignment with the first hole, the second flat layer at least partially covers the hole wall of the first hole, and the bottom of the hole wall of the first hole has a first slope angle. By limiting the first slope angle within 40 degrees, the slope of the hole wall of the first hole is reduced, thereby reducing the stress on the second flat layer at the first hole, so that the risk of cracking of the second flat layer at the first hole can be reduced, and thus the risk of cracking of the anode at the first hole and the second hole can be reduced, and further the production yield of the display panel can be improved.

[0036] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0038] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0039] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0040] Figure 2 for Figure 1 An enlarged schematic diagram of the dotted box in FIG.

[0041] Figure 3 A top view of a first hole and a second hole in a display panel provided in an embodiment of the present application;

[0042] Figure 4 A flowchart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0043] Figures 5a to 5e A schematic diagram of a method for manufacturing a display panel provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a photomask used in a method for manufacturing a display panel according to an embodiment of the present application;

[0045] Figure 7 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0046] Figure 8 for Figure 7 An enlarged schematic diagram of the dotted box in FIG.

[0047] Figure 9 This is an enlarged schematic diagram of the display panel at the second hole V2 in Example 1;

[0048] Figure 10 is a cross-sectional view of the display panel at the second hole V2 in Comparative Example 1;

[0049] Figure 11 A schematic diagram of a display device provided in an embodiment of the present application. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0051] An embodiment of the present application provides a display panel. The display panel includes a driving circuit layer, a planarization layer, and an anode layer. The driving circuit layer includes a pixel driving circuit. The planarization layer is disposed on the driving circuit layer. The planarization layer includes a first planarization layer and a second planarization layer disposed on the first planarization layer. The first planarization layer is provided with a first hole, and the second planarization layer is provided with a second hole. The second hole is disposed in alignment with the first hole. The anode layer is disposed on the second planarization layer. The anode layer includes an anode, and the anode is electrically connected to the pixel driving circuit through the second hole and the first hole in sequence. The bottom of the hole wall of the first hole has a first slope angle, and the first slope angle is greater than 0 degree and less than or equal to 40 degrees. At least a part of the second planarization layer covers the hole wall of the first hole.

[0052] In the embodiment of the present application, by limiting the first slope angle at the bottom of the hole wall of the first hole within 40 degrees, the slope of the hole wall of the first hole is reduced, thereby reducing the stress on the second planarization layer at the first hole. In this way, the risk of cracking of the second planarization layer at the first hole can be reduced, so that the risk of cracking of the anode at the first hole and the second hole can be reduced, and further the production yield of the display panel can be improved.

[0053] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the display panel provided by the embodiment of the present application. The display panel 100 includes a driving circuit layer 11, a planarization layer 12, and an anode layer 13. The driving circuit layer 11 includes a pixel driving circuit. The planarization layer 12 is disposed on the driving circuit layer 11. The planarization layer 12 includes a first planarization layer 121 and a second planarization layer 122 disposed on the first planarization layer 121. The first planarization layer 121 is provided with a first hole V1, and the second planarization layer 122 is provided with a second hole V2. The second hole V2 is disposed in alignment with the first hole V1.

[0054] It should be noted that the alignment setting of the second hole V2 and the first hole V1 means that the second hole V2 is located above the first hole V1, and the center of the second hole V2 coincides with the center of the first hole V1; or, the second hole V2 is located above the first hole V1, and the distance between the center of the second hole V2 and the center of the first hole V1 in the horizontal direction is within a certain error range. In some embodiments, the distance between the center of the second hole V2 and the center of the first hole V1 in the horizontal direction is greater than or equal to 0 and less than or equal to 0.5 μm. For example, the distance between the center of the second hole V2 and the center of the first hole V1 in the horizontal direction can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc. When the distance between the center of the second hole V2 and the center of the first hole V1 in the horizontal direction is 0, the centers of the first hole V1 and the second hole V2 coincide.

[0055] As Figure 1 shown, the anode layer 13 is disposed on the second flat layer 12. The anode layer 13 includes an anode 131, and the anode 131 is electrically connected to the pixel driving circuit through the second hole V2 and the first hole V1 in sequence.

[0056] As Figure 2 and Figure 3 shown, Figure 2 is Figure 1 the enlarged schematic view of the dashed box in Figure 3 This is a top view of the first hole and the second hole in the display panel provided by the embodiment of the present application. The bottom of the hole wall of the first hole V1 has a first slope angle a, and the first slope angle a is greater than 0 degree and less than or equal to 40 degrees. Herein, the bottom of the hole wall of the first hole V1 refers to the part of the hole wall of the first hole V1 close to the driving circuit layer, and the top of the hole wall of the first hole V1 refers to the part of the hole wall of the first hole V1 away from the driving circuit layer 11. The slope angle refers to the angle between the tangent line of any point on the hole wall of the first hole V1 and the horizontal direction, and the horizontal direction is the direction parallel to the bearing surface of the display panel.

[0057] As Figure 2As shown, the first hole V1 gradually expands outward from one end close to the driving circuit layer 11 to the end away from the driving circuit layer 11. The slope angle of the hole wall of the first hole V1 gradually decreases from the bottom to the top of the first hole V1. This allows the slope of the hole wall of the first hole V1 to gradually decrease from the bottom to the top of the first hole V1. The second flat layer 122 at least partially covers the hole wall of the first hole V1. Because the first slope angle a at the bottom of the hole wall of the first hole V1 is within 40 degrees, the entire hole wall of the first hole V1 has a smaller slope. This can reduce the stress on the second flat layer 122 at the first hole V1, thereby reducing the risk of cracks in the second flat layer 122 at the first hole V1, thereby reducing the risk of cracks in the anode 131 at the first hole V1 and the second hole V2, thereby improving the production yield of the display panel.

[0058] In some embodiments, as Figure 1 As shown, the display panel 100 includes a substrate 10 and a driving circuit layer 11, which is disposed on the substrate 10. The driving circuit layer 11 includes a buffer layer 111, an active layer 112, a first gate insulating layer 113, a first gate layer 114, a second gate insulating layer 115, a second gate layer 116, a first interlayer dielectric layer 117, a first source and drain layer 118, and a passivation layer 119, which are sequentially stacked on the substrate 10. The planarization layer 12 is disposed on a side of the passivation layer 119 away from the substrate 10.

[0059] In some embodiments, as Figure 1 and Figure 2 As shown, the orthographic projection of the second hole V2 on the driving circuit layer 11 is within the orthographic projection of the first hole V1 on the driving circuit layer. The second flat layer 122 completely covers the wall of the first hole V1 and also partially covers the bottom of the first hole V1. When the first hole V1 and the second hole V2 are circular holes, the diameter of the first hole V1 is larger than the diameter of the second hole V2. When the first hole V1 and the second hole V2 are not circular holes, the diameter of the minimum circumscribed circle of the first hole V1 is larger than the diameter of the minimum circumscribed circle of the second hole V2.

[0060] By making the orthographic projection of the second hole V2 on the driving circuit layer 11 fall within the orthographic projection range of the first hole V1 on the driving circuit layer 11 and making the second flat layer 122 completely cover the hole wall of the first hole V1, part of the second flat layer 122 can be directly deposited on the bottom of the first hole V1 at the first hole V1. On the one hand, since the bottom of the first hole V1 is relatively flat, the stress on the second flat layer 122 at the first hole V1 can be further reduced, so as to further reduce the risk of cracks in the second flat layer 122 at the first hole V1, thereby further reducing the risk of cracks in the anode 131 at the first hole V1 and the second hole V2, and then improving the production yield of the display panel. On the other hand, the orthographic projection of the second hole V2 on the driving circuit layer 11 falls within the orthographic projection range of the first hole V1 on the driving circuit layer 11, which can reduce the space occupied by the second hole V2. Therefore, there is more space for placing sub-pixels, thereby improving the pixel density of the display panel.

[0061] In some embodiments, referring to Figure 2 , there is a first distance L1 in the horizontal direction between the bottom of the hole wall of the first hole V1 and the bottom of the hole wall of the second hole V2, and the horizontal direction is the direction parallel to the bearing surface of the display panel. The first flat layer 121 has a first thickness H1, and the first thickness H1 is the overall thickness of the first flat layer 121. The ratio of the first thickness H1 to the first distance L1 is greater than or equal to 2 / 3 and less than or equal to 2. For example, the ratio of the first thickness H1 to the first distance L1 can be 2 / 3, 3 / 4, 1, 1.2, 1.5, 1.7, or 2, etc.

[0062] As Figure 2 shown, the bottom of the hole wall of the second hole V2 has a second slope angle b. The second slope angle b is affected by the first thickness H1 and the first distance L1. The larger the first thickness H1, the larger the second slope angle b; the smaller the first distance L1, the smaller the second slope angle b. If the second slope angle b is too large, the film forming uniformity of the anode 131 deposited on the hole wall of the second hole V2 will be poor, and there is even a risk of fracture; if the second slope angle b is too small, when the thickness of the second flat layer 122 remains unchanged, the space occupied by the second hole V2 will increase, and even compress the space of the surrounding sub-pixels, resulting in a decrease in the pixel density of the display panel. In this embodiment, by limiting the ratio of the first thickness H1 to the first distance L1 between 2 / 3 and 2, not only can the film forming uniformity of the anode 131 be improved, the risk of cracks in the anode 131 at the second hole V2 be reduced, but also the space occupied by the second hole V2 can be reduced, and the pixel density of the display panel can be improved.

[0063] In some embodiments, as Figure 2As shown, the first thickness H1 is greater than or equal to 1 μm and less than or equal to 3 μm, and the first distance L1 is greater than or equal to 1 μm and less than or equal to 5 μm. For example, the first thickness H1 is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc., and the first distance L1 is 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.

[0064] It should be noted that restricting the first thickness H1 between 1 μm and 3 μm and the first distance L1 between 1 μm and 5 μm can not only ensure the flatness of the first flat layer 121, but also avoid the situation where the second slope angle b at the bottom of the hole wall of the second hole V2 is too large due to the excessive first thickness H1, resulting in poor film formation uniformity of the anode 131. Moreover, it can reduce the space occupied by the second hole V2 and improve the pixel density of the display panel.

[0065] In some embodiments, as Figure 2 shown, the first distance L1 is greater than or equal to 1 μm and less than or equal to 2 μm. In this way, the risk of cracks in both the second flat layer 122 and the anode 131 can be reduced simultaneously, and the pixel density of the display panel can be improved.

[0066] In some embodiments, as Figure 2 shown, the first slope angle a is greater than or equal to 20° and less than or equal to 40°. For example, the first slope angle a can be 20°, 25°, 30°, 35°, 40°, etc. It should be noted that when the thickness of the first flat layer 121 remains unchanged, the space occupied by the first hole V1 is related to the first slope angle a. The smaller the first slope angle a, the larger the space occupied by the first hole V1. When ensuring the flatness of the first flat layer 121, if the first slope angle a is too small, the space occupied by the first hole V1 will be larger, and even the space of surrounding sub-pixels will be compressed, resulting in a decrease in the pixel density of the display panel. In this embodiment, by adjusting the first slope angle a from the existing 45° to between 20° and 40°, while reducing the space occupied by the first hole V1 and increasing the pixel density of the display panel, the risk of cracks in the second flat layer 122 and the anode 131 at the first hole V1 can be reduced.

[0067] In some embodiments, please refer to Figure 2, the second slope angle b is greater than or equal to 40 degrees and less than or equal to 70 degrees. For example, the second slope angle b can be 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, or 70 degrees, etc. It should be noted that when the thickness of the second flat layer 122 remains unchanged, the space occupied by the second hole V2 is related to the second slope angle b. The smaller the second slope angle b, the larger the space occupied by the second hole V2. When ensuring the flatness of the second flat layer 122, if the second slope angle b is too small, the space occupied by the second hole V2 will be larger, and even the space of surrounding sub-pixels will be compressed, resulting in a decrease in the pixel density of the display panel. In this embodiment, by limiting the second slope angle b between 40 degrees and 75 degrees, the space occupied by the second hole V2 can be reduced, the pixel density of the display panel can be increased, and at the same time, the risk of the anode 131 cracking at the second hole V2 can be reduced.

[0068] In some embodiments, as Figure 2 shown, the thickness of the second flat layer 122 is greater than or equal to 2 micrometers and less than or equal to 3 micrometers. For example, the second flat layer 122 has a second thickness H2, and the second thickness H2 can be 2 micrometers, 2.5 micrometers, or 3 micrometers, etc. It should be noted that since the second flat layer 122 needs to cover the first flat layer 121, if the thickness of the second flat layer 122 is too small, the flatness of the second flat layer 122 will be reduced; if the thickness of the second flat layer 122 is too large, the production cost will increase. In this embodiment, by limiting the thickness of the second flat layer 122 between 2 and 3 micrometers, the flatness of the second flat layer 122 and the production cost can be taken into account.

[0069] In some embodiments, please refer to Figure 2 , the second hole V2 can be a round hole, and the aperture of the second hole V2 is Figure 2 the second distance L2 shown, and the second distance L2 is greater than or equal to 5 micrometers. In some other embodiments, the second hole V2 can also be an oval, a rounded rectangular hole, or a hexagon, etc. At this time, the minimum diameter of the circumscribed circle of the second hole V2 is the second distance L2, and the second distance L2 is greater than or equal to 1.5 micrometers. For example, the second distance L2 is 1.5 micrometers, 1.8 micrometers, 2 micrometers, or 2.5 micrometers, etc. It should be noted that if the aperture of the second hole V2 or the minimum diameter of the circumscribed circle of the second hole V2 is too small, due to the accuracy of the exposure machine, the second hole V2 that penetrates the second flat layer 122 may not be formed. By limiting the aperture of the second hole V2 or the minimum diameter of the circumscribed circle to more than 1.5 micrometers, it can be ensured that the second hole V2 can be formed, and the yield of the display panel can be improved.

[0070] In some embodiments, please refer to Figure 1 and Figure 2, the planar layer 12 further includes a third planar layer 123, and the third planar layer 123 is located on a side of the first planar layer 121 away from the second planar layer 122. By adopting the three-layer planar structure formed by the first planar layer 121, the second planar layer 122, and the third planar layer 123, the flatness of the planar layer 12 can be improved, which is convenient for improving the uniformity of the thickness of the film layer formed by inkjet printing and improving the uniformity of the display brightness of the display panel.

[0071] In some embodiments, referring to Figure 1 , the display panel 100 further includes a connection layer 14. The connection layer 14 is disposed between the first planar layer 121 and the third planar layer 123. The connection layer 14 includes a connection portion 141, and the anode 131 is electrically connected to the pixel driving circuit through the second hole V2, the first hole V1, and the connection portion 141 penetrating through the third planar layer 123 in sequence.

[0072] In some embodiments, referring to Figure 1 , the display panel 100 further includes a pixel definition layer 16 and a spacer layer 15. The pixel definition layer 16 is disposed on the anode layer 13 and the second planar layer 122, and the spacer layer 15 is disposed on the pixel definition layer 16. The pixel definition layer 16 has a plurality of pixel openings that penetrate through the pixel definition layer 16. The anode 131 is located at the bottom of the pixel opening, and the region defined by each pixel opening corresponds to a sub-pixel.

[0073] Referring to Figures 1 to 4 and Figures 5a to 5e , Figure 4 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application. Figures 5a to 5e is a schematic diagram of a method for manufacturing a display panel provided by an embodiment of the present application. The method for manufacturing the display panel includes the following steps:

[0074] Step S1, forming a driving circuit layer 11;

[0075] Step S2, forming a layer of first planar material 1210 on the driving circuit layer 11;

[0076] Step S3, patterning the first planar material 1210 to form a first hole V1 and obtaining a first planar layer 121;

[0077] Step S4, forming a layer of second planar material 1220 on the first planar layer 121;

[0078] Step S5, patterning the second planar material 1220 to form a second hole V2 and obtaining a second planar layer 122;

[0079] Step S6, forming an anode layer 13 on the second planar layer 122.

[0080] AsFigure 5a As shown, before performing step S2, a connection portion 141 is formed on the driving circuit layer 11, and the first planar material 1210 covers the driving circuit layer 11 and the connection portion 141.

[0081] As Figure 5b and Figure 5c shown, step S3 includes: step S31, patterning the first planar material 1210 to form a third hole V3 and a reserved portion 1211 connected to the inner wall of the third hole V3; step S32, heating the first planar material 1210 to cause the reserved portion 1211 to flow towards the center of the third hole V3 to form a first hole V1.

[0082] In some embodiments, step S31 includes: covering a photomask 2 above the first planar material 1210, the photomask 2 having a first light-transmitting region 21, a first light-blocking region 23, and a second light-transmitting region 22, the first light-blocking region 23 surrounding the second light-transmitting region 22, and the first light-transmitting region 21 surrounding the first light-blocking region 23; exposing the first planar material 1210, the width of the first light-transmitting region 21 being less than the exposure accuracy; performing a developing process on the first planar material 1210, a portion of the first planar material 1210 corresponding to the second light-transmitting region 22 forming the third hole V3, and a portion of the first planar material 1210 corresponding to the first light-blocking region 23 forming the reserved portion 1211.

[0083] As Figure 6 shown, Figure 6 is a schematic diagram of a photomask in the manufacturing method of a display panel provided by an embodiment of the present application. The photomask 2 has a first light-transmitting region 21, a first light-blocking region 23, and a second light-transmitting region 22. The first light-blocking region 23 surrounds the second light-transmitting region 22, the first light-transmitting region 21 surrounds the first light-blocking region 23. Both the first light-transmitting region 21 and the first light-blocking region 23 are annular structures. The first light-transmitting region 21 has a first width L3, and the first width L3 is less than the exposure accuracy of the exposure machine.

[0084] In the actual preparation process, since the first width L3 of the first light-transmitting region 21 is less than the exposure accuracy of the exposure machine, a portion of the first planar material 1210 corresponding to the first light-transmitting region 21 cannot be fully exposed. As a result, after the developing process, there is still a portion of the first planar material 1210 remaining in the portion corresponding to the first light-transmitting region 21. This remaining portion of the first planar material constitutes the inner wall of the third hole V3 and is connected to the reserved portion 1211.

[0085] In some embodiments, the accuracy of the exposure machine is 1 micron, and the first width L3 is less than 1 micron. In this way, it can be ensured that the portion of the first planar material 1210 corresponding to the first light-transmitting region 21 cannot be completely removed, so as to ensure the connection between the reserved portion 1211 and the inner wall of the third hole V3, and avoid breakage with other parts after the reserved portion 1211 is heated and flows.

[0086] In some embodiments, as Figure 6 As shown, the first non-light-transmitting area 23 has a second width L4, and the second width L4 is less than the precision of the exposure machine. For example, the precision of the exposure machine is 1 micron, and the second width L4 is less than 1 micron. It should be noted that if the second width L4 of the first non-light-transmitting area 23 is too large, the first slope angle c of the bottom of the hole wall of the first hole V1 formed by the reserved portion 1211 after the heat treatment will be too large, resulting in an increased risk of cracks in the second flat layer 122 and the anode 131 at the first hole V1. By making the width of the first non-light-transmitting area 23 smaller than the precision of the exposure machine, this embodiment can ensure that the first slope angle c of the bottom of the hole wall of the first hole V1 formed by the reserved portion 1211 after the heat treatment is within 40 degrees, thereby reducing the risk of cracks in the second flat layer 122 and the anode 131 at the first hole V1 and improving the production yield of the display panel.

[0087] In some embodiments, as Figure 5b and Figure 5c As shown, the material of the first flat material 1210 is photoresist. Since the photoresist is fluid, after the first flat material 1210 is heated, the reserved portion 1211 will flow toward the center of the third hole, and cause the third hole V3 to shrink inward to form the first hole V1, so that the hole wall of the first hole V1 has a gentle slope, and the first slope angle of the bottom of the hole wall of the first hole V1 can be less than or equal to 40 degrees.

[0088] In some embodiments, the first planar material 1210 may be heated by baking.

[0089] In some embodiments, as Figure 5d and Figure 5e As shown, a layer of second flat material 1220 is formed on the first flat layer 121, and the second flat material 1220 is patterned to form a second hole V2, and a second flat layer 122 is obtained. The second flat layer 122 covers the hole wall of the first hole V1 and part of the hole bottom of the first hole V1. Since the hole wall of the first hole V1 has a gentle slope, the first slope angle of the bottom of the hole wall of the first hole V1 is less than or equal to 40 degrees. In this way, the stress on the second flat layer 122 at the first hole V1 can be reduced, thereby reducing the risk of cracks in the second flat layer 122 and the anode 131 at the first hole V1, thereby improving the production yield of the display panel.

[0090] In some embodiments, see Figure 7 and Figure 8 , Figure 7 A schematic structural diagram of another display panel provided in an embodiment of the present application is shown. Figure 8 for Figure 7 The enlarged schematic diagram of the dotted box in FIG. 1 shows thatFigure 7 The structure of the display panel shown is the same as that of Figure 1 the display panel shown, except that: the second flat layer 122 partially covers the hole wall of the first hole V1, and the orthographic projection of the first hole V1 on the driving circuit layer 11 is within the orthographic projection range of the second V2 on the driving circuit layer 11.

[0091] It should be noted that since the first slope angle a at the bottom of the hole wall of the first hole V1 is less than or equal to 40 degrees, the hole wall of the first hole V1 has a relatively small slope. In this structure, when the second flat layer 122 is overlapped on the hole wall of the first hole V1, the stress on the second flat layer 122 at the first hole V1 can also be reduced. Therefore, the risk of cracks generated at the first hole V1 between the second flat layer 122 and the anode 131 can be reduced, thereby improving the production yield of the display panel.

[0092] The following are the embodiments and comparative examples of this application:

[0093] Embodiment 1: The display panel includes a driving circuit layer 11, a flat layer 12, and an anode layer 13. The flat layer 12 includes a first flat layer 121 and a second flat layer 122. The first flat layer 121 is provided with a first hole V1, and the second flat layer 122 is provided with a second hole V2. The second flat layer 122 completely covers the hole wall of the first hole V1. The first slope angle a at the bottom of the hole wall of the first hole V1 is 40 degrees, the second slope angle b at the bottom of the hole wall of the second hole V2 is 70 degrees, the first distance L1 is 2 microns, the second distance L2 is 1.5 microns, and the first thickness H1 is 2.7 microns.

[0094] Embodiment 2: The display panel includes a driving circuit layer 11, a flat layer 12, and an anode layer 13. The flat layer 12 includes a first flat layer 121 and a second flat layer 122. The first flat layer 121 is provided with a first hole V1, and the second flat layer 122 is provided with a second hole V2. The second flat layer 122 partially covers the hole wall of the first hole V1. The first slope angle a at the bottom of the hole wall of the first hole V1 is 40 degrees, the second slope angle b at the bottom of the hole wall of the second hole V2 is 70 degrees, and the first thickness H1 is 2.7 microns.

[0095] Comparative Example 1: The display panel includes a driving circuit layer 11, a flat layer 12, and an anode layer 13. The flat layer 12 includes a first flat layer 121 and a second flat layer 122. The first flat layer 121 is provided with a first hole V1, and the second flat layer 122 is provided with a second hole V2. The second flat layer 122 partially covers the hole wall of the first hole V1. The first slope angle a at the bottom of the hole wall of the first hole V1 is 45 degrees, the second slope angle b at the bottom of the hole wall of the second hole V2 is 70 degrees, and the first thickness H1 is 2.7 microns.

[0096] Combined with Figure 9 shown, Figure 9This is an enlarged schematic diagram of the display panel at the second hole V2 in Example 1. At the second hole V2, no cracks are generated in the second flat layer 122 and the anode 131. Similarly, in Example 2, no cracks are generated in the second flat layer 122 and the anode 131 at the second hole V2.

[0097] Combination Figure 10 As shown, Figure 10 1 is a cross-sectional view of the display panel at the second hole V2 in Comparative Example 1. At the second hole V2, cracks are generated in the second planar layer 122. As a result of the cracks in the second planar layer 122, cracks are also generated in the anode 131.

[0098] By comparing Example 1, Example 2, and Comparative Example 1, it can be seen that both Example 1 and Example 2 employ the display panel manufacturing method provided in this application to achieve a first slope angle c of the bottom of the hole wall of the first hole V1 in the first flat layer 121 within 40 degrees. In Example 1, the second flat layer 122 completely covers the hole wall of the first hole V1, while in Example 2, the second flat layer 122 partially covers the hole wall of the first hole V1. As a result, no cracks occur in the second flat layer 122 or the anode 131 at the first hole V1 in either Example 1 or Example 2. In Comparative Example 1, the first slope angle of the bottom of the hole wall of the first hole V1 on the first flat layer 121 is 45 degrees, which exceeds the range specified in this application. This results in cracks in the second flat layer 122 at the first hole V1 in Comparative Example 1, and also in the anode 131 at this location. It can be seen that according to the technical solution provided in the embodiment of the present application, the risk of cracks in the second flat layer 122 and the anode 131 at the first hole V1 of the first flat layer 121 can be reduced, thereby achieving the technical effect of improving the yield of the display panel.

[0099] According to the display panel provided in the above embodiment of the present application, the embodiment of the present application further provides a display device, see Figure 11 , Figure 11 This is a schematic diagram of a display device provided in an embodiment of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided in any of the above embodiments. The display device provided in an embodiment of the present application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be described in detail here.

[0100] Beneficial effects of the embodiments of the present application: The present application provides a display panel and a method for manufacturing a display panel, wherein the display panel includes a driving circuit layer, a flat layer and an anode layer, the flat layer includes a first flat layer and a second flat layer, the first flat layer is provided with a first hole, the second flat layer is provided with a second hole, the second hole is arranged in alignment with the first hole, the second flat layer at least partially covers the hole wall of the first hole, the bottom of the hole wall of the first hole has a first slope angle, and the first slope angle is limited to within 40 degrees to reduce the slope of the hole wall of the first hole, thereby reducing the stress on the second flat layer at the first hole, thereby reducing the risk of cracks in the second flat layer at the first hole, thereby reducing the risk of cracks in the anode at the first hole and the second hole, thereby improving the production yield of the display panel.

[0101] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0102] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0103] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0104] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, Comprising: A driving circuit layer, including a pixel driving circuit; A planarization layer, disposed on the driving circuit layer, the planarization layer includes a first planarization layer and a second planarization layer disposed on the first planarization layer, the first planarization layer is provided with a first hole, the second planarization layer (122) is provided with a second hole, and the second hole is disposed in alignment with the first hole; An anode layer, disposed on the second planarization layer, the anode layer includes an anode, and the anode is electrically connected to the pixel driving circuit through the second hole and the first hole in sequence; Wherein, the bottom of the hole wall of the first hole has a first slope angle, the first slope angle is greater than 0 degree and less than or equal to 40 degrees, and the second planarization layer at least partially covers the hole wall of the first hole.

2. The display panel according to claim 1, wherein The orthographic projection of the second hole on the driving circuit layer is located within the orthographic projection range of the first hole on the driving circuit layer, and the second planarization layer completely covers the hole wall of the first hole.

3. The display panel according to claim 2, wherein There is a first distance in the horizontal direction between the bottom of the hole wall of the first hole and the bottom of the hole wall of the second hole, the first planarization layer has a first thickness, and the ratio of the first thickness to the first distance is greater than or equal to 2 / 3 and less than or equal to 2.

4. The display panel according to claim 2, characterized in that The first planarization layer has a first thickness, and the first thickness is greater than or equal to 1 micron and less than or equal to 3 microns; There is a first distance between the bottom of the hole wall of the first hole and the bottom of the hole wall of the second hole, and the first distance is greater than or equal to 1 micron and less than or equal to 5 microns.

5. The display panel according to claim 1, characterized in that, The first slope angle is greater than or equal to 20 degrees.

6. The display panel according to claim 1, wherein The bottom of the hole wall of the second hole has a second slope angle, and the second slope angle is greater than or equal to 40 degrees and less than or equal to 70 degrees.

7. The display panel according to claim 1, characterized in that, The thickness of the second planarization layer is greater than or equal to 2 microns and less than or equal to 3 microns.

8. The display panel according to any one of claims 1 to 7, characterized in that, The planarization layer further includes a third planarization layer, and the third planarization layer is disposed on the side of the first planarization layer away from the second planarization layer; Wherein, the display panel further includes a connection layer, the connection layer is disposed between the first planarization layer and the third planarization layer, the connection layer includes a connection portion, and the anode is electrically connected to the pixel driving circuit through the second hole, the first hole and the connection portion penetrating through the third planarization layer in sequence.

9. A method for manufacturing a display panel, characterized in that, The manufacturing method of the display panel includes: Forming a driving circuit layer; Forming a layer of first planarization material on the driving circuit layer; Performing patterning on the first planarization material to form a first hole and obtain a first planarization layer; Forming a layer of second planarization material on the first planarization layer; Performing patterning on the second planarization material to form a second hole and obtain a second planarization layer; Forming an anode layer on the second planarization layer; Wherein, the driving circuit layer includes a pixel driving circuit, the anode layer includes an anode, the second hole is disposed in alignment with the first hole, the bottom of the hole wall of the first hole has a first slope angle, the first slope angle is greater than 0 degree and less than or equal to 40 degrees, the second planarization layer at least partially covers the hole wall of the first hole, and the anode is electrically connected to the pixel driving circuit through the second hole.

10. The manufacturing method of the display panel according to claim 9, wherein, The step of patterning the first flat material to form a first hole and obtain a first flat layer includes: Patterning the first flat material to form a third hole and a reserved portion connected to the inner wall of the third hole; Heating the first flat material to cause the reserved portion to flow towards the center of the third hole to form the first hole.

11. The manufacturing method of the display panel according to claim 10, wherein The step of patterning the first flat material to form a third hole and a reserved portion connected to the inner wall of the third hole includes: Covering a photomask above the first flat material, the photomask having a first light-transmitting region, a first light-blocking region, and a second light-transmitting region, the first light-blocking region surrounding the second light-transmitting region, and the first light-transmitting region surrounding the first light-blocking region; Exposing the first flat material, the width of the first light-transmitting region being less than the exposure accuracy; Developing the first flat material, a portion of the first flat material corresponding to the second light-transmitting region forming the third hole, and a portion of the first flat material corresponding to the first light-blocking region forming the reserved portion.

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