Adaptive current limiting circuit

Abstract

A power supply circuit includes an amplifier (AMP1) and first and second transistors (M1 and M3). The amplifier (AMP1) is configured to provide a drive potential at its output. The first transistor (M1) is coupled between a voltage supply terminal and an output terminal, and has a first control terminal coupled to the amplifier output, and is configured to receive at least a portion of the drive potential at the first control terminal. The second transistor (M3) is coupled between the first control terminal and the output terminal and has a second control terminal coupled to the amplifier output. The threshold voltage of the first transistor (M1) is lower than the threshold voltage of the second transistor (M3). The second transistor (M3) is operable to switch on the portion of the drive potential at the first control terminal adaptively in response to a voltage at the output terminal being lower than a certain voltage level, for example by the second transistor (M3).

Description

Technical Field

[0001] This specification relates to regulated power supplies, and more particularly to an adaptive current circuit. Background Art

[0002] The direct current (DC) output voltage provided by a standard power supply to a load may vary due to any number of factors such as transient conditions, environmental conditions, and load conditions changes. In such cases, a voltage regulator may be coupled between the power supply and the load and is used to provide a regulated DC output voltage to the load. In this way, the output voltage of the voltage regulator remains unaffected by sudden changes in the input supply voltage and load current or other transient changes. There are many types of DC-DC voltage regulators, including switching regulators and linear regulators.

[0003] Source follower power supply configurations are widely used in DC-DC voltage regulator designs. For example, a switching regulator (e.g., a buck converter) may use a source follower to charge the startup capacitor of a startup circuit, and a linear regulator (e.g., a low dropout voltage regulator or an LDO voltage regulator) may use a source follower to provide a regulated output voltage. However, there are still several problems that cannot be ignored in such regulators. Summary of the Invention

[0004] One example includes a power supply circuit that includes an amplifier and first and second transistors. The amplifier has an amplifier output and is configured to provide a drive potential at the amplifier output. The first transistor is coupled between a voltage supply terminal and an output terminal and has a first control terminal coupled to the amplifier output. The first transistor is configured to receive at least a portion of the drive potential at the first control terminal. The second transistor is coupled between the first control terminal and the output terminal and has a second control terminal coupled to the amplifier output. The threshold voltage of the first transistor is lower than the threshold voltage of the second transistor, and the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal in response to the voltage at the output terminal being lower than a certain voltage level by turning on the second transistor. In one such example configuration, the power supply circuit may be included within an integrated circuit package, and the output terminal is a pin or pad of the integrated circuit package. The output terminal may be, for example, a startup pin (to which a startup capacitor is coupled) or an output voltage pin.

[0005] Another example is a power supply circuit that includes an amplifier and first, second, and third transistors. The amplifier has an amplifier output and a voltage reference input. The first transistor is coupled between a voltage supply terminal and an output terminal and has a first control terminal coupled to the amplifier output. The second transistor is coupled between the first transistor and the output terminal and has a second control terminal coupled to the amplifier output. The third transistor is coupled between the second transistor and the output terminal and has a third control terminal and a body terminal, where the third control terminal is coupled to the amplifier output and the body terminal is coupled to a reference terminal. In one such example configuration, the power supply circuit can be included within an integrated circuit package, and the output terminal is a pin or pad of the integrated circuit package. The output terminal can be, for example, an enable pin or an output voltage pin.

[0006] Another example is a power supply circuit that includes an amplifier and first and second transistors. The amplifier has an amplifier output and a voltage reference input. The first transistor is coupled between a voltage supply terminal and an output terminal and has a first control terminal coupled to the amplifier output. The second transistor is coupled between the first control terminal and the output terminal and has a second control terminal coupled to the amplifier output. The threshold voltage of the first transistor is lower than the second threshold voltage of the second transistor. In one such example configuration, the power supply circuit can be included within an integrated circuit package, and the output terminal is a pin or pad of the integrated circuit package. The output terminal can be, for example, an enable pin or an output voltage pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A block diagram showing a switched-mode power supply configured with an adaptive current limit circuit in one example.

[0008] Figure 1B A block diagram showing a low dropout (LDO) voltage regulator configured with an adaptive current limit circuit in one example.

[0009] Figure 2 A regulated power supply circuit vulnerable to damage caused by a short circuit condition on a given output pin is shown.

[0010] Figure 3 A schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in one example.

[0011] Figure 4 A schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in another example.

[0012] Figure 5 A schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in another example.

[0013] Figure 6 Schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in another example.

[0014] Figure 7A Another detailed schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in another example.

[0015] Figure 7B Another detailed schematic diagram showing a switched-mode power supply configured with an adaptive current limit circuit in another example.

[0016] Figure 8A Schematic diagram showing an LDO voltage regulator configured with an adaptive current limit circuit in an example.

[0017] Figure 8B Schematic diagram showing an LDO voltage regulator configured with an adaptive current limit circuit in another example.

[0018] Figure 9 Method for adaptively limiting current in a regulated power supply in an example. Detailed Description

[0019] Adaptive current limit techniques are described herein. Although these techniques can be used in any number of applications, they are particularly useful for limiting the current through a source follower power supply coupled to terminals that are prone to shorting. The techniques are adaptive because they can be used to provide a desired transient response (relatively high current) during normal operation and low power dissipation (relatively low current) during short circuit conditions. In one example, a power supply circuit includes an amplifier and first and second transistors. The amplifier has an amplifier output and is configured to provide a drive potential at the amplifier output. The first transistor is coupled between a voltage supply terminal and an output terminal and has a first control terminal coupled to the amplifier output. The first transistor is configured to receive at least a portion of the drive potential at the first control terminal. In one such example, the first transistor is configured as a source follower power supply. The second transistor is coupled between the first control terminal and the output terminal and has a second control terminal coupled to the amplifier output. The threshold voltage of the first transistor is lower than the threshold voltage of the second transistor. In operation, the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal, for example, by the second transistor turning on in response to the voltage at the output terminal being below a certain voltage level (e.g., a voltage indicating a short circuit on the output terminal). The output terminal can be, for example, a pin or pad of an integrated circuit package, such as a pin to which a startup capacitor can be coupled (e.g., in a switched-mode power supply) or an output voltage pin (e.g., in an LDO voltage regulator).

[0020] General Overview

[0021] As described above, there are still several problems that cannot be ignored in DC-DC voltage regulators employing a source follower power supply configuration. For example, in a switching regulator that uses a source follower to charge the startup capacitor of a startup circuit, if the startup pin is inadvertently shorted to ground, there may be very high power dissipation in the charging path, which may damage the source follower. More specifically, assume that the switching regulator has a 12-volt input voltage and a 150-milliamp current, and the source follower is implemented with an n-channel field effect transistor (NFET). In this case, if the startup pin is shorted to ground, approximately 1.8 watts of power is dissipated in the charging path and across the NFET. The NFET may be easily damaged due to this relatively high power dissipation depending on its size. A possible solution to this problem is to use a constant current source to limit the available current. For example, given a 12-volt input voltage, a constant limit of 10 milliamps can be used to limit the power dissipation to approximately 0.12 watts. However, this current limit will also limit the transient response current required to charge the startup capacitor. A similar problem may occur in the case of an LDO regulator, where if the output voltage pin is inadvertently shorted to ground, the passFET may be damaged.

[0022] Accordingly, a current limiting circuit system is described herein to adaptively limit the current passing through a power supply (e.g., a source follower power supply) coupled to an output pin or other terminal. Different from a constant current source, the techniques can be used to provide a desired transient response (relatively high current) during normal or first operating mode and low power dissipation (relatively low current) during a short circuit condition or second operating mode. The techniques can be implemented in any number of power supply topologies.

[0023] Circuit Architecture

[0024] Figure 1A A block diagram of a switching power supply 50 configured with an adaptive current limiting circuit 55 is shown in an example. As shown, the switching power supply 50 generally includes a regulation core 51 and a switching core 53. The adaptive current limiting circuit 55 is implemented within the switching core 53. The switching power supply 50 receives a given input voltage (V IN ) at its input voltage terminal and provides a regulated output voltage (V OUT ) at its output voltage terminal. The values or ranges of V IN and V OUT can vary according to the example, but in some examples, both are in the range of 3.3 volts to 35 volts (e.g., V IN equals 5 volts or 12 volts, and V OUTequal to 5 volts or 8 volts).

[0025] The regulation core 51 is configured to generate a drive signal (V IN ) based on a given input voltage (V DRV ) and a given reference voltage. In this example case, the reference voltage is generated internally within the regulation core 51, but in other cases, the reference voltage can be generated externally to the regulation core 51. The switching core 53 receives the drive signal V DRV as well as the input voltage V IN , and is configured to generate a regulated output voltage (V OUT ). Each of the regulation core 51 and the switching core 53 can be implemented with any suitable configuration, provided that the switching core 53 is further configured with an adaptive current limit circuit 55. In some examples, the regulation core 51 and the switching core 53 are configured to implement a buck converter, a boost converter, a buck-boost converter, or a flyback converter. More generally, the regulation core 51 and the switching core 53 can be any power supply circuitry that includes terminals (e.g., pins, pads, internal nodes, or external nodes) that are powered, and the terminals are vulnerable to short circuit conditions or some other condition that may cause an overcurrent to flow to the terminals.

[0026] As shown, the adaptive current limit circuit 55 is coupled to the V IN terminal, a reference or ground terminal (REF), and the output of the regulation core 51 such that it receives the drive signal V DRV as an input. The adaptive current limit circuit 55 is further coupled to the terminal (T PROT ) to be protected in the event of a short circuit condition at the terminal. In one example, the terminal T PROT is coupled to the output of a source follower power supply implemented within the switched-mode power supply 50 (e.g., in a startup circuit). The terminal T PROT can be, for example, a node within the switched-mode power supply 50 or a pin or pad of an integrated circuit package in which the switched-mode power supply 50 is located. More generally, the terminal T PROT can be any conductor that is powered via a source follower power supply or any other power supply that may be damaged due to a short circuit or other high current condition. In operation, the adaptive current limit circuit 55 is configured to limit the current flowing to the terminal T PROT during a short circuit or high current condition at the terminal. Additional details of the adaptive current limit circuit 55 are described below with reference to Figures 2 - 7B and 9.

[0027] Figure 1BBlock diagram of a low dropout (LDO) voltage regulator 100 configured with an adaptive current limit circuit 110 in one example. As shown, the LDO voltage regulator 100 includes a voltage-to-current converter (V2I) circuit 102, a reference voltage (V REF ) circuit 104, a dropout detection circuit 106, and an LDO core 108. The adaptive current limit circuit 110 is implemented within the LDO core 108. The LDO voltage regulator 100 receives a given input voltage (V IN ) at its input voltage terminal and provides a regulated output voltage (V OUT ) at its output voltage terminal. The values or ranges of V IN and V OUT may vary according to the example, but in some examples, both are in the range of 3.3 volts to 35 volts (e.g., V IN is equal to 5 volts or 12 volts, and V OUT is equal to 5 volts or 8 volts).

[0028] The V2I circuit 102 is configured to provide a stable bias current (I REF ) to V BIAS 104. In one example, the V2I circuit 102 is implemented with a voltage-to-current converter circuit that includes a bandgap voltage reference (BGVR), an operational amplifier, a FET, and a resistor. The BGVR is configured to provide a stable voltage reference to the input of the amplifier and can be implemented with any number of standard or proprietary bandgap voltage reference circuit topologies, such as Brokaw, Widlar, and switched capacitor topologies. The amplifier may have a voltage follower configuration, with its inverting input connected to its output and receiving the output voltage of the BGVR at its non-inverting input. The output of the amplifier drives the gate of the FET. The resistor grounds the source of the FET, and the current through the resistor flows from the source of the FET to the drain, thereby providing the bias current I REF to the V BIAS circuit 104 to assist in generating the reference voltage V REF . More generally, the V2I circuit 102 can be any number of voltage-to-current converter configurations.

[0029] The V REF circuit 104 is configured to generate a reference voltage V REF for the LDO core 108 based on the bias current I BIAS from the V2I circuit 102. In one example, V REFCircuit 104 includes an amplifier and a transistor (such as a passFET or other switching element). The transistor is gated or otherwise controlled by the output signal of the amplifier. The amplifier is configured with first and second input resistors on its inverting and non-inverting inputs respectively, which, in combination with the bias current I BIAS effectively determine a reference current. The reference current generated by the amplifier passes through the transistor and a reference resistor (which may be external to V REF Circuit 104), which in turn generates a reference voltage V REF . More generally, V REF Circuit 104 can be implemented with any reference voltage generator circuit configuration.

[0030] The differential pressure detection circuit 106 senses a differential pressure condition and is configured to cause a higher reference current (sometimes referred to as a fast soft-start current IFss) in V REF Circuit 104 in order to shorten the start-up time with a higher ramp rate across a reference capacitor coupled in parallel with a reference resistor external or internal to V REF Circuit 104. Additionally, the differential pressure detection circuit 106 is configured to limit overshoot on the reference voltage V OUT by disconnecting or otherwise deactivating the fast soft-start current IFss in response to the regulator output voltage V REF reaching a given voltage threshold (e.g., 90% of the target output voltage) when the regulator is coming out of differential pressure. In one example, the differential pressure detection circuit 106 includes a comparator that outputs a logic low (or other differential pressure indication signal) whenever the output voltage V OUT deviates from regulation by more than a given threshold (e.g., ≥5%). The differential pressure indication signal can be used to turn on and off the fast soft-start current as needed (e.g., by controlling the value of one of the input resistors on the input of the amplifier of V REF Circuit 104). More generally, the differential pressure detection circuit 106 can be implemented with any configuration capable of adjusting the reference current provided by V REF Circuit 104 during differential pressure.

[0031] The LDO core 108 is configured to provide a regulated voltage output V IN based on the input supply voltage V REF and the reference voltage V REF provided by V OUT Circuit 104. In one example, the LDO core 108 includes a switching element (also referred to as a conducting element), such as a passFET coupled in a source follower configuration between the input voltage terminal V IN and the output voltage terminal V OUT ; and a unit gain configuration for driving a signal V DRVAn amplifier for a gating switch element. More generally, the LDO core 108 can be implemented with any LDO core configuration capable of generating a regulated output voltage based on an input supply voltage V IN and a reference voltage V REF provided by a reference voltage generation circuit, provided that the LDO core 108 is further configured with an adaptive current limit circuit 110.

[0032] Thus, each of the V2I circuit 102, the V REF circuit 104, the voltage difference detection circuit 106, and the LDO core 108 can be implemented in any suitable configuration, provided that the LDO core 108 is further configured with an adaptive current limit circuit 110. More generally, the LDO voltage regulator 100 can be any low-dropout voltage circuitry that includes a terminal (e.g., a pin, pad, internal node, or external node) powered by a source follower power supply or any other power supply that may be damaged due to a short circuit or other high-current condition.

[0033] As shown, the adaptive current limit circuit 110 is coupled to the V IN terminal, a reference or ground terminal (REF), and the output of the V REF circuit 104 such that it receives the reference voltage V REF as an input. As described above, the LDO core 108 uses the reference voltage V REF to generate a drive signal V DRV , and the current limit circuit 110 also receives the drive signal as an input. The adaptive current limit circuit 110 is further coupled to a terminal (T PROT ) to be protected in the event of a short circuit condition at the terminal. The terminal T PROT is coupled to the output of a source follower power supply implemented within the LDO voltage regulator 100, such as a passFET in the LDO core 108. The terminal T PROT can be, for example, a node within the LDO voltage regulator 100 or a pin or pad of an integrated circuit package in which the LDO voltage regulator 100 is located. In this example, the terminal T PROT is the output voltage V OUT terminal. In operation, the adaptive current limit circuit 110 is configured to limit the current flowing to the terminal T PROT (which is also the V OUT terminal) during a short circuit or other high-current condition at that terminal. Additional details of the adaptive current limit circuit 110 are described below with reference to Figure 8A -B and 9.

[0034] Figure 2A regulated power supply circuit vulnerable to damage caused by a short - circuit condition on a given terminal is shown. As shown, the circuit includes an operational amplifier (AMP1), a first n - channel FET (M1), a second n - channel FET (M PASS ), and a voltage divider network (R1 and R2). The output voltage (V DRV ) of amplifier AMP1 is applied to the gates of FETs M1 and M PASS . In operation, FET M PASS is configured to transfer current from the V PASS terminal to the voltage divider network in response to V DRV at the gate of M IN . The voltage divider network samples the voltage at the source of M PASS and provides the sample (V IN *R1 / [R1 + R2]) to the inverting input of AMP1. Since the source voltage of M PASS follows the output voltage of amplifier AMP1, this configuration is sometimes referred to as a voltage follower. Additionally, FET M1 is configured as a source - follower power supply to supply power from the input voltage terminal V DRV to terminal P1 in response to the output voltage V IN of amplifier AMP1. Unfortunately, if terminal P1 is inadvertently short - circuited to ground, most of the voltage V IN will drop across FET M1, potentially damaging M1.

[0035] Figure 3 A schematic diagram of a switched - mode power supply 50a configured with an adaptive current - limiting circuit in one example is shown. As shown, the switched - mode power supply 50a generally includes a regulation core 51 and an adaptive current - limiting circuit 55a. Other parts of the switched - mode power supply 50a (such as the switching core) are not shown in Figure 3 but are shown in Figure 7A -B. The regulation core 51 is configured as a voltage follower in a manner similar to that shown in Figure 2 , and the related description above applies here as well.

[0036] The adaptive current - limiting circuit 55a of this example also includes an n - channel FET M1, which is configured as a source - follower power supply to supply power from the input voltage terminal V DRV to terminal T IN in response to the output voltage V PROT of amplifier AMP1. However, different from the circuit of Figure 2 , the percentage or ratio of the output voltage V DRV of amplifier AMP1 applied to the gate of FET M1 can be based on the terminal T PROTvaries with the voltage level at. For example, in this instance, the current limiting circuit 55a further includes resistors R3 and R4 operatively coupled to n-channel FETs M2 and M3, the n-channel FETs being connected in series between the gate of FET M1 and terminal T PROT . More specifically, resistors R3 and R4 are connected in series with each other between the AMP1 output and the M1 gate and can be used to fine-tune the current flowing through M1. The M2 drain is connected to the M1 gate, and resistor R3 is connected between the gate and drain of M2. The M3 drain is connected to the M2 source, and resistor R4 is connected between the gates of M2 and M3. The M3 source is connected to terminal T PROT , and the M3 body (or back gate) is connected to a reference (REF) terminal (which is grounded in this case).

[0037] As shown, FETs M1 and M2 are arranged in a current mirror configuration and can be a matched pair (e.g., a 1:1 ratio with respect to transistor width and length) and have similar voltage thresholds (V TH , sometimes referred to as V GS ), but they do not have to be so matched. In the case where the back gate of FET M3 is connected to the REF terminal, the threshold voltage V TH of FET M3 is greater than the V TH of M1. In one example, for instance, R3 and R4 are each in the range of 10 kΩ to 200 kΩ (e.g., R3 is in the range of about 10 kΩ to 100 kΩ; R4 is in the range of about 100 kΩ to 200 kΩ), the threshold voltage V TH of FET M3 is in the range of 2 to 5 volts, and the V TH of each of M1 and M2 is in the range of 0.6 to 1 volt. The source-drain on-resistance (R SD_ON ) of M3 decreases proportionally as the voltage at terminal T PROT decreases. In this way, FET M3 acts as a variable resistor and is configured to adaptively reduce the portion of the drive potential V PROT applied at the gate of M1 by turning on in response to the voltage at terminal T DRV being lower than expected (lower than a certain voltage level). The lower the voltage at terminal T PROT , the lower the R SD_ON of M3 (the more M3 turns on). The lower the R SD_ON of M3, the lower the portion of V DRV applied to the M1 gate.

[0038] For example, assume that terminal T PROT is the start capacitor terminal of the start circuit of the switched power supply 50a, and terminal TPROT The voltage at BOOT is V under normal conditions (e.g., about 5 volts). Further assume that V DRV is about 5 to 6 volts, and the V TH of M3 is about 2 to 5 volts. Thus, in the normal operating mode, V DRV - V BOOT is less than the V TH of M3 (e.g., 6 volts - 5 volts = 1 volt, which is less than 2 volts), and M3 is turned off or conducts very little, and thus is effectively open (e.g., the R SD_ON of M3 ≥ 1 milliohm to infinity, or is a very high resistance). Thus, M2 does not conduct current, and the M1 gate receives about 100% of V DRV .

[0039] However, in response to V DRV - V BOOT satisfying or exceeding the V TH of M3, the normal operating mode stops and M2 and M3 start to conduct, and the R SD_ON of M3 is set to be proportional to V DRV - V BOOT . Thus, as V DRV - V BOOT increases further beyond the V TH of M3, M3 turns on more (the current conducted through M2 and M3 increases as the value of V DRV - V BOOT increases). If the terminal T PROT is shorted to ground (possibly accidentally), then V DRV - V BOOT is the maximum amount it can be, and the R SD_ON of M3 is the lowest amount it can be (e.g., < 1 ohm, or very small relative to the impedance at the M1 gate). In the case where M2 and M3 are conducting, a variable voltage divider is formed, which allows the amount of V DRV applied to the M1 gate to vary proportionally with respect to the voltage at the terminal T PROT . For example, in the case where the terminal T PROT is shorted to ground, the current from the V DRV potential seeks the lower resistance path through M2 and M3 (relative to the high impedance path to the M1 gate), and the M1 gate thus receives about 0% or some other relatively small amount of V DRV . For a non - zero (non - short) voltage value at the terminal T PROT , the M1 gate can receive a proportional amount of V DRV (some value between about 0 volts and the full V DRV potential). Thus, control is provided over the V INAdaptive limiting of supply current.

[0040] like Figure 3 As further shown in the dashed circle, some embodiments of the switching power supply 50a may include a circuit coupled to a terminal T PROT The switch S is connected between the source of M1 and M3. The switch can be controlled by the control signal C. For example, when it is desired to connect the terminal T PROT The control signal C can be activated when disconnected from the active power source, such as when a desired startup capacitor is connected or some other situation (e.g., detecting the value of the connected startup capacitor). This switching circuit can further help reduce the terminal T during field testing or assembly operations. PROT Overcurrent condition at.

[0041] Figure 4 A schematic diagram of a switching power supply 50b configured with an adaptive current limiting circuit in another example is shown. As shown in the figure, the switching power supply 50b generally includes a regulation core 51 and an adaptive current limiting circuit 55b. The other parts of the switching power supply 50b (such as the switching core) are arranged in a Figure 4 Not shown in , but in Figure 7A -B. Adjust the core 51 to Figure 2 A similar approach as shown in is configured as a voltage follower, and the above description is also applicable here.

[0042] The adaptive current limiting circuit 55b of this example is similar to Figure 3 The adaptive current limiting circuit 55a is the same as that of the embodiment of the present invention, except that the circuit 55b includes three series-connected n-channel FETs M3, M4, and M5 instead of the n-channel FET M3, and four series-connected resistors R4, R5, R6, and R7 instead of the resistor R4. Figure 3 The description of the related circuit 55b is also applicable here. In a similar manner to the circuit 55a, the adaptive current limiting circuit 55b operates so that the output voltage V of the amplifier AMP1 applied to the gate of the FET M1 is DRV The percentage or ratio can be based on the terminal T PROT The voltage level at which the

[0043] For example, in this example, the current limiting circuit 55b further includes resistors R4, R5, R6, and R7 operatively coupled to n-channel FETs M2 to M5 connected in series between the gate of FET M1 and terminal T PROTBetween. More specifically, resistors R3, R4, R5, R6, and R7 are connected in series with each other between the output of AMP1 and the gate of M1, and can be used to fine-tune the current flowing through M1. The drain of M2 is connected to the gate of M1, and R3 is connected between the gate and drain of M2. The drain of M3 is connected to the source of M2, and R5 is connected between the gates of M2 and M3. The drain of M4 is connected to the source of M3, and R6 is connected between the gates of M3 and M4. The drain of M5 is connected to the source of M4, and R7 is connected between the gates of M4 and M5. The source of M5 is connected to terminal T PROT , and the body (or back gate) of each of M3, M4, and M5 is connected to a reference (REF) terminal (which is grounded in this case). R4 is connected between the output of AMP1 and the gate of M5.

[0044] As described above with reference to Figure 3 , FETs M1 and M2 are arranged in a current mirror configuration and can be a matched pair (e.g., with a 1:1 ratio with respect to transistor width and length) and have similar voltage thresholds (V TH , sometimes referred to as V GS ), but they do not have to be so matched. In the case where the back gates of FETs M3, M4, and M5 are connected to the REF terminal, the threshold voltage V TH of each of said FETs is greater than the V TH of M1. In one example, for instance, R3, R4, R5, R6, and R7 are each in the range of 10 kiloohms to 200 kiloohms (e.g., each of R3, R5, R6, and R7 is in the range of about 10 kiloohms to 100 kiloohms; R4 is in the range of about 100 kiloohms to 200 kiloohms), the threshold voltage V TH of each of FETs M3, M4, and M5 is in the range of 2 to 5 volts, and the V TH of each of M1 and M2 is in the range of 0.6 to 1 volt. The source-drain on-resistance (R SD_ON ) of each of M3, M4, and M5 decreases proportionally as the voltage at terminal T PROT decreases. In this way, each of FETs M3, M4, and M5 acts as a variable resistor, and together they are configured to adaptively reduce the portion of the drive potential V Figure 3 applied at the gate of M1 in a manner similar to that described for FET M3 with reference to DRV .

[0045] Figure 5Schematic diagram showing a switched-mode power supply 50c configured with an adaptive current limit circuit in another example. As shown, the switched-mode power supply 50b generally includes a regulation core 51 and an adaptive current limit circuit 55c. Other parts of the switched-mode power supply 50c (such as the switching core) are not shown in Figure 5 but are shown in Figure 7A -B. The regulation core 51 is configured as a voltage follower in a manner similar to that shown in Figure 2 , and the relevant description above also applies here.

[0046] The adaptive current limit circuit 55c of this example is similar to the adaptive current limit circuit 55a of Figure 3 , except that the circuit 55c includes three n-channel FETs M3, M4, and M5 connected in parallel instead of the FET n-channel M3, and three resistors R4, R5, and R6 connected in series instead of the resistor R4. The relevant description above regarding Figure 3 also applies here. In a manner similar to the circuit 55a, the adaptive current limit circuit 55c operates such that the output voltage V of the amplifier AMP1 applied to the gate of the FET M1 DRV as a percentage or proportion can vary based on the voltage level at the terminal T PROT .

[0047] For example, in this example, the current limit circuit 55c further includes resistors R3 to R6 operatively coupled to the n-channel FETs M2 to M5. M2 is connected in series with the parallel combination of M3 to M6 between the gate of the FET M1 and the terminal T PROT . More specifically, the resistors R3, R4, R5, and R6 are connected in series with each other between the output of AMP1 and the gate of M1, and can be used to fine-tune the current flowing through M1. The drain of M2 is connected to the gate of M1, and the resistor R3 is connected between the gate and the drain of M2. The drain of M3 is connected to the source of M2, and the resistor R4 is connected between the gates of M2 and M3. The drain of M4 is connected to the drain of M3, and the resistor R5 is connected between the gates of M3 and M4. The drain of M5 is connected to the drain of M4, and the resistor R6 is connected between the gates of M4 and M5. The source of each of M3, M4, and M5 is connected to the terminal T PROT , and the body (or back gate) of each of M3, M4, and M5 is connected to a reference (REF) terminal (which is grounded in this case).

[0048] As described above with reference to Figure 3 , the FETs M1 and M2 are arranged in a current mirror configuration and can be a matched pair (e.g., with a ratio of 1:1 with respect to the transistor width and length) and have similar voltage thresholds (V TH, sometimes referred to as V GS ), but they do not have to match. In the case where the back gates of FETs M3, M4, and M5 are connected to the REF terminal, the threshold voltage V of each of the FETs TH is greater than V of M1 TH . In one example, for instance, R3, R4, R5, and R6 are each in the range of 10 kiloohms to 200 kiloohms (e.g., each of R3, R4, R5, and R6 is in the range of about 10 kiloohms to 100 kiloohms), the threshold voltage V of each of FETs M3, M4, and M5 TH is in the range of 2 to 5 volts, and V of each of M1 and M2 TH is in the range of 0.6 to 1 volt. The source-drain on-resistance (R SD_ON ) of each of M3, M4, and M5 decreases proportionally as the voltage at terminal T PROT decreases. In this way, each of FETs M3, M4, and M5 acts as a variable resistor, and they are together configured to adaptively reduce the drive potential V applied at the gate of M1 Figure 3 in a manner similar to that described for FET M3 above with reference to DRV .

[0049] Figure 6 FIG. shows a schematic diagram of a switched-mode power supply 50d configured with an adaptive current limit circuit in another example. As shown, the switched-mode power supply 50d generally includes a regulation core 51 and an adaptive current limit circuit 55d. Other parts of the switched-mode power supply 50d (such as the switching core) are not shown in Figure 6 , but are shown in Figure 7A -B. The regulation core 51 is configured as a voltage follower in a manner similar to that shown in Figure 2 , and the related description above applies here as well.

[0050] The adaptive current limit circuit 55d further includes an n-channel depletion or low-threshold voltage FET M1, which is configured as a source follower power supply to supply power from the input voltage terminal V DRV to terminal T IN in response to the output voltage V of the amplifier AMP1 PROT . However, the percentage or proportion of the output voltage V of the amplifier AMP1 applied to the gate of FET M1 DRV can vary based on the voltage level at terminal T PROT . For example, the example circuit 55d further includes resistors R3 and R4 operatively coupled to an n-channel FET M2, and the n-channel FET is connected in series between the M1 gate and terminal T PROTBetween. More specifically, resistors R3 and R4 are connected in series with each other between the output of AMP1 and the gate of M1, and can be used to fine-tune the current flowing through M1. The drain of M2 is connected to the gate of M1, and resistor R3 is connected between the gate and the drain of M2. The source of M2 is connected to terminal T PROT .

[0051] FETs M1 and M2 are of different sizes, where M1 is much larger than M2 (e.g., with a ratio of transistor width and length of 1000:1 or greater). Also, the threshold voltage V TH of M2 is greater than the V TH of M1. In some instances: if M1 is a depletion FET, its V TH can be in the range of -0.1 to -0.2 volts, and if M1 is a low-threshold FET, its V TH can be in the range of 0.1 to 0.2 volts; the V TH of M2 is in the range of 0.6 to 1 volt; R3 is in the range of about 1 kiloohm to 10 kiloohms; and R4 is in the range of about 100 kiloohms to 200 kiloohms. The source-drain on-resistance (R SD_ON ) of M2 decreases proportionally as the voltage at terminal T PROT decreases. In this way, FET M2 acts as a variable resistor and is configured to adaptively reduce the portion of the drive potential V PROT applied at the gate of M1 by turning on in response to the voltage at terminal T DRV being lower than expected (lower than a certain voltage level). The lower the voltage at terminal T PROT , the lower the R SD_ON of M2 (the more M2 turns on). The lower the R SD_ON of M2, the lower the portion of V DRV applied to the gate of M1.

[0052] For example, assume that terminal T PROT is the start capacitor terminal of the start circuit of a switched power supply 50d, and the voltage at terminal T PROT is V BOOT under normal conditions (e.g., about 5 volts). Further assume that V DRV is about 5 volts, and the V TH of M2 is about 0.6 volts. Thus, in the normal operating mode, V DRV - V BOOT is less than the V TH of M2 (e.g., 5 volts - 5 volts = 0 volts, which is less than 0.6 volts), and M2 is off or conducts very little, and thus is effectively open (e.g., the R SD_ON≥1 milliohm to infinity, or a very high resistance). Thus, the M1 gate receives approximately 100% of V DRV .

[0053] However, in response to V DRV -V BOOT meeting or exceeding the V TH of M2, the normal operating mode stops and M2 starts to conduct, and the R SD_ON of M2 is set to be proportional to V DRV -V BOOT . Thus, as the value of V DRV -V BOOT further increases beyond the V TH of M2, M2 turns on more (the current conducted through M2 increases as the value of V DRV -V BOOT increases). If the terminal T PROT is shorted to ground, then V DRV -V BOOT is the maximum amount it can be, and the R SD_ON of M2 is the lowest amount it can be (e.g., <1 ohm, or very small relative to the impedance at the M1 gate). When M2 is conducting, a variable voltage divider is formed, which allows the amount of V DRV applied to the M1 gate to vary proportionally with respect to the voltage at the terminal T PROT . For example, when the terminal T PROT is shorted to ground, the current originating from the V DRV potential seeks a lower resistance path through M2 (relative to the high impedance path to the M1 gate), and the M1 gate thus receives approximately 0% or some other relatively small amount of V DRV . For a non-zero (non-short) voltage value at the terminal T PROT , the M1 gate can receive a proportional amount of V DRV (some value between approximately 0 volts and the full V DRV potential). Thus, an adaptive limit on the supply current of V IN through M1 is provided.

[0054] As further shown in the dashed circle in Figure 6 , some examples of the switched power supply 50d may include a switch S coupled between the terminal T Figures 3 - 5 and the sources of M1 and M2 in a manner similar to that shown in the example of PROT , and the relevant description above applies equally here.

[0055] Figure 7AAnother detailed schematic diagram showing a switched-mode power supply 50e configured with an adaptive current limit circuit in another example. As shown, the switched-mode power supply 50e generally includes a regulation core 51, a switching core 53, and an adaptive current limit circuit 55e. The regulation core 51 is configured as a voltage follower in a manner similar to that shown in Figure 2 and the related description above applies equally here.

[0056] The switching core 53 of this example is configured as a buck converter having a low-side and a high-side switching element and corresponding driver circuits. More specifically, the high-side switching element M H is coupled between the input voltage terminal V IN and the switching node SN, and its control terminal is coupled to the output of the high-side driver HSD. The low-side switching element M L is coupled between the ground terminal and the switching node SN, and its control terminal is coupled to the output of the low-side driver LSD. A pulse width modulation (PWM) controller 703 receives a reference voltage V REF2 and a feedback voltage V OUT representing the output voltage V FB as inputs, and generates a high-side drive signal HS DRV and a low-side drive signal LS DRV respectively provided to the inputs of the high-side driver HSD and the low-side driver LSD. V REF2 can be provided, for example, by a bandgap voltage reference, and the feedback voltage V FB is generated by a voltage divider including resistors R7 and R8 connected in series between V OUT and the ground terminal. The switching elements M H and M L are both implemented with n-channel power FETs, but any number of other transistor technologies can be used. The PWM controller 703 can be implemented with any suitable PWM control scheme and circuitry.

[0057] As further shown, the positive supply terminal of the high-side driver HSD is coupled to the startup node and terminal T PROT , and the negative supply terminal of the high-side driver HSD is coupled to the switching node SN. Also, a startup capacitor is coupled between terminal T PROT and the switching node SN. The positive supply rail is provided by the adaptive current limit circuit 55e configured as shown in Figure 3 , and the related description above applies equally here. Thus, at terminal T PROTIn the case of a short circuit or high current condition occurring at [location], the current through M1 will be adaptively limited as described herein. As further shown, the positive supply terminal of the low-side driver LSD is coupled to the VCC node or terminal, and the negative supply terminal of the low-side driver LSD is coupled to ground. In some instances, the positive supply rail VCC may be provided by a second occurrence of the adaptive current limiting circuit 55e. Thus, in the case of a short circuit or high current condition occurring at the VCC node, the source current can be adaptively limited as described herein. In some such cases, the V DRV signal may be applied (shared) to each copy of the adaptive current limiting circuit 55e.

[0058] As further shown, the inductor L is coupled between the switch node SN and the output voltage terminal, and the output capacitor C OUT is coupled between V OUT and the ground terminal. For a given power supply application, any number of loads may be connected between V OUT and the ground terminal.

[0059] Figure 7B Another detailed schematic diagram of a switched-mode power supply 50f configured with an adaptive current limiting circuit in another example is shown. As shown, the switched-mode power supply 50f generally includes a regulation core 51, a switching core 53, and an adaptive current limiting circuit 55f. Each of the regulation core 51 and the switching core 53 is configured in a manner similar to that shown in Figure 3 and 7A , and the relevant description above applies here as well. In this example, the positive supply rail of the high-side driver HSD is provided by the adaptive current limiting circuit 55f configured as shown in Figure 6 , and the relevant description above applies here as well. Thus, in the case of a short circuit or high current condition occurring at the terminal T PROT , the current through M1 will be adaptively limited as described herein. As further shown, the positive supply terminal of the low-side driver LSD is coupled to the VCC node or terminal, and the negative supply terminal of the low-side driver LSD is coupled to ground. In some instances, the positive supply rail VCC may be provided by a second occurrence of the adaptive current limiting circuit 55f, such that the current supplied to the VCC terminal can also be adaptively limited as described herein. In a manner similar to that described with respect to Figure 7A , the V DRV generated by the regulation core 51 may be shared by two copies of the adaptive current limiting circuit 55f.

[0060] Other examples may include Figure 7A -B additional circuitry not shown. For example, the regulation core 51 may further include circuitry configured to generate voltage references V REF1 and VREF2 A bandgap voltage reference circuit system, a current bias generator for generating a current bias for biasing an input or node of each given design, an error amplifier for comparing voltage values, a logic circuit system for controlling operations, a current sensing circuit system, and other such functional blocks.

[0061] Figure 8A A schematic diagram showing an LDO voltage regulator 100a configured with an adaptive current limit circuit in one example. As shown, the LDO voltage regulator 100a includes a V2I circuit 102, a V REF circuit 104, a voltage difference detection circuit 106, and an LDO core 108a. The adaptive current limit circuit 110a is implemented within the LDO core 108a. The LDO voltage regulator 100a receives an input voltage V IN at its input voltage terminal and provides an output voltage V OUT at its output voltage terminal. Each of the V2I circuit 102, the V REF circuit 104, the voltage difference detection circuit 106, and the LDO core 108a can be configured in a manner similar to that described in the reference Figure 1B , where additional details of the adaptive current limit circuit 110a are provided relative to Figure 3 , and the relevant description above applies equally here.

[0062] As Figure 8A further shows, the V REF circuit 104 is configured to generate a reference voltage V BIAS for the LDO core 108a based on the bias current I REF from the V2I circuit 102. In this example, the V REF circuit 104 includes an amplifier AMP2 and a p-channel FET M4. The FET M4 is gated or otherwise controlled by the output signal V G of the AMP2. The AMP2 is configured with input resistors R P and R N on its non-inverting and inverting inputs respectively, and operates in conjunction with the bias current I BIAS to determine a reference current I REF . The I REF passes through the FET M4 and a reference resistor R EXT (which is external to the V REF circuit 104 in this example), which in turn generates a reference voltage V REF provided to the LDO core 108a.

[0063] As Figure 8A further shown, the LDO core 108a is configured to be based on V IN and VREF Provide V OUT . In this example, the LDO core 108a includes an amplifier AMP1, which is configured to generate V based on VREF (applied to the non-inverting input of AMP1) and the feedback voltage obtained at terminal T PROT (applied to the inverting input of AMP1). The output of AMP1 is applied to the adaptive current limit circuit 110a. In this example, the current limit circuit 110a includes resistors R1 and R2 operatively coupled to n-channel FETs M2 and M3, the n-channel FETs being connected in series between the gate of FET M1 and terminal T DRV . More specifically, resistors R1 and R2 are connected in series with each other between the AMP1 output and the M1 gate and can be used to fine-tune the current flowing through M1. The M2 drain is connected to the M1 gate, and resistor R2 is connected between the gate and drain of M2. The M3 drain is connected to the M2 source, and resistor R1 is connected between the AMP1 output and the gates of M2 and M3. The M3 source is connected to terminal T PROT (which is also V PROT in this example), and the M3 body (or back gate) is grounded. Output capacitor C OUT is coupled between V OUT and the ground terminal. OUT

[0064] As further shown in Figure 8A , FETs M1 and M2 are arranged in a current mirror configuration and can be a matched pair (e.g., a 1:1 ratio with respect to transistor width and length) and have similar voltage thresholds V TH , but they need not be so matched. In the case where the back gate of FET M3 is grounded, the threshold voltage V TH of FET M3 is greater than the V TH of M1. In one example, for instance, R1 and R2 are each in the range of 10 kΩ to 200 kΩ (e.g., R1 is in the range of about 100 kΩ to 200 kΩ; R2 is in the range of about 10 kΩ to 100 kΩ), the V TH of FET M3 is in the range of 2 to 5 volts, and the V TH of each of M1 and M2 is in the range of 0.6 to 1 volt. In operation, the R SD_ON of M3 decreases proportionally as the voltage at terminal T PROT decreases. In this way, M3 effectively acts as a variable resistor and adaptively reduces the portion of V PROT applied at the gate of M1 in response to the voltage at terminal T DRV being lower than expected (thus indicating a high current condition, such as a short circuit). Terminal TPROT The lower the voltage at, the lower the R of M3 SD_ON (and the more M3 is turned on). The lower the R of M3 SD_ON , the lower the portion of V applied to the gate of M1 DRV as described above with respect to Figure 1B . Thus, in response to an abnormally low voltage at terminal T PROT , the current through M1 is adaptively limited by an adaptive voltage divider provided by the operation of M3.

[0065] Figure 8B FIG. shows a schematic diagram of an LDO voltage regulator 100b configured with an adaptive current limiting circuit in another example. As shown, the LDO voltage regulator 100b is similar to Figure 8A the LDO voltage regulator 100a, except that it includes an LDO core 108b implemented with an adaptive current limiting circuit 110b. The adaptive current limiting circuit 110b is configured in a manner similar to the adaptive current limiting circuit 55d described with respect to Figure 6 . The related description above applies equally here.

[0066] As Figure 8B shown, resistors R1 and R2 are connected in series with each other between the output of AMP1 and the gate of M1, and can be used to fine-tune the current flowing through M1. The drain of M2 is connected to the gate of M1, and the resistor R2 is connected between the gate and the drain of M2. The source of M2 is connected to terminal T PROT (in this example, which is also V OUT ). FETs M1 and M2 are of different sizes, where M1 is much larger than M2 (e.g., a ratio of transistor width and length of 1000:1 or greater). Also, the V TH of M2 is greater than the V TH of M1. In some examples: if M1 is a depletion FET, its V TH can be in the range of -0.1 to -0.2 volts, and if M1 is a low-threshold FET, its V TH can be in the range of 0.1 to 0.2 volts; the V TH of M2 is in the range of 0.6 to 1 volt; R1 is in the range of about 100 kΩ to 200 kΩ; and R2 is in the range of about 1 kΩ to 10 kΩ. The R SD_ON of M2 decreases proportionally as the voltage at terminal T PROT decreases. In this way, M2 acts as a variable resistor, and adaptively reduces the portion of V applied at the gate of M1 in response to the voltage at terminal T PROT being lower than expected to turn on. The lower the voltage at terminal T DRV , the lower the R of M2 PROT ​SD_ON Lower (the more M2 is turned on). The R of M2 SD_ON is lower, and the V applied to the gate of M1 DRV is a lower portion of

[0067] Therefore, in this particular instance, terminal T PROT is the V of the LDO voltage regulator 100b OUT terminal. Assume that the voltage at terminal T PROT should be approximately 5 volts under normal conditions. Further assume that V DRV is approximately 5 volts, and the V of M2 TH is approximately 0.6 volts. Therefore, in the normal operating mode, V DRV - V BOOT is less than the V of M2 TH (e.g., 5 volts - 5 volts = 0 volts, which is less than 0.6 volts), and M2 is turned off or conducts very little, and is thus effectively open (e.g., the R of M2 SD_ON ≥1 milliohm to infinity, or is a very high resistance). Therefore, the M1 gate receives approximately 100% of V DRV .

[0068] However, in response to V DRV - V BOOT satisfying or exceeding the V of M2 TH , the normal operating mode stops and M2 begins to conduct, and the R of M2 SD_ON is set to be proportional to V DRV - V BOOT . Therefore, as V DRV - V BOOT increases further beyond the V of M2 TH , M2 turns on more (the current conducted through M2 increases as V DRV - V BOOT increases). If terminal T PROT is shorted to ground, then V DRV - V BOOT is the maximum amount it can be, and the R of M2 SD_ON is the lowest amount it can be (e.g., <1 ohm, or very small relative to the impedance at the M1 gate). When M2 is conducting, a variable voltage divider is formed, which allows the amount of V DRV applied to the M1 gate to vary proportionally with respect to the voltage at terminal T PROT . For example, in the case where terminal T PROT is shorted to ground, the current originating from the V DRV potential seeks the lower resistance path through M2 (relative to the high impedance path to the M1 gate), and the M1 gate thus receives approximately 0% or some other relatively small amount of V DRVFor terminal T PROT at a non-zero (non-shorted) voltage value, the M1 gate can receive a proportional amount of V DRV (a value between approximately 0 volts and full V DRV potential). Thus, an adaptive limit on the supply current of V IN through M1 is provided.

[0069] Method

[0070] Figure 9 illustrates a method for adaptively limiting current in a regulated power supply in one example. The method can be implemented in any number of power supply topologies and configurations (e.g., Figures 1A - 8B the example shown in TERM ) or in any other power supply having a terminal (T PROT ) supplied with voltage (V TH ) via a source follower. In this example method, it is assumed that a first transistor configured as a source follower voltage supply has a first V PROT and is coupled between a power supply rail and T TH and that a second transistor having a second V TH greater than the first V PROT is coupled between the gate of the first transistor and T DRV ). Also, the control terminals of the first and second transistors each receive a portion of a drive signal (e.g., 0% to 100% of V Figures 3 - 5 ). For the purposes of this example description, it is assumed that the first and second transistors are FETs, such as Figure 6 , M1 and M3 of the example circuit depicted in 7A or 8A, or 7B or M1 and M2 of the example circuit depicted in 8B.

[0071] At 901 and 903 respectively, the method includes receiving a gate drive signal V DRV from a voltage regulation circuit and determining whether the difference (V DRV -V TERM ) between V DRV and V TERM is greater than or equal to the V TH of the second transistor. The voltage regulation circuit can be, for example, the regulation core 51 of any one of the switched power supplies 50a-f or the amplifier AMP1 of the LDO voltage regulator 100a-b. More generally, V DRV can be provided by any circuit configured to generate a drive signal for a power supply switching element. In this example, the determination at 903 is made by the operation of the second transistor. This determination indicates whether an overcurrent (OC) condition exists on T PROT .

[0072] In response to V DRV -V TERM whose difference is not greater than or equal to the V of the second transistor TH , the second transistor remains in its off or non-conducting state, and the method continues at 905, where all (or substantially all, e.g., 90% or more) of V DRV is applied to the gate of the first transistor to supply voltage V PROT at the protected terminal T TERM . This determination and the corresponding action may indicate a normal operating mode, where there is no overcurrent condition at terminal T PROT .

[0073] In contrast, in response to V DRV -V TERM whose difference is greater than or equal to the V of the second transistor TH , the second transistor turns on or otherwise begins to conduct, and the method continues at 907 and 909 respectively, where an adaptive voltage divider is engaged to reduce the portion of V DRV applied to the gate of the first transistor, and the voltage divider is adjusted based on the value of V DRV -V TERM to further reduce the portion of V DRV applied to the gate of the first transistor (source follower power supply). This determination and the corresponding action may indicate an abnormal operating mode, where there is an overcurrent condition at terminal T PROT .

[0074] In this example, an adaptive voltage divider is effectively provided by the operation of the second transistor having an R SD_ON value, and the R SD_ON value decreases proportionally as the V TERM value decreases. In this way, the second transistor effectively acts as a variable resistor. The lower the value of V PROT at terminal T TERM , the lower the R SD_ON value of the second transistor (and the more the second transistor turns on). The lower the R SD_ON value of the second transistor, the lower the portion of V DRV applied to the gate of the first transistor. Thus, in response to an abnormally low value of V PROT at terminal T TERM , the current passing through the first transistor is adaptively limited by the adaptive voltage divider provided by the operation of the second transistor.

[0075] Additional examples

[0076] Example 1 is a power supply circuit, the power supply circuit comprising: an amplifier having an amplifier output, the amplifier being configured to provide a drive potential at the amplifier output; a first transistor coupled between a voltage supply terminal and an output terminal, the first transistor having a first control terminal coupled to the amplifier output, and the first transistor being configured to receive at least a portion of the drive potential at the first control terminal; and a second transistor coupled between the first control terminal and the output terminal, the second transistor having a second control terminal coupled to the amplifier output. The threshold voltage of the first transistor is lower than the threshold voltage of the second transistor, and the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal in response to the voltage at the output terminal being lower than a certain voltage level by turning on the second transistor. The degree to which the second transistor turns on can vary based on the magnitude of the voltage at the output terminal.

[0077] Example 2 includes the power supply circuit according to Example 1, and further includes one or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor.

[0078] Example 3 includes the power supply circuit according to Example 1 or 2, wherein the output terminal is a startup capacitor terminal or an output voltage terminal.

[0079] Example 4 includes the power supply circuit according to any one of Examples 1 to 3, wherein the amplifier is configured as a unity follower.

[0080] Example 5 includes the power supply circuit according to any one of Examples 1 to 4, and further includes a switch coupled between the first transistor and the output terminal.

[0081] Example 6 includes the power supply circuit according to any one of Examples 1 to 5, wherein the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal by adaptively changing the channel resistance of the second transistor based on the potential difference between the drive potential and the voltage at the output terminal.

[0082] Example 7 includes the power supply circuit according to any one of Examples 1 to 6, wherein: the first and second transistors are field effect transistors (FETs); the first transistor is a depletion mode or native transistor, its drain is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal; and the second transistor is smaller than the first transistor, and its drain is coupled to the gate of the first transistor and its source is coupled to the output terminal, and its gate is the second control terminal.

[0083] Example 8 includes the power supply circuit according to any one of Examples 1 to 6, wherein: the first and second transistors are field effect transistors (FETs); the drain of the first transistor is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal; and the source of the second transistor is coupled to the output terminal, its body terminal is coupled to the reference terminal, and its gate is the second control terminal.

[0084] Example 9 includes the power supply circuit according to any one of Examples 1 to 8, wherein the power supply circuit is a buck converter circuit or a low dropout (LDO) voltage regulator circuit.

[0085] Example 10 is an integrated circuit package that includes the power supply circuit according to any one of Examples 1 to 9, wherein the output terminal is a pin or pad of the integrated circuit package.

[0086] Example 11 is a power supply circuit that includes: an amplifier having an amplifier output and a voltage reference input; a first transistor coupled between the voltage supply terminal and the output terminal, the first transistor having a first control terminal coupled to the amplifier output; a second transistor coupled between the first transistor and the output terminal, the second transistor having a second control terminal coupled to the amplifier output; and a third transistor coupled between the second transistor and the output terminal, the third transistor having a third control terminal and a body terminal, the third control terminal being coupled to the amplifier output, and the body terminal being coupled to the reference terminal.

[0087] Example 12 includes the power supply circuit according to Example 11, and further includes a first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; and / or a second resistor coupled between the second control terminal of the second transistor and the third control terminal of the third transistor.

[0088] Example 13 includes the power supply circuit according to Example 11 or 12, wherein the output terminal is a start capacitor terminal, and the reference terminal is a ground terminal.

[0089] Example 14 includes the power supply circuit according to any one of Examples 11 to 13, wherein the amplifier is configured as a unity follower.

[0090] Example 15 includes the power supply circuit according to any one of Examples 11 to 14, and further includes: one or more fourth transistors coupled between the third transistor and the output terminal, each of the one or more fourth transistors having a corresponding control terminal coupled to the amplifier output and a corresponding body terminal coupled to the reference terminal; and a resistor coupled between the third control terminal of the third transistor and the one or more control terminals of the one or more fourth transistors.

[0091] Example 16 includes the power supply circuit according to any one of Examples 11 to 14, and further includes: one or more fourth transistors coupled in parallel with the third transistor, each of the one or more fourth transistors having a corresponding control terminal coupled to the amplifier output and a corresponding body terminal coupled to the reference terminal; and a resistor coupled between the third control terminal of the third transistor and the one or more control terminals of the one or more fourth transistors.

[0092] Example 17 includes the power supply circuit according to any one of Examples 11 to 16, and further includes a switch coupled between the first transistor and the output terminal.

[0093] Example 18 includes the power supply circuit according to any one of Examples 11 to 17, wherein: the first, second, and third transistors are field effect transistors (FETs); the drain of the first transistor is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal coupled to the amplifier output; the drain of the second transistor is coupled to the gate of the first transistor and its source is coupled to the drain of the third transistor, and its gate is the second control terminal coupled to the amplifier output; and the source of the third transistor is coupled to the output terminal, and its gate is the third control terminal coupled to the amplifier output, and its back gate is the body terminal coupled to the reference terminal.

[0094] Example 19 includes the power supply circuit according to Example 18, wherein the first, second, and third transistors are n-channel field effect transistors (NFETs), and the power supply circuit further includes: a first resistor coupled between the gate of the first transistor and the gate of the second transistor; and a second resistor coupled between the gate of the second transistor and the gate of the third transistor.

[0095] Example 20 includes the power supply circuit according to any one of Examples 11 to 19, wherein the power supply circuit is part of a buck converter circuit or a low dropout (LDO) voltage regulator circuit.

[0096] Example 21 is an integrated circuit package that includes a power supply circuit according to any one of Examples 11 to 20, where the output terminal is a pin or pad of the integrated circuit package.

[0097] Example 22 is a power supply circuit that includes: an amplifier having an amplifier output and a voltage reference input; a first transistor coupled between a voltage supply terminal and an output terminal, the first transistor having a first control terminal coupled to the amplifier output; and a second transistor coupled between the first control terminal and the output terminal, the second transistor having a second control terminal coupled to the amplifier output; where the threshold voltage of the first transistor is lower than the second threshold voltage of the second transistor.

[0098] Example 23 includes the power supply circuit according to Example 22 and further includes: a first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; and / or a second resistor coupled between the second control terminal of the second transistor and the amplifier output.

[0099] Example 24 includes the power supply circuit according to Example 22 or 23, where the output terminal is a start capacitor terminal or an output voltage terminal.

[0100] Example 25 includes the power supply circuit according to any one of Examples 22 to 24, where the amplifier is configured as a unity follower.

[0101] Example 26 includes the power supply circuit according to any one of Examples 22 to 25 and further includes a switch coupled between the first transistor and the output terminal.

[0102] Example 27 includes the power supply circuit according to any one of Examples 22 to 24, where: the first and second transistors are field effect transistors (FETs); the first transistor is a depletion mode or native transistor, its drain is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal coupled to the amplifier output; and the second transistor is smaller than the first transistor, and its drain is coupled to the gate of the first transistor and its source is coupled to the output terminal, and its gate is the second control terminal coupled to the amplifier output.

[0103] Example 28 includes the power supply circuit according to Example 27, where the first and second transistors are n-channel field effect transistors (NFETs), and the size ratio of the first transistor to the second transistor is 1000:1 or higher.

[0104] Example 29 includes a power supply circuit according to any one of Examples 22 to 28, wherein the power supply circuit is part of a buck converter circuit or a low dropout (LDO) voltage regulator circuit.

[0105] Example 30 includes an integrated circuit package that includes a power supply circuit according to any one of Examples 22 to 29, wherein the output terminal is a pin or pad of the integrated circuit package.

[0106] Example 31 is a method for adaptively limiting current in a regulated power supply having a terminal (T TERM ) supplied with a voltage (V PROT ), the regulated power supply further including a first transistor and a second transistor, the first transistor having a first V TH and coupled between a power supply rail and T PROT , and the second transistor having a second V TH greater than the first V TH and coupled between the gate of the first transistor and T PROT . The method includes: receiving a gate drive signal V DRV from a voltage regulation circuit. In response to the difference between V DRV and V TERM being not greater than or equal to the V TH of the second transistor, the method includes applying substantially all of V DRV to the gate of the first transistor. In response to the difference between V DRV and V TERM being greater than or equal to the V TH of the second transistor, the method includes: engaging an adaptive voltage divider to reduce the portion of V DRV applied to the gate of the first transistor, and adjusting the voltage divider based on the value of V DRV - V TERM to further reduce the portion of V DRV applied to the gate of the first transistor.

[0107] Example 32 includes the method according to Example 31, wherein the lower the value of V PROT at terminal T TERM , the more the second transistor turns on.

[0108] Example 33 includes the method according to Example 32 or 33, wherein: the lower the value of V PROT at terminal T TERM , the lower the R SD_ON value of the second transistor; and the lower the R SD_ON value of the second transistor, the lower the portion of V DRV applied to the gate of the first transistor.

[0109] In this specification, the term "coupled" may encompass a connection, a communication, or a signal path that implements a functional relationship in accordance with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0110] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed via firmware and / or software programming of the device, via the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0111] As used herein, the terms "terminal", "node", "interconnection", "pin", and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection or an end thereof between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0112] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device and may be adapted to be coupled to at least some of the passive elements and / or the sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0113] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. Further, the device may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0114] As used herein, a field effect transistor (FET) being "on" means that a conducting channel of the FET exists and a drain current can flow through the FET. As used herein, a FET being "off" means that a conducting channel of the FET does not exist and a drain current does not flow through the FET. However, an off FET may have a current flowing through the body diode of the transistor.

[0115] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide a certain amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0116] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately", or "substantially" in front of a parameter means within + / - 10% of the parameter.

[0117] Modifications are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A power supply circuit, comprising: An amplifier having an amplifier output, the amplifier being configured to provide a drive potential at the amplifier output; A first transistor coupled between a voltage supply terminal and an output terminal, the first transistor having a first control terminal coupled to the amplifier output, and the first transistor being configured to receive at least a portion of the drive potential at the first control terminal; And A second transistor coupled between the first control terminal and the output terminal, the second transistor having a second control terminal coupled to the amplifier output; Wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor, and the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal by the second transistor turning on in response to a voltage at the output terminal being lower than a certain voltage level.

2. The power supply circuit according to claim 1, further comprising: One or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor.

3. The power supply circuit according to claim 1, wherein the output terminal is a start capacitor terminal or an output voltage terminal.

4. The power supply circuit according to claim 1, wherein the amplifier is configured as a unity follower.

5. The power supply circuit according to claim 1, further comprising a switch coupled between the first transistor and the output terminal.

6. The power supply circuit according to claim 1, wherein the second transistor is configured to adaptively reduce the portion of the drive potential at the first control terminal by adaptively changing a channel resistance of the second transistor based on a potential difference between the drive potential and the voltage at the output terminal.

7. The power supply circuit according to claim 1, wherein: The first and second transistors are field effect transistors (FETs); The first transistor is a depletion mode or native transistor, its drain is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal; and The second transistor is smaller than the first transistor, its drain is coupled to the gate of the first transistor and its source is coupled to the output terminal, and its gate is the second control terminal.

8. The power supply circuit according to claim 1, wherein: The first and second transistors are field effect transistors (FETs); The drain of the first transistor is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal; and The source of the second transistor is coupled to the output terminal, its body terminal is coupled to a reference terminal, and its gate is the second control terminal.

9. The power supply circuit according to claim 1, wherein the power supply circuit is a buck converter circuit or a low dropout (LDO) voltage regulator circuit.

10. An integrated circuit package, comprising the power supply circuit according to claim 1, wherein the output terminal is a pin or pad of the integrated circuit package.

11. A power supply circuit, comprising: an amplifier having an amplifier output and a voltage reference input; a first transistor coupled between a voltage supply terminal and an output terminal, the first transistor having a first control terminal coupled to the amplifier output; a second transistor coupled between the first transistor and the output terminal, the second transistor having a second control terminal coupled to the amplifier output; and a third transistor coupled between the second transistor and the output terminal, the third transistor having a third control terminal and a body terminal, the third control terminal being coupled to the amplifier output and the body terminal being coupled to a reference terminal.

12. The power supply circuit according to claim 11, comprising: a first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; and / or a second resistor coupled between the second control terminal of the second transistor and the third control terminal of the third transistor.

13. The power supply circuit according to claim 11, wherein the output terminal is a start capacitor terminal and the reference terminal is a ground terminal.

14. The power supply circuit according to claim 11, further comprising: one or more fourth transistors coupled between the third transistor and the output terminal, each of the one or more fourth transistors having a respective control terminal coupled to the amplifier output and a respective body terminal coupled to the reference terminal; and a resistor coupled between the third control terminal of the third transistor and the one or more control terminals of the one or more fourth transistors.

15. The power supply circuit according to claim 11, further comprising; one or more fourth transistors coupled in parallel with the third transistor, each of the one or more fourth transistors having a respective control terminal coupled to the amplifier output and a respective body terminal coupled to the reference terminal; and a resistor coupled between the third control terminal of the third transistor and the one or more control terminals of the one or more fourth transistors.

16. The power supply circuit according to claim 11, wherein: the first, second, and third transistors are field effect transistors (FETs); the drain of the first transistor is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is the first control terminal coupled to the amplifier output; the drain of the second transistor is coupled to the gate of the first transistor, and its source is coupled to the drain of the third transistor, and its gate is the second control terminal coupled to the amplifier output; and The source of the third transistor is coupled to the output terminal, its gate is coupled to the third control terminal of the amplifier output, and its back gate is coupled to the body terminal of the reference terminal.

17. The power supply circuit according to claim 16, wherein the first, second, and third transistors are n-channel field effect transistors (NFETs), and the power supply circuit further comprises: A first resistor coupled between the gate of the first transistor and the gate of the second transistor; And A second resistor coupled between the gate of the second transistor and the gate of the third transistor.

18. A power supply circuit comprising: An amplifier having an amplifier output and a voltage reference input; A first transistor coupled between a voltage supply terminal and an output terminal, the first transistor having a first control terminal coupled to the amplifier output; And A second transistor coupled between the first control terminal and the output terminal, the second transistor having a second control terminal coupled to the amplifier output; Wherein the threshold voltage of the first transistor is lower than the second threshold voltage of the second transistor.

19. The power supply circuit according to claim 18, comprising: A first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; And / or A second resistor coupled between the second control terminal of the second transistor and the amplifier output.

20. The power supply circuit according to claim 18, wherein the output terminal is a start capacitor terminal or an output voltage terminal.

21. The power supply circuit according to claim 18, wherein: The first and second transistors are field effect transistors (FETs); The first transistor is a depletion mode or native transistor, its drain is coupled to the voltage supply terminal and its source is coupled to the output terminal, and its gate is coupled to the first control terminal of the amplifier output; and The second transistor is smaller than the first transistor, its drain is coupled to the gate of the first transistor and its source is coupled to the output terminal, and its gate is coupled to the second control terminal of the amplifier output.

22. The power supply circuit according to claim 21, wherein the first and second transistors are n-channel field effect transistors (NFETs), and the size ratio of the first transistor to the second transistor is 1000:1 or higher.

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