Silicon carbide p-channel metal oxide semiconductor field effect transistor and silicon carbide complementary metal oxide semiconductor device

Abstract

This SiC p-channel MOSFET is provided with: a SiC substrate (10), the surface of which has a planar orientation (0001); and a fin section (100) formed of SiC and protruding perpendicularly with respect to the surface of the SiC substrate, the fin section having a source region (30), a drain region (40), and a channel region (50) sandwiched between the source region and the drain region, a gate electrode (70) being formed across a side surface and an upper surface of the channel region with a gate oxide film (60) interposed therebetween, and a side surface of the channel region (50) being configured from a (1-100) plane.

Description

Technical Field

[0001] The present invention relates to a silicon carbide p-channel metal oxide semiconductor field effect transistor (MOSFET) using a silicon carbide (SiC) substrate, and a silicon carbide complementary metal oxide semiconductor (MOS) device. Background Art

[0002] In a MOS type transistor (SiC MOSFET) using an SiC substrate, when a SiO2 film (gate oxide film) is formed on the surface of the SiC substrate by thermal oxidation, the channel mobility of the SiC MOSFET is low because the defect density at the interface between the SiO2 film and the SiC substrate is high.

[0003] Non-Patent Document 1 discloses the following method: in order to improve the channel mobility, after forming a SiO2 film on the surface of the SiC substrate by thermal oxidation, heat treatment is performed in a NO (nitric oxide) gas atmosphere to nitride the interface between the SiO2 film and the SiC substrate, thereby reducing the defect density at the interface between the SiO2 film and the SiC substrate.

[0004] Non-Patent Document 1: G.Y. Chung et al., IEEE Electron Device Lett., vol. 22, 176 (2001) Summary of the Invention

[0005] -Technical Problem to be Solved by the Invention-

[0006] In a complementary MOS device composed of an n-channel MOSFET and a p-channel MOSFET, no current flows except during switching, and the static power consumption is almost zero. Therefore, it becomes a basic device in SiC integrated circuits.

[0007] However, in a SiC MOSFET, the channel mobility of the p-channel MOSFET is significantly smaller than that of the n-channel MOSFET. Therefore, the characteristics of the p-channel MOSFET become an important factor limiting the performance of the complementary MOS device, and it is necessary to realize a p-channel MOSFET with a large channel mobility.

[0008] An object of the present invention is to provide a SiC p-channel MOSFET with a large channel mobility.

[0009] -Technical Solution for Solving the Technical Problem-

[0010] The SiC p-channel MOSFET according to the present invention includes: a SiC substrate with a surface plane orientation of (0001); and fin portions formed of SiC that protrude perpendicularly to the surface of the SiC substrate. The fin portions have a source region, a drain region, and a channel region sandwiched between the source region and the drain region. A gate electrode is formed across the side surface and the upper surface of the channel region with a gate oxide film interposed therebetween, and the side surface of the channel region is composed of a (1-100) plane.

[0011] - Effects of the Invention -

[0012] According to the present invention, it is possible to provide a SiC p-channel MOSFET with a large channel mobility. Description of the Drawings

[0013] Figure 1 A diagram showing the structure of a fabricated planar p-channel MOSFET;

[0014] Figure 2 In (A) and (B) are graphs showing the measurement results of the channel mobility of a p-channel MOSFET with a channel plane orientation of (1-100);

[0015] Figure 3 In (A) and (B) are graphs showing the measurement results of the channel mobility of a p-channel MOSFET with a channel plane orientation of (11-20);

[0016] Figure 4 Is a graph showing the crystal plane dependence of the channel mobility;

[0017] Figure 5 Is a graph showing the channel direction dependence of the channel mobility;

[0018] Figure 6 Is a perspective view schematically showing the structure of the fin-type p-channel MOSFET in the present embodiment;

[0019] Figure 7 Is in Figure 6 A perspective view of the p-channel MOSFET shown with the gate oxide film and the gate electrode omitted;

[0020] Figure 8 Is along Figure 6 A cross-sectional view taken along line VIII-VIII in

[0021] Figure 9 Is along Figure 6 A cross-sectional view taken along line IX-IX in

[0022] Figure 10 Is a diagram showing the crystal orientation of the SiC crystal;

[0023] Figure 11 It is a diagram showing an orientation plane representing the <1-100> direction formed on a SiC substrate;

[0024] Figure 12 Among (A) to (C), they are diagrams illustrating the manufacturing method of the SiC p-channel MOSFET in this embodiment;

[0025] Figure 13 Among (A) to (C), they are diagrams illustrating the manufacturing method of the SiC p-channel MOSFET in this embodiment;

[0026] Figure 14 It is a perspective view schematically showing the structure of the SiC complementary MOS device in this embodiment;

[0027] Figure 15 It is on Figure 14 A perspective view of the SiC complementary MOS device shown, with the gate oxide film and gate electrode omitted. Detailed implementation manners

[0028] The inventor of the present application used a SiC substrate with surface plane orientations of (11-20) and (1-100), and trial-produced a planar p-channel MOSFET as Figure 1 shown, and studied the crystal plane dependence of the channel mobility. In a planar MOSFET, the surface plane orientation of the SiC substrate becomes the plane orientation of the channel region. It should be noted that in crystallography, a "-" (horizontal line) is added above the number to represent the negative index of the crystal plane, but in this specification, for ease of description, a "-" (negative sign) is added in front of the number to represent the index.

[0029] A planar p-channel MOSFET was fabricated by the following method.

[0030] An n-type region 210 with an n-type impurity (nitrogen) concentration of 5×10 15 to 8×10 17 cm -3 was formed on the n-type SiC substrate 200, and then a p-type source region 220 and a drain region 230 were formed on the surface of the n-type region 210. The channel region 240 is formed between the source region 220 and the drain region 230. Then, after forming a gate oxide film 250 with a thickness of 40 nm by thermal oxidation on the surfaces of the source region 220, the drain region 230, and the channel region 240, heat treatment was performed in a NO (nitric oxide) gas atmosphere, and finally, a gate electrode 260, a source electrode 270, and a drain electrode 280 were formed. It should be noted that the channel length is 100 μm and the channel width is 50 μm.

[0031] Figure 2 of (A), (B), and Figure 3 of (A), (B) are graphs showing the measurement results of measuring the channel mobility (drain voltage: -0.1 V) of the fabricated p-channel MOSFET, where Figure 2 of (A), (B) show the case where the plane orientation of the channel surface is (1 - 100), while Figure 3 of (A), (B) show the case where the plane orientation of the channel surface is (11 - 20). Figure 2 of (A), Figure 3 of (A) shows the case where the channel direction (the direction of the drain current) is perpendicular to the c-axis <0001> direction, while Figure 2 of (B), Figure 3 of (B) shows the case where the channel direction is parallel to the c-axis <0001> direction. In Figure 2 of (A), (B), the curves indicated by arrows A, B, and C respectively show that the impurity concentration (channel concentration) of the channel region 240 is 1×10 16 cm -3 , 5×10 16 cm -3 , 4×10 17 cm -3 of the case. In Figure 3 of (A), (B), the curves indicated by arrows A, B, and C respectively show that the impurity concentration (channel concentration) of the channel region 240 is 5×10 15 cm -3 , 8×10 16 cm -3 , 8×10 17 cm -3 of the case.

[0032] <Channel mobility's crystal plane dependence>

[0033] Figure 4 is based on Figure 2 of (A) and Figure 3 of (A) shows a graph of the crystal plane dependence of the channel mobility based on the measurement results. The horizontal axis shows the channel concentration, and the vertical axis shows the maximum value of the channel mobility when the channel direction is perpendicular to the c-axis. The curve represented by squares shows the case where the plane orientation of the channel surface is (1 - 100), and the curve represented by triangles shows the case where the plane orientation of the channel surface is (11 - 20). It should be noted that for the sake of comparison, the curve represented by circles shows the case where the plane orientation of the channel surface is (0001).

[0034] <Channel mobility's channel direction dependence>

[0035] Figure 5 is based on Figure 2of (A), (B) and Figure 3 The measurement results shown in (A) and (B) of the figure show a graph of the channel direction dependence of the channel mobility. The horizontal axis shows the channel concentration, and the vertical axis shows the maximum value of the channel mobility. The curve represented by squares shows the case where the plane orientation of the channel surface is (1-100), and the curve represented by triangles shows the case where the plane orientation of the channel surface is (11-20). The curve shown by the solid line shows the case where the channel direction is perpendicular to the c-axis, and the curve shown by the dotted line shows the case where the channel direction is parallel to the c-axis.

[0036] As Figure 4 shown, it can be seen that the channel mobility when the plane orientation of the channel surface is (1-100) is greater than the channel mobility when the plane orientation of the channel surface is (11-20). As Figure 5 shown, it can be seen that even when the plane orientation of the channel surface is the same, the channel mobility when the channel direction is perpendicular to the c-axis is greater than the channel mobility when the channel direction is parallel to the c-axis.

[0037] That is to say, if a p-channel MOSFET with a plane orientation of the channel surface of (1-100) and a channel direction perpendicular to the c-axis can be fabricated, a p-channel MOSFET with a large channel mobility can be realized.

[0038] The above measurement results were obtained by fabricating the Figure 1 shown planar MOSFET using a SiC substrate with the same plane orientation as the channel surface and performing measurements. However, due to the ease of achieving large diameter and high-quality crystal growth, etc., as the SiC substrate used in the mass production process, a SiC substrate with a plane orientation of (0001) on the surface is mostly used. Therefore, if a planar MOSFET is fabricated using a SiC substrate with a plane orientation of (0001) on the surface, a p-channel MOSFET with a plane orientation of the channel surface of (1-100) and a channel direction perpendicular to the c-axis cannot be realized.

[0039] The present invention provides a fin-type SiC p-channel MOSFET that uses a SiC substrate with a plane orientation of (0001) on the surface and has a structure in which the plane orientation of the channel surface is (1-100) and the channel direction is perpendicular to the c-axis.

[0040] <Structure of Fin-Type p-Channel MOSFET>

[0041] Figure 6 is a perspective view schematically showing the structure of the fin-type p-channel MOSFET in the present embodiment. Figure 7 is a perspective view in which the gate oxide film and the gate electrode are omitted based on the Figure 6 shown p-channel MOSFET. Figure 8 is along Figure 6Cross-sectional view taken along line VIII-VIII. Figure 9 It is along Figure 6 Cross-sectional view taken along line IX-IX.

[0042] like Figures 6 to 9 As shown, the p-channel MOSFET in this embodiment includes: an n-type SiC substrate 10 having a surface orientation of (0001); and a SiC fin 100 protruding perpendicularly from the surface of the SiC substrate 10. The fin 100 includes a p-type source region 30, a p-type drain region 40, and an n-type channel region 50 sandwiched between the source region 30 and the drain region 40. A field oxide film 20 is formed on the surface of the SiC substrate 10, and the fin 100 is formed from the SiC substrate 10 through the field oxide film 20. A gate electrode 70 is formed across the side and top surfaces of the channel region 50 via a gate oxide film 60. A source electrode 80 and a drain electrode 90 are formed on the top surfaces of the source region 30 and the drain region 40.

[0043] Figure 10 is a diagram showing the crystal orientation of SiC crystal. Figure 10 As shown in FIG, the (1-100) plane is a plane perpendicular to the (0001) plane. Therefore, the fin 100 is formed to protrude perpendicularly relative to the surface of the SiC substrate 10, so that the side surface (channel surface) of the channel region 50 is composed of the (1-100) plane. Figure 7 As shown, the drain current I D The direction of is parallel to the surface of SiC substrate 10 , and thus the channel direction is perpendicular to the c-axis.

[0044] Therefore, in Figure 6 In the SiC p-channel MOSFET having the structure shown, the channel plane has a plane orientation of (1-100) and the channel direction is perpendicular to the c-axis, thereby realizing a p-channel MOSFET with high channel mobility.

[0045] It should be noted that if Figure 10 As shown, the (11-20) plane is also perpendicular to the (0001) plane, and therefore the fin 100 needs to be formed on the surface of the SiC substrate 10 so that the side surface of the channel region 50 becomes the (1-100) plane.

[0046] As a specific method, for example, Figure 11As shown, an orientation plane 11 indicating the <1-100> direction is generally formed on a commercially available SiC(0001) substrate (wafer) 10. Therefore, by forming the fin portion 100 to extend in a direction parallel to the orientation plane 11, the side surface (channel surface) of the channel region 50 can be made into a (1-100) plane. It should be noted that instead of the orientation plane 11, a notch indicating the <1-100> direction may be formed.

[0047] It should be noted that in the SiC crystal, the (01-10) plane and the (10-10) plane that intersect the (1-100) plane at an angle of 60 degrees are also equivalent to the (1-100) plane. Therefore, as Figure 11 shown, the fin portion 100 may also be formed to extend in a direction intersecting the orientation plane 11 at an angle of 60 degrees.

[0048] In this specification, when referring to the channel plane (1-100), it means including the (01-10) plane and the (10-10) plane that are equivalent to the (1-100) plane.

[0049] <Manufacturing method of SiC p-channel MOSFET>

[0050] Refer to Figure 12 (A)-(C) of Figure 13 and (A)-(C) of

[0051] to describe the manufacturing method of the SiC p-channel MOSFET in this embodiment. It should be noted that the manufacturing method of the SiC p-channel MOSFET is not limited to this.

[0051] First, as Figure 12 (A) of Figure 11 shown, an n-type SiC substrate 10 with a surface plane orientation of (0001) is prepared. As

[0052] shown, the SiC substrate 10 can be a wafer-shaped substrate.

[0052] Next, as Figure 12 (B) of

[0053] shown, using photolithography, p-type impurities (aluminum or boron) are selectively ion-implanted into the surface of the SiC substrate 10 to form p-type source regions 30 and drain regions 40. It should be noted that, if necessary, n-type impurities (nitrogen or phosphorus) may also be selectively ion-implanted into the n-type channel region 50 sandwiched between the source region 30 and the drain region 40.

[0053] Next, as Figure 12As shown in (C), using photolithography, the source region 30, the channel region 50, and the drain region 40 are selectively etched to form the fin 100. At this time, the surface of the SiC substrate 10 is etched simultaneously so that a part 12 of the SiC substrate 10 remains directly below the fin 100. As the etching for forming the fin 100, reactive ion etching using plasma is generally used.

[0054] It should be noted that the upper surface of the fin 100 also becomes the channel surface, but since its surface orientation is (0001), it does not contribute to the improvement of the channel mobility. Therefore, as Figure 13 shown in (A), when the height of the side surface of the fin 100 is set to H and the width of the upper surface is set to W, the aspect ratio (H / W) is preferably 2 or more. If the aspect ratio is less than 2, the contribution of the channel surface at the upper surface of the fin 100 to the channel mobility is relatively large, and the effect of the present invention becomes small. It should be noted that there is no strict limitation on the width of the fin 100, but it is preferably about 0.05 - 2 μm.

[0055] Next, as Figure 13 shown in (A), a field oxide film 20 is selectively formed on the surface of the SiC substrate 10 other than the fin 100. Specifically, after depositing a SiO2 film on the entire surface by chemical vapor deposition, the SiO2 film on the upper surface and the side surface of the fin 100 is removed using photolithography.

[0056] Next, as Figure 13 shown in (B), a gate oxide film 60 is selectively formed so as to straddle the side surface and the upper surface of the channel region. Specifically, after forming a thermal oxide film on the side surface and the upper surface of the fin 100, the thermal oxide film is selectively etched using photolithography, thereby enabling the formation of the gate oxide film 60. Generally, thermal oxidation is performed at a temperature of about 1150 - 1300 °C to form an oxide film with a thickness of about 5 - 80 nm. An oxide film can also be formed by a deposition method instead of thermal oxidation.

[0057] Finally, as Figure 13 shown in (C), using photolithography, a gate electrode 70 is formed so as to cover the gate oxide film 60, and a source electrode 80 and a drain electrode 90 are formed on the upper surfaces of the source region 30 and the drain region 40. Thus, the Figure 6 shown SiC p-channel MOSFET is completed. The gate electrode generally uses low-resistance polycrystalline Si, but metals such as Mo and W can also be used.

[0058] <SiC Complementary MOS Device>

[0059] In the SiC p-channel MOSFET of this embodiment, since a high channel mobility can be obtained, a SiC complementary metal-oxide-semiconductor (MOS) device can be formed by combining it with a SiC n-channel MOSFET having the same structure, thereby enabling a SiC complementary MOS device with a large transconductance and a fast switching speed.

[0060] Figure 14 FIG. is a perspective view schematically showing the structure of the SiC complementary MOS device of this embodiment. Figure 15 is in Figure 14 FIG. is a perspective view of the SiC complementary MOS device shown above with the gate oxide film and the gate electrode omitted.

[0061] As Figure 14 shown, on a SiC substrate 10 with a surface plane orientation of (0001), a SiC n-channel MOSFET and a SiC p-channel MOSFET are formed. As Figure 15 shown, including fin portions 100 formed of SiC protruding perpendicularly to the surface of the SiC substrate 10, a source region 30A, a channel region 50A, and a drain region 40A of the n-channel MOSFET, and a source region 30B, a channel region 50B, and a drain region 40B of the p-channel MOSFET are formed on the fin portions 100.

[0062] The n-channel MOSFET and the p-channel MOSFET are respectively configured such that the surface orientation of the channel plane is (1 - 100), and the channel direction is perpendicular to the c-axis.

[0063] In the n-channel MOSFET and the p-channel MOSFET, gate electrodes 70A and 70B are formed across the side surfaces and the upper surface of the channel regions 50A and 50B with a gate oxide film 60 interposed therebetween. It should be noted that the gate electrodes 70A and 70B are connected by wirings 95 formed on a field oxide film 20. On the upper surfaces of the source region 30A, the drain region 40A, the source region 30B, and the drain region 40B, source electrodes 80A, drain electrodes 90A, source electrodes 80B, and drain electrodes 90B are respectively formed. It should be noted that the drain electrodes 90A and 90B are common electrodes.

[0064] The above has described the present disclosure through preferred embodiments. However, the above content is not a limiting description, and various changes can of course be made.

[0065] -Symbol Explanation-

[0066] 10 SiC substrate

[0067] 11 Orientation plane

[0068] 20 - field oxide film

[0069] Source regions 30, 30A, 30B

[0070] Drain regions 40, 40A, 40B

[0071] Channel regions 50, 50A, 50B

[0072] 60 - gate oxide film

[0073] Gate electrodes 70, 70A, 70B

[0074] Source electrodes 80, 80A, 80B

[0075] Drain electrodes 90, 90A, 90B

[0076] 95 - wiring

[0077] 100 - fin

Claims

1. A silicon carbide p-channel metal oxide semiconductor field effect transistor, characterized in that: The silicon carbide p-channel metal oxide semiconductor field effect transistor includes: A silicon carbide substrate with a surface plane orientation of (0001); and A fin formed of silicon carbide protruding perpendicularly to the surface of the silicon carbide substrate, The fin has a source region, a drain region, and a channel region sandwiched between the source region and the drain region, A gate electrode is formed across the side surface and the upper surface of the channel region with a gate oxide film interposed therebetween, The side surface of the channel region is composed of (1-100) planes.

2. The silicon carbide p-channel metal oxide semiconductor field effect transistor according to claim 1, characterized in that: A field oxide film is formed on the surface of the silicon carbide substrate, The fin is formed by penetrating the field oxide film from the silicon carbide substrate.

3. The silicon carbide p-channel metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The direction of the current flowing in the channel region is perpendicular to the c-axis <0001> direction of the silicon carbide substrate.

4. The silicon carbide p-channel metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The silicon carbide substrate has an orientation plane representing the <1-100> direction, The fin extends along a direction parallel to the orientation plane or a direction intersecting the orientation plane at an angle of 60 degrees.

5. A silicon carbide complementary metal oxide semiconductor device, which includes a silicon carbide p-channel metal oxide semiconductor field effect transistor and a silicon carbide n-channel metal oxide semiconductor field effect transistor, characterized in that: The silicon carbide p-channel metal oxide semiconductor field effect transistor and the silicon carbide n-channel metal oxide semiconductor field effect transistor are formed on a silicon carbide substrate with a surface plane orientation of (0001), The silicon carbide p-channel metal oxide semiconductor field effect transistor has the same structure as the silicon carbide p-channel metal oxide semiconductor field effect transistor according to claim 1, The silicon carbide n-channel metal oxide semiconductor field effect transistor has the same structure as the silicon carbide p-channel metal oxide semiconductor field effect transistor, The side surfaces of the channel regions of the silicon carbide p-channel metal oxide semiconductor field effect transistor and the silicon carbide n-channel metal oxide semiconductor field effect transistor are respectively composed of (1-100) planes.

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