Silicon carbide epitaxial wafer, preparation method thereof, and semiconductor device

Abstract

The present application belongs to the field of semiconductor technology and discloses a silicon carbide epitaxial wafer, a preparation method thereof, and a semiconductor device, comprising: growing a first epitaxial layer on a side surface of a silicon carbide substrate in a first cavity; growing a second epitaxial layer on a side surface of the first epitaxial layer away from the silicon carbide substrate in a second cavity; growing a third epitaxial layer on a side surface of the second epitaxial layer away from the first epitaxial layer in the second cavity; growing a fourth epitaxial layer on a side surface of the third epitaxial layer away from the second epitaxial layer in the first cavity; and growing a fifth epitaxial layer on a side surface of the fourth epitaxial layer away from the third epitaxial layer in the second cavity, to obtain the silicon carbide epitaxial wafer; wherein the first and fourth epitaxial layers are N-type layers, and the second, third, and fifth epitaxial layers are P-type layers. As a result, the silicon carbide epitaxial wafer has high quality, low defect density, and low surface roughness, and its application in ultra-high voltage power devices is beneficial to improving device performance and yield.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide epitaxial wafer, a preparation method thereof, and a semiconductor device. Background Art

[0002] As one of the two leading third-generation semiconductor materials, silicon carbide has achieved industrialization in the field of power devices. Compared with traditional silicon-based materials, it has the advantages of high-voltage, high-temperature, and high-frequency resistance, making it particularly suitable for high-voltage and high-power devices. Currently, the mass application of silicon carbide materials in the field of power semiconductor devices is mainly concentrated in 650V / 1200V diodes (SBDs) / field-effect transistors (MOSFETs). The silicon carbide epitaxial wafer structure required is relatively simple, mainly concentrated in a single-layer structure with a film thickness of about 5μm to 10μm. The dopant type is N-type, and the doping dose is 5×10 15 atoms / cm 3 ~1×10 16 atoms / cm 3 For ultra-high voltage devices (>10kV), such as insulated gate bipolar transistors (IGBTs) and gate turn-off thyristors (GTOs), thick films (>100μm) with N-type and P-type doping at a dose of 1×10 14 atoms / cm 3 ~1×10 20 atoms / cm 3 However, when the film thickness is greater than 100 μm, the quality of the epitaxial wafer is prone to deterioration, which seriously affects the performance and yield of ultra-high voltage devices and does not meet the device design and manufacturing requirements. In addition, stable P-type lightly doped (about 10 14 atoms / cm 3 magnitude) and heavily doped (about 1×10 19 atoms / cm 3 ~1×10 20 atoms / cm 3 Therefore, the growth technology of multi-layer thick-film silicon carbide epitaxial wafers needs to be studied.

[0003] It should be noted that the above statements are only used to provide background technical information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0004] In a first aspect of the present application, the present application proposes a method for preparing a silicon carbide epitaxial wafer, comprising:

[0005] growing a first epitaxial layer on a surface of a silicon carbide substrate in a first cavity;

[0006] growing a second epitaxial layer on a surface of the first epitaxial layer away from the silicon carbide substrate in a second cavity;

[0007] growing a third epitaxial layer in the second cavity on a surface of the second epitaxial layer away from the first epitaxial layer;

[0008] growing a fourth epitaxial layer on a surface of the third epitaxial layer away from the second epitaxial layer in the first cavity;

[0009] growing a fifth epitaxial layer in the second cavity on a surface of the fourth epitaxial layer away from the third epitaxial layer to obtain the silicon carbide epitaxial wafer;

[0010] The first epitaxial layer and the fourth epitaxial layer are N-type layers, and the second epitaxial layer, the third epitaxial layer, and the fifth epitaxial layer are P-type layers.

[0011] The present application can obtain high-quality silicon carbide epitaxial wafers through the above method, which is suitable for ultra-high voltage power devices, is simple to operate, and is easy to implement industrial production.

[0012] In addition, the preparation method according to the above embodiment of the present application may also have the following additional technical features:

[0013] In some embodiments of the present application, the defect density, thickness, and doping concentration of the first epitaxial layer are measured after the first epitaxial layer is grown; the defect density, thickness, and doping concentration of the second epitaxial layer are measured after the second epitaxial layer is grown; the defect density, thickness, and doping concentration of the third epitaxial layer are measured after the third epitaxial layer is grown; the defect density, thickness, and doping concentration of the fourth epitaxial layer are measured after the fourth epitaxial layer is grown; and the defect density, thickness, and doping concentration of the fifth epitaxial layer are measured after the fifth epitaxial layer is grown. This helps solve the problem of difficulty in characterizing multi-layer thick-film epitaxial wafers.

[0014] In some embodiments of the present application, the process parameters for growing the first epitaxial layer include a nitrogen flow rate of 40 sccm to 60 sccm, a growth temperature of 1580°C to 1650°C, a growth pressure of 160 mbar to 280 mbar, a growth time of 1200 s to 2500 s, and a growth rate of 5 μm×h -1 ~10μm×h -1 Thus, a first epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0015] In some embodiments of the present application, the process parameters for growing the second epitaxial layer include: a trimethylaluminum injection rate of 0.1 sccm to 0.13 sccm, a trimethylaluminum water bath temperature of 19°C to 20°C, a growth temperature of 1600°C to 1660°C, a growth pressure of 50 mbar to 70 mbar, a growth time of 50 s to 70 s, and a growth rate of 80 μm×h -1 ~120μm×h -1 Thus, a second epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0016] In some embodiments of the present application, the process parameters for growing the third epitaxial layer include: a trimethylaluminum injection amount of 0.0003 sccm to 0.0008 sccm, a trimethylaluminum water bath temperature of 19°C to 20°C, a growth temperature of 1600°C to 1660°C, a growth pressure of 50 mbar to 70 mbar, a growth time of 3200 s to 3400 s, and a growth rate of 110 μm×h -1 ~120μm×h -1 Thus, a third epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0017] In some embodiments of the present application, the process parameters for growing the fourth epitaxial layer include: nitrogen flow rate of 50 sccm~60 sccm, growth temperature of 1580℃~1640℃, growth pressure of 180mbar~260mbar, growth time of 100s~200s, and growth rate of 60μm×h -1 ~70μm×h -1 Thus, a fourth epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0018] In some embodiments of the present application, the process parameters for growing the fifth epitaxial layer include: a trimethylaluminum injection rate of 6 sccm to 8 sccm, a trimethylaluminum water bath temperature of 30°C to 40°C, a growth temperature of 1580°C to 1620°C, a growth pressure of 70 mbar to 90 mbar, a growth time of 120s to 240s, and a growth rate of 20 μm×h -1 ~40μm×h -1 Thus, a fifth epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0019] In a second aspect of this application, a silicon carbide epitaxial wafer is provided, produced using the method described in the first aspect of this application. As a result, the silicon carbide epitaxial wafer has high quality, low defect density, and low surface roughness, and its application in ultra-high voltage power devices can improve device performance and yield.

[0020] In some embodiments of the present application, the silicon carbide epitaxial wafer includes a stacked first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a fourth epitaxial layer, and a fifth epitaxial layer, wherein the first epitaxial layer and the fourth epitaxial layer are N-type layers, and the second epitaxial layer, the third epitaxial layer, and the fifth epitaxial layer are P-type layers. The silicon carbide epitaxial wafer has high quality, low defect density and surface roughness, and its application in ultra-high voltage power devices can help improve device performance and yield.

[0021] In some embodiments of the present application, the doping concentration of the first epitaxial layer is 1×10 18 atoms / cm 3 ~5×10 18 atoms / cm 3 , the doping concentration of the second epitaxial layer is 1×10 16 atoms / cm 3 ~2×10 17 atoms / cm 3 The doping concentration of the third epitaxial layer is 1×10 14 atoms / cm 3 ~5×10 14 atoms / cm 3 The doping concentration of the fourth epitaxial layer is 5×10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 The doping concentration of the fifth epitaxial layer is 1×10 19 atoms / cm 3 ~1×10 20 atoms / cm 3 The doping concentration of each epitaxial layer is within the above range, which is conducive to optimizing carrier transport and achieving charge balance, making the electric field distribution uniform, reducing interface delamination caused by differences in thermal expansion coefficients, and thus improving the overall quality of the silicon carbide epitaxial wafer.

[0022] In some embodiments of the present application, the thickness of the first epitaxial layer is 1 μm to 5 μm, the thickness of the second epitaxial layer is 1 μm to 3 μm, the thickness of the third epitaxial layer is 100 μm to 110 μm, the thickness of the fourth epitaxial layer is 1 μm to 3 μm, and the thickness of the fifth epitaxial layer is 1 μm to 3 μm. Thus, the silicon carbide epitaxial wafer has a relatively high thickness and is suitable for ultra-high voltage devices.

[0023] In some embodiments of the present application, the defect density of the silicon carbide epitaxial wafer is ≤0.5 pcs / cm 2 As a result, the silicon carbide epitaxial wafer has higher quality, which is beneficial to improving the performance and reliability of semiconductor devices.

[0024] In some embodiments of the present application, the surface roughness of the silicon carbide epitaxial wafer is ≤0.5 nm, which is beneficial for reducing defects in the silicon carbide epitaxial wafer and further improving the performance and reliability of semiconductor devices.

[0025] In a third aspect of the present application, a semiconductor device is provided, comprising a silicon carbide epitaxial wafer prepared by the method described in the first aspect of the present application or the silicon carbide epitaxial wafer described in the second aspect of the present application. Thus, the semiconductor device has high reliability and service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0027] Figure 1 This is a schematic diagram of the growth process of the first epitaxial layer according to one embodiment of the present application.

[0028] Figure 2 This is a schematic diagram of the growth process of the second epitaxial layer according to one embodiment of the present application.

[0029] Figure 3 This is a schematic diagram of the growth process of the third epitaxial layer according to one embodiment of the present application.

[0030] Figure 4 This is a schematic diagram of the growth process of the fourth epitaxial layer according to one embodiment of the present application.

[0031] Figure 5 This is a schematic diagram of the growth process of the fifth epitaxial layer according to one embodiment of the present application.

[0032] Figure 6 This is a defect test data diagram of a silicon carbide epitaxial wafer according to an embodiment of the present application.

[0033] Figure 7 This is a photo of the surface roughness of a silicon carbide epitaxial wafer according to one embodiment of the present application.

[0034] Figure 8 Schematic diagram of the doping concentration and film thickness measurement points of a silicon carbide epitaxial wafer according to one embodiment of the present application. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present application in detail. Examples of the embodiments are shown in the accompanying drawings, but unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of substantially identical structures may be omitted. This is to avoid unnecessary lengthiness in the following description and to facilitate understanding by those skilled in the art. In addition, the drawings and the following description are provided to enable those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0036] Unless otherwise defined, all technical and scientific terms used in this application have the same meanings as those commonly understood by technicians in the technical field to which this application belongs; the terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application; unless otherwise specified, the numerical values ​​of the various parameters mentioned in this application can be measured using various measurement methods commonly used in the art (for example, they can be tested according to the methods given in the embodiments of this application).

[0037] The terms "include" and "have" in the description and claims of this application and any variations thereof are open expressions, that is, including the contents specified in this application but not excluding other contents.

[0038] In the description of this application, all numbers disclosed herein are approximate, regardless of whether the word "about" or "approximately" is used. The value of each number may vary by less than 10% or by a reasonable difference considered by a person skilled in the art, such as 1%, 2%, 3%, 4% or 5%.

[0039] The "range" disclosed in this application is defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundaries of a particular range. The range defined in this way can be inclusive or exclusive of the end values, and can be arbitrarily combined, i.e., any lower limit can be combined with any upper limit to form a range. For example, if a range of 60 to 120 and 80 to 110 is listed for a particular parameter, it is understood that a range of 60 to 110 and 80 to 120 is also expected. In addition, if the minimum range values ​​listed are 1 and 2, and if the maximum range values ​​listed are 3, 4, and 5, then the following ranges can all be expected: 1 to 3, 1 to 4, 1 to 5, 2 to 3, 2 to 4, and 2 to 5. In this application, unless otherwise specified, the numerical range "a to b" represents an abbreviation of any real number combination between a and b, wherein a and b are both real numbers. For example, a numerical range of "0-5" indicates that all real numbers between "0-5" are listed herein, and "0-5" is simply an abbreviation for these numerical combinations. Furthermore, stating that a parameter is an integer ≥ 2 is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0040] In the description of this application, the terms "first," "second," "third," "fourth," or "fifth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. "First feature" or "second feature" may include one or more of such features.

[0041] In this application, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic. Unless otherwise specified, all steps of this application can be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or steps (b) and (a) performed sequentially. For example, it is mentioned that the method may also include step (c), indicating that step (c) can be added to the method in any order. For example, the method may include steps (a), (b) and (c), or steps (a), (c) and (b), or steps (c), (a) and (b), etc.

[0042] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0043] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0044] In a first aspect of the present application, the present application proposes a method for preparing a silicon carbide epitaxial wafer, comprising:

[0045] S1: growing a first epitaxial layer on one surface of a silicon carbide substrate in a first cavity.

[0046] In some embodiments of the present application, process parameters for growing the first epitaxial layer include: a nitrogen flow rate of 40 sccm to 60 sccm (such as 40 sccm, 50 sccm, or 60 sccm), a growth temperature of 1580° C. to 1650° C. (such as 1580° C., 1600° C., 1630° C., or 1650° C.), a growth pressure of 160 mbar to 280 mbar (such as 160 mbar, 180 mbar, 200 mbar, 240 mbar, 260 mbar, or 280 mbar), a growth time of 1200 s to 2500 s (such as 1200 s, 1400 s, 1600 s, 1800 s, 2000 s, 2200 s, or 2500 s), and a growth rate of 5 μm×h -1 ~10μm×h -1 (e.g. 5μm×h -1 、6μm×h -1 、7μm×h -1 、8μm×h -1 、9μm×h -1 or 10 μm × h -1 As a result, a first epitaxial layer having a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0047] In some embodiments of the present application, the process parameters for growing the first epitaxial layer also include: a hydrogen injection amount of 180 slm~230 slm (such as 180 slm, 190 slm, 200 slm, 210 slm, 220 slm or 230 slm, etc.), a trichlorosilane (TCS) injection amount of 60 sccm~121 sccm (such as 60 sccm, 80 sccm, 100 sccm or 121 sccm, etc.), an ethylene (C2H4) injection amount of 25 sccm~50 sccm (such as 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm, etc.), and a hydrogen chloride (HCl) injection amount of 500 sccm~700 sccm (such as 500 sccm, 600 sccm or 700 sccm, etc.).

[0048] It is understandable that after each epitaxial layer is grown, it needs to be cleaned to ensure device performance, mainly to remove surface contaminants (such as particles, metal ions, organic matter) and the natural oxide layer.

[0049] In some embodiments of the present application, the defect density, thickness, and doping concentration of the first epitaxial layer are measured after the first epitaxial layer is grown, thereby solving the problem that multi-layer thick-film epitaxial wafers are difficult to characterize.

[0050] S2: growing a second epitaxial layer in the second cavity on a surface of the first epitaxial layer away from the silicon carbide substrate.

[0051] In some embodiments of the present application, the process parameters for growing the second epitaxial layer include: a trimethylaluminum injection amount of 0.1 sccm to 0.13 sccm (such as 0.1 sccm, 0.11 sccm, 0.12 sccm or 0.13 sccm), a trimethylaluminum water bath temperature of 19° C. to 20° C. (such as 19° C. or 20° C., etc.), a growth temperature of 1600° C. to 1660° C. (such as 1600° C., 1610° C., 1620° C., 1630° C., 1640° C., 1650° C. or 1660° C., etc.), a growth pressure of 50 mbar to 70 mbar (such as 50 mbar, 60 mbar or 70 mbar, etc.), a growth time of 50 s to 70 s (such as 50 s, 60 s or 70 s, etc.), and a growth rate of 80 μm×h -1 ~120μm×h -1 (e.g. 80 μm × h -1 、90μm×h -1 、100μm×h -1 、110μm×h -1 or 120 μm × h -1 As a result, a second epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0052] In some embodiments of the present application, the process parameters for growing the second epitaxial layer also include: a hydrogen injection amount of 80 slm~130 slm (such as 80 slm, 90 slm, 100 slm, 110 slm, 120 slm or 130 slm, etc.), a trichlorosilane (TCS) injection amount of 336 sccm~506 sccm (such as 336 sccm, 350 sccm, 400 sccm, 450 sccm or 506 sccm, etc.), and an ethylene (C2H4) injection amount of 206 sccm~310 sccm (such as 206 sccm, 220 sccm, 240 sccm, 260 sccm, 280 sccm or 310 sccm, etc.).

[0053] In some embodiments of the present application, the defect density, thickness, and doping concentration of the second epitaxial layer are measured after the second epitaxial layer is grown, thereby solving the problem that multi-layer thick film epitaxial wafers are difficult to characterize.

[0054] S3: growing a third epitaxial layer in the second cavity on a surface of the second epitaxial layer away from the first epitaxial layer.

[0055] In some embodiments of the present application, process parameters for growing the third epitaxial layer include: a trimethylaluminum injection rate of 0.0003 sccm to 0.0008 sccm (e.g., 0.0003 sccm, 0.0004 sccm, 0.0005 sccm, 0.0006 sccm, 0.0007 sccm, or 0.0008 sccm), and a trimethylaluminum water bath temperature of 19° C. to 20° C. (e.g., 19° C. or 20° C.). The growth temperature is 1600℃~1660℃ (such as 1600℃, 1610℃, 1620℃, 1630℃, 1640℃, 1650℃ or 1660℃), the growth pressure is 50mbar~70mbar (such as 50mbar, 60mbar or 70mbar), the growth time is 3200s~3400s (such as 3200s, 3300s or 3400s), and the growth rate is 110μm×h -1 ~120μm×h -1 (e.g. 110 μm × h -1 、115μm×h -1 , or 120μm×h -1 As a result, a third epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0056] In some embodiments of the present application, the process parameters for growing the third epitaxial layer also include: a hydrogen injection amount of 80 slm~130 slm (such as 80 slm, 90 slm, 100 slm, 110 slm, 120 slm or 130 slm, etc.), a trichlorosilane (TCS) injection amount of 458 sccm~550 sccm (such as 458 sccm, 470 sccm, 490 sccm, 510 sccm, 530 sccm or 550 sccm, etc.), and an ethylene (C2H4) injection amount of 247 sccm~298 sccm (such as 247 sccm, 260 sccm, 270 sccm, 280 sccm, 290 sccm or 298 sccm, etc.).

[0057] In some embodiments of the present application, the defect density, thickness, and doping concentration of the third epitaxial layer are measured after the third epitaxial layer is grown, thereby solving the problem that multi-layer thick film epitaxial wafers are difficult to characterize.

[0058] S4: growing a fourth epitaxial layer in the first cavity on a surface of the third epitaxial layer away from the second epitaxial layer.

[0059] In some embodiments of the present application, the process parameters for growing the fourth epitaxial layer include: a nitrogen flow rate of 50 sccm to 60 sccm (such as 50 sccm, 53 sccm, 56 sccm or 60 sccm, etc.), a growth temperature of 1580°C to 1640°C (such as 1580°C, 1600°C, 1620°C or 1640°C, etc.), a growth pressure of 180 mbar to 260 mbar (such as 180 mbar, 200 mbar, 220 mbar, 240 mbar or 260 mbar, etc.), a growth time of 100 s to 200 s (such as 100 s, 120 s, 140 s, 160 s, 180 s or 200 s, etc.), and a growth rate of 60 μm×h -1 ~70μm×h -1 (e.g. 60 μm×h -1 、65μm×h -1 or 70 μm × h -1 As a result, a fourth epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0060] In some embodiments of the present application, the process parameters for growing the fourth epitaxial layer further include: a hydrogen flow rate of 180 slm to 230 slm (such as 180 slm, 190 slm, 200 slm, 210 slm, 220 slm or 230 slm, etc.), a trichlorosilane (TCS) flow rate of 714 sccm to 833.2 sccm (such as 714 sccm, 730 sccm, 750 sccm, 770 sccm, 790 sccm, etc.), and a 3D CMOS process. ccm, 810sccm or 833.2sccm, etc.), the injection amount of ethylene (C2H4) is 300sccm~350.1sccm (such as 300sccm, 310sccm, 320sccm, 330sccm, 340sccm or 350.1sccm, etc.), and the injection amount of hydrogen chloride (HCl) is 500sccm~700sccm (such as 500sccm, 600sccm or 700sccm, etc.).

[0061] In some embodiments of the present application, the defect density, thickness, and doping concentration of the fourth epitaxial layer are measured after the fourth epitaxial layer is grown, thereby solving the problem that multi-layer thick film epitaxial wafers are difficult to characterize.

[0062] S5: growing a fifth epitaxial layer in the second cavity on a surface of the fourth epitaxial layer away from the third epitaxial layer to obtain a silicon carbide epitaxial wafer; wherein the first epitaxial layer and the fourth epitaxial layer are N-type layers, and the second epitaxial layer, the third epitaxial layer, and the fifth epitaxial layer are P-type layers.

[0063] In some embodiments of the present application, the process parameters for growing the fifth epitaxial layer include: a trimethylaluminum injection amount of 6 sccm to 8 sccm (such as 6 sccm, 7 sccm or 8 sccm, etc.), a trimethylaluminum water bath temperature of 30°C to 40°C (such as 30°C, 35°C or 40°C, etc.), a growth temperature of 1580°C to 1620°C (such as 1580°C, 1600°C or 1620°C), a growth pressure of 70 mbar to 90 mbar (such as 70 mbar, 80 mbar or 90 mbar, etc.), a growth time of 120s to 240s (such as 120s, 160s, 200s or 240s, etc.), and a growth rate of 20 μm×h -1 ~40μm×h -1 (e.g. 20 μm × h -1 、30μm×h -1 or 40 μm × h -1 As a result, a fifth epitaxial layer with a specific thickness and doping concentration can be obtained, and the uniformity of the film thickness and doping concentration is high, which is beneficial to improving the overall quality of the silicon carbide epitaxial wafer.

[0064] In some embodiments of the present application, the process parameters for growing the fifth epitaxial layer also include: a hydrogen injection amount of 80 slm~130 slm (such as 80 slm, 90 slm, 100 slm, 110 slm, 120 slm or 130 slm, etc.), a trichlorosilane (TCS) injection amount of 76 sccm~152 sccm (such as 76 sccm, 100 sccm, 130 sccm or 152 sccm, etc.), and an ethylene (C2H4) injection amount of 57 sccm~115 sccm (such as 57 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm or 115 sccm, etc.).

[0065] In some embodiments of the present application, the defect density, thickness, and doping concentration of the fifth epitaxial layer are measured after the fifth epitaxial layer is grown, thereby solving the problem that multi-layer thick-film epitaxial wafers are difficult to characterize.

[0066] In some embodiments of the present application, the doping source gas for the N-type layer is nitrogen (N2), and the doping source gas for the P-type layer is trimethylaluminum (TMAl). This application requires precise control of the N2 flow rate to balance resistivity and breakdown voltage. The TMAl flow rate and water bath temperature are also controlled to achieve high-quality silicon carbide epitaxial wafers.

[0067] In some embodiments of the present application, the process flow of the present method is divided into five stages, wherein process chamber A is used to grow the N-type layer, i.e., the first epitaxial layer Layer 1 and the fourth epitaxial layer Layer 4 mentioned above; process chamber B is used to grow the P-type layer, i.e., the second epitaxial layer Layer 2, the third epitaxial layer Layer 3 and the fifth epitaxial layer Layer 5 mentioned above. The growth process parameters and preparation process of each layer are as follows:

[0068] Formulation A1: Hydrogen flow rate is 180slm~230slm, trichlorosilane flow rate is 60sccm~121sccm, ethylene flow rate is 25sccm~50sccm, nitrogen flow rate is 40sccm~60sccm, hydrogen chloride flow rate is 500sccm~700sccm, growth temperature is 1580℃~1650℃, growth pressure is 160mbar~280mbar, growth time is 1200s~2500s, growth rate is 5μm×h -1 ~10μm×h -1 .

[0069] Formulation B2: The hydrogen flow rate is 80 slm~130 slm, the trichlorosilane flow rate is 336 sccm~506 sccm, the ethylene flow rate is 206 sccm~310 sccm, the trimethylaluminum flow rate is 0.1 sccm~0.13 sccm, the water bath temperature of the trimethylaluminum is 19℃~20℃, the growth temperature is 1600℃~1660℃, the growth pressure is 50 mbar~70 mbar, the growth time is 50 s~70 s, and the growth rate is 80 μm×h -1 ~120μm×h -1 .

[0070] Formulation B3: The hydrogen flow rate is 80 slm~130 slm, the trichlorosilane flow rate is 458 sccm~550 sccm, the ethylene flow rate is 247 sccm~298 sccm, the trimethylaluminum flow rate is 0.0003 sccm~0.0008 sccm, the water bath temperature of trimethylaluminum is 19℃~20℃, the growth temperature is 1600℃~1660℃, the growth pressure is 50 mbar~70 mbar, the growth time is 3200 s~3400 s, and the growth rate is 110 μm×h -1 ~120μm×h -1 .

[0071] Formulation A4: Hydrogen flow rate is 180 slm~230 slm, trichlorosilane flow rate is 714 sccm~833.2 sccm, ethylene flow rate is 300 sccm~350.1 sccm, nitrogen flow rate is 50 sccm~60 sccm, hydrogen chloride flow rate is 500 sccm~700 sccm, growth temperature is 1580℃~1640℃, growth pressure is 180 mbar~260 mbar, growth time is 100 s~200 s, growth rate is 60 μm×h -1 ~70μm×h -1 .

[0072] Formulation B5: The hydrogen flow rate is 80slm~130slm, the trichlorosilane flow rate is 76sccm~152sccm, the ethylene flow rate is 57sccm~115sccm, the trimethylaluminum flow rate is 6sccm~8sccm, the water bath temperature of trimethylaluminum is 30℃~40℃, the growth temperature is 1580℃~1620℃, the growth pressure is 70mbar~90mbar, the growth time is 120s~240s, and the growth rate is 20μm×h -1 ~40μm×h -1 .

[0073] like Figure 1 The figure shows the growth process of the first epitaxial layer Layer1. The first step is to send the (companion substrate) DUMMY1 substrate 1 into the process chamber A and use the formula A1 to grow the first epitaxial layer Layer1. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the target. The third step is to send the (main substrate) PRIME substrate into the process chamber A and use the formula A1 to grow the first epitaxial layer Layer1 (recorded as PL1 wafer) if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the formula A1 until it meets the requirements, and then grow the PL1 wafer.

[0074] It should be noted that DUMMY substrates are auxiliary substrates used for informal production purposes. They are used to preheat and balance the reaction chamber (stabilize temperature and airflow) and reduce damage to the main substrate due to environmental fluctuations in the initial process stages. They are used for test growth during equipment commissioning or process development and are not used for actual device manufacturing. PRIME substrates are high-quality substrates officially used for epitaxial growth. They are used directly to grow silicon carbide epitaxial layers and ultimately manufacture power devices.

[0075] like Figure 2The figure shows the growth process of the second epitaxial layer Layer2. The first step is to send the DUMMY2 substrate 2 into the process chamber B and grow the second epitaxial layer Layer2 using the recipe B2. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PL1 wafer into the process chamber B and grow the second epitaxial layer Layer2 using the recipe B2 (recorded as PL2 wafer) if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the recipe B2 until it meets the requirements, and then grow the PL2 wafer.

[0076] like Figure 3 The figure shows the growth process of the third epitaxial layer Layer3. The first step is to send the DUMMY3 substrate 3 into the process chamber B and grow the third epitaxial layer Layer3 using the recipe B3. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PL2 wafer into the process chamber B and grow the third epitaxial layer Layer3 using the recipe B3 (recorded as PL3 wafer) if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the recipe B3 until it meets the requirements, and then grow the PL3 wafer.

[0077] like Figure 4 The figure shows the growth process of the fourth epitaxial layer Layer4. The first step is to send the DUMMY4 substrate 4 into the process chamber A and use the formula A4 to grow the fourth epitaxial layer Layer4. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the target. The third step is to send the PL3 wafer into the process chamber A and use the formula A4 to grow the fourth epitaxial layer Layer4 (recorded as PL4 wafer) if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the formula A4 until it meets the requirements, and then grow the PL4 wafer.

[0078] like Figure 5The figure shows the growth process for the fifth epitaxial layer, Layer 5. Step 1: DUMMY5 substrate 5 is introduced into process chamber B to grow the fifth epitaxial layer, Layer 5, using recipe B5. Step 2: Measure defects, film thickness, and doping concentration parameters to determine if they meet the target. Step 3: If the results of Step 2 meet the requirements, a PL4 wafer is introduced into process chamber B to grow the fifth epitaxial layer, Layer 5, using recipe B5 (denoted as PL5 wafer). Otherwise, DUMMY substrates are used to adjust recipe B5 until the requirements are met before growing the PL5 wafer. Step 4: Measure defects and roughness on the PL5 wafer. If the results meet the requirements, the preparation is complete, the entire process is terminated, and the wafer is cleaned for future use. Otherwise, the cause is analyzed and growth is resumed. There are three main causes of product failure: 1. Substrate failure (raw material issues); 2. Process failure (parameter fluctuations during growth). This can be addressed by reviewing historical monitoring records of various parameters during machine operation; checking facility conditions and the supply of key utilities such as water, electricity, and gas; and 3. Hardware failure (damage to key components within the reactor or abnormalities in the wafer carrier). In this application, the detection of defects and roughness are all automatically tested and the results are output by a dedicated measurement machine. The defect detection machine is a domestic machine, model E3500 produced by Angkun Vision; the roughness measurement machine is an atomic force microscope AFM produced by Park, model NX20.

[0079] It should be noted that whether the thickness and doping concentration of each epitaxial layer meet the requirements needs to be measured at multiple points. For details, please refer to Figure 8 The points are selected to reduce measurement errors and improve measurement accuracy. Furthermore, the arrangement of the P and N layers, the doping concentration and thickness of each layer, and the total number of layers required are determined by the specific chip design. Those skilled in the art can flexibly select these based on actual needs.

[0080] This application grows epitaxial layers separately through five process steps and controls the growth process parameters of each layer, so that the quality of silicon carbide epitaxial wafers is high, and the defect density and surface roughness are low. Applying it to ultra-high voltage power devices is beneficial to improving the performance and yield of the devices. The preparation method is simple and easy to realize industrial production.

[0081] The above preparation method of the present application has at least the following beneficial effects:

[0082] (1) The N-type layer and the P-type layer are grown in the first cavity and the second cavity respectively, which is beneficial to reduce cross contamination during the alternating growth process and thus improve the quality of the silicon carbide epitaxial wafer;

[0083] (2) After growing a single epitaxial layer, the defect concentration, thickness and doping concentration of the epitaxial layer are measured, which is helpful to solve the problem that multi-layer thick film epitaxial wafers are difficult to characterize;

[0084] (3) This application reduces the defect density and surface roughness and improves the quality of silicon carbide epitaxial wafers by strictly controlling the growth process parameters of each epitaxial layer;

[0085] (4) The silicon carbide epitaxial wafer prepared in this application has a relatively high thickness and can withstand higher voltages. Applying it to ultra-high voltage power devices is beneficial to improving the performance and yield of the devices.

[0086] In a second aspect of this application, a silicon carbide epitaxial wafer is provided, produced using the method of the first aspect of this application. As a result, the silicon carbide epitaxial wafer exhibits high quality, low defect density, and low surface roughness, and its application in ultra-high voltage power devices is beneficial for improving device performance and yield.

[0087] In some embodiments of the present application, a silicon carbide epitaxial wafer includes a stacked first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a fourth epitaxial layer, and a fifth epitaxial layer. The first and fourth epitaxial layers are N-type layers, while the second, third, and fifth epitaxial layers are P-type layers. As a result, the silicon carbide epitaxial wafer has high quality, low defect density, and low surface roughness. Its application in ultra-high voltage power devices can improve device performance and yield.

[0088] In some embodiments of the present application, the doping concentration of the first epitaxial layer is 1×10 18 atoms / cm 3 ~5×10 18 atoms / cm 3 , for example, it can be 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 or 5×10 18 atoms / cm 3 etc.; the doping concentration of the second epitaxial layer is 1×10 16 atoms / cm 3 ~2×10 17 atoms / cm 3 , for example, it can be 1×10 16 atoms / cm 3 , 2×10 16 atoms / cm 3 , 4×10 16 atoms / cm 3 , 6×10 16atoms / cm 3 , 8×10 16 atoms / cm 3 , 1×10 17 atoms / cm 3 or 2×10 17 atoms / cm 3 etc.; the doping concentration of the third epitaxial layer is 1×10 14 atoms / cm 3 ~5×10 14 atoms / cm 3 , for example, it can be 1×10 14 atoms / cm 3 , 2×10 14 atoms / cm 3 , 3×10 14 atoms / cm 3 , 4×10 14 atoms / cm 3 or 5×10 14 atoms / cm 3 etc.; the doping concentration of the fourth epitaxial layer is 5×10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 , for example, it can be 5×10 16 atoms / cm 3 , 6×10 16 atoms / cm 3 , 7×10 16 atoms / cm 3 or 8×10 16 atoms / cm 3 etc.; the doping concentration of the fifth epitaxial layer is 1×10 19 atoms / cm 3 ~1×10 20 atoms / cm 3 , for example, it can be 1×10 19 atoms / cm 3 , 2×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 or 1×10 20 atoms / cm3 The doping concentration of each epitaxial layer within the above range is conducive to optimizing carrier transport, achieving charge balance, making the electric field distribution uniform, reducing interface delamination caused by differences in thermal expansion coefficients, and thus improving the overall quality of the silicon carbide epitaxial wafer.

[0089] In some embodiments of the present application, the thickness of the first epitaxial layer is 1μm~5μm, for example, it can be 1μm, 2μm, 3μm, 4μm or 5μm, etc.; the thickness of the second epitaxial layer is 1μm~3μm, for example, it can be 1μm, 1.5μm, 2μm, 2.5μm or 3μm, etc.; the thickness of the third epitaxial layer is 100μm~110μm, for example, it can be 100μm, 102μm, 104μm, 106μm, 108μm or 110μm, etc.; the thickness of the fourth epitaxial layer is 1μm~3μm, for example, it can be 1μm, 1.5μm, 2μm, 2.5μm or 3μm, etc.; the thickness of the fifth epitaxial layer is 1μm~3μm, for example, it can be 1μm, 1.5μm, 2μm, 2.5μm or 3μm, etc. Understandably, SiC ultra-high voltage (>10kV) power devices require thicker epitaxial layers to withstand high voltages. Thicker epitaxial layers ensure uniform electric field distribution within the depletion region, reducing local electric field concentration that can lead to premature breakdown. Thicker epitaxial layers also reduce the impact of defect density on device performance. However, a thicker epitaxial layer is not necessarily better. Excessively thick epitaxial layers increase on-resistance and device capacitance, resulting in slower switching speeds and significantly increased switching losses, hindering high-frequency applications. Furthermore, thick SiC epitaxial growth is slow, and achieving thickness uniformity and controlling defects (such as dislocations and stacking faults) are more difficult, leading to reduced yield and increased costs. SiC epitaxial wafers within the aforementioned thickness range can not only withstand higher voltages, making them suitable for ultra-high voltage devices, but also exhibit relatively high yield and performance.

[0090] In some embodiments of the present application, the defect density of the silicon carbide epitaxial wafer is ≤0.5 pcs / cm 2 , for example, it can be 0.1pcs / cm 2 、0.2pcs / cm 2 、0.3pcs / cm 2 、0.4pcs / cm 2 or 0.5pcs / cm 2Etc. Specifically, the defect density characterization method is: the defect detection machine will automatically generate this data each time it detects a wafer, and the calculation method is the total number of four types of defects per wafer / wafer area. The defect density of silicon carbide epitaxial wafers is a key factor affecting its device performance and yield. The defects of SiC epitaxial wafers mainly include: (1) surface defects: triangle defects, carrot defects, drops, scratches, pits, etc.; (2) crystal defects: basal plane dislocations (BPDs), screw dislocations (TSDs), edge dislocations (TEDs), micropipes, point defects, etc.; (3) particle contamination: particle contamination from the substrate or the epitaxial growth process affects the surface quality. These defects will cause the device leakage current to increase, the breakdown voltage to decrease, the reliability to decrease, and even affect the chip yield. The defect density is within the above range, indicating that the silicon carbide epitaxial wafer of the present application has a relatively high quality, which is conducive to improving the performance and reliability of semiconductor devices.

[0091] In some embodiments of the present application, the surface roughness of the silicon carbide epitaxial wafer is ≤0.5nm, for example, it can be 0.1nm, 0.2nm, 0.3nm, 0.4nm or 0.5nm, etc. Specifically, the surface roughness is characterized by: atomic force microscope detection, automatic calculation, and taking the Ra value (arithmetic mean deviation). The surface roughness of the silicon carbide epitaxial wafer is one of the key parameters affecting device performance. The rough surface will increase the interface state density, resulting in an increase in leakage current and a decrease in breakdown voltage. It may also cause defects (such as triangle defects and carrot defects), affecting the uniformity of the epitaxial layer. The surface roughness is within the above range, indicating that the surface of the silicon carbide epitaxial wafer of the present application is relatively flat and has fewer defects, which is beneficial to improving the performance and reliability of semiconductor devices.

[0092] In a third aspect of the present application, a semiconductor device is provided, comprising a silicon carbide epitaxial wafer prepared using the method of the first aspect of the present application or the silicon carbide epitaxial wafer of the second aspect of the present application. For example, the semiconductor device may be a high-voltage GTO thyristor structure. As a result, the semiconductor device has high reliability and service life.

[0093] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0094] The present invention will be described below by way of specific examples. It should be noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Where specific techniques or conditions are not specified in the examples, they are determined according to the techniques or conditions described in the literature in this area or according to the product specifications. Reagents or instruments not specified by manufacturer are all commercially available conventional products.

[0095] Example 1

[0096] The process flow of this method is divided into five stages, wherein process chamber A is used for growing N-type layers, namely the first epitaxial layer Layer 1 and the fourth epitaxial layer Layer 4; process chamber B is used for growing P-type layers, namely the second epitaxial layer Layer 2, the third epitaxial layer Layer 3, and the fifth epitaxial layer Layer 5. The reaction gases used in this embodiment mainly involve hydrogen (H2) as a carrier gas, argon (Ar) as a purge gas, trichlorosilane (TCS) as the silicon source gas required for the reaction, ethylene (C2H4) as the carbon source gas required for the reaction, nitrogen (N2) as an N-type doping source gas, trimethylaluminum (TMAl) as a P-type doping source gas, and hydrogen chloride (HCl) as an auxiliary gas. The details are as follows:

[0097] (1) The first stage of the process, namely the first epitaxial layer Layer 1, N-type layer, requires a film thickness of 2.5 μm ± 5% and a doping concentration of 1×10 18 atoms / cm 3 ±25%, film thickness uniformity ≤5% (1σ / mean), doping concentration uniformity ≤10% (1σ / mean). Figure 1 The figure shows the growth process of the first epitaxial layer Layer1. The first step is to send the DUMMY1 substrate 1 into the process chamber A and grow the first epitaxial layer Layer1 using the process parameters in Table 1. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PRIME substrate into the process chamber A and grow the first epitaxial layer Layer1 (recorded as PL1 wafer) using the process parameters in Table 1 if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the formula A1 until the requirements are met, and then grow the PL1 wafer.

[0098] Table 1 Main process parameters of the first epitaxial layer Layer 1

[0099]

[0100] The results of growing Layer 1 using the process parameters shown in Table 1 are as follows, Table 2 shows the doping concentration data, and Table 3 shows the film thickness data.

[0101] Table 2 Doping concentration measurement data of the first epitaxial layer Layer 1

[0102]

[0103] The calculated average doping concentration of Layer 1 is 1.05×10 18 atoms / cm 3 , the uniformity is 2.98% (1σ / mean), which meets the requirements.

[0104] Table 3 Thickness measurement data of the first epitaxial layer Layer 1

[0105]

[0106] Calculation shows that the average thickness of Layer 1 is 2.57 μm and the uniformity is 1.00% (1σ / mean), which meets the requirements.

[0107] (2) The second stage of the process, namely the second epitaxial layer Layer 2, P-type layer, requires a film thickness of 2.6 μm ± 5% and a doping concentration of 1×10 17 atoms / cm 3 ±25%, film thickness uniformity ≤5% (1σ / mean), doping concentration uniformity ≤10% (1σ / mean). Figure 2 The figure shows the growth process of the second epitaxial layer Layer2. The first step is to send the DUMMY2 substrate 2 into the process chamber B and grow the second epitaxial layer Layer2 using the process parameters in Table 4. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PL1 wafer into the process chamber B and grow the second epitaxial layer Layer2 (recorded as PL2 wafer) using the process parameters in Table 4 if the results of the second step meet the requirements. Otherwise, continue to use the DUMMY substrate to debug the recipe B2 until the requirements are met, and then grow the PL2 wafer.

[0108] Table 4 Main process parameters of the second epitaxial layer Layer 2

[0109]

[0110] The results of growing Layer 2 using the process parameters shown in Table 4 are as follows, Table 5 shows the doping concentration data, and Table 6 shows the film thickness data.

[0111] Table 5 Doping concentration measurement data of the second epitaxial layer Layer 2

[0112]

[0113] The calculated average doping concentration of Layer 2 is 1.02×10 17 atoms / cm 3 , the uniformity is 5.95% (1σ / mean), which meets the requirements.

[0114] Table 6 Thickness measurement data of the second epitaxial layer Layer 2

[0115]

[0116] Calculation shows that the average thickness of Layer 2 is 2.64 μm and the uniformity is 2.28% (1σ / mean), which meets the requirements.

[0117] (3) The third stage of the process, namely the third epitaxial layer Layer 3, P-type layer, requires a film thickness of 105 μm ± 5% and a doping concentration of 4 × 10 14 atoms / cm 3 ±25%. Figure 3 The figure shows the growth process of the third epitaxial layer Layer3. The first step is to send the DUMMY3 substrate 3 into the process chamber B and grow the third epitaxial layer Layer3 using the process parameters in Table 7. The second step is to measure its defects, film thickness, and concentration parameters, and determine whether they meet the targets. The third step is to send the PL2 wafer into the process chamber B and grow the third epitaxial layer Layer3 (recorded as PL3 wafer) using the process parameters in Table 7 if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the recipe B3 until it meets the requirements, and then grow the PL3 wafer.

[0118] Table 7 Main process parameters of the third epitaxial layer Layer 3

[0119]

[0120] The results of growing Layer 3 using the process parameters shown in Table 7 are as follows, Table 8 shows the doping concentration data, and Table 9 shows the film thickness data.

[0121] Table 8 Doping concentration measurement data of the third epitaxial layer Layer 3

[0122]

[0123] The calculated average doping concentration of Layer 3 is 3.84×10 14 atoms / cm 3 , meeting the requirements.

[0124] Table 9 Thickness measurement data of the third epitaxial layer Layer 3

[0125]

[0126] Calculation shows that the average thickness of Layer 3 is 104.37 μm, which meets the requirements.

[0127] (4) The fourth stage of the process, namely the fourth epitaxial layer Layer 4, N-type layer, requires a film thickness of 2.6 μm ± 5% and a doping concentration of 7 × 10 16 atoms / cm 3 ±25%, film thickness uniformity ≤5% (1σ / mean), doping concentration uniformity ≤10% (1σ / mean). Figure 4The figure shows the growth process of the fourth epitaxial layer Layer4. The first step is to send the DUMMY4 substrate 4 into the process chamber A and grow the fourth epitaxial layer Layer4 using the process parameters in Table 10. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PL3 wafer into the process chamber A and grow the fourth epitaxial layer Layer4 (recorded as PL4 wafer) using the process parameters in Table 10 if the result of the second step meets the requirements. Otherwise, continue to use the DUMMY substrate to debug the formula A4 until the requirements are met, and then grow the PL4 wafer.

[0128] Table 10 Main process parameters of the fourth epitaxial layer Layer 4

[0129]

[0130] The results of growing Layer 4 using the process parameters shown in Table 10 are as follows. Table 11 shows the doping concentration data, and Table 12 shows the film thickness data.

[0131] Table 11 Doping concentration measurement data of the fourth epitaxial layer Layer 4

[0132]

[0133] The calculated average concentration of Layer 4 is 7.01×10 16 atoms / cm 3 , the uniformity is 1.99% (1σ / mean), which meets the requirements.

[0134] Table 12 Thickness measurement data of the fourth epitaxial layer Layer 4

[0135]

[0136] Calculation shows that the average thickness of Layer 4 is 2.60 μm and the uniformity is 1.19% (1σ / mean), which meets the requirements.

[0137] (5) The fifth stage of the process, namely the fifth epitaxial layer Layer 5, is a P-type layer with a required film thickness of 2.5 μm ± 5% and a doping concentration of 2×10 19 atoms / cm 3 ±25%. Figure 5The figure shows the growth process of the fifth epitaxial layer Layer5. The first step is to send the DUMMY5 substrate 5 into the process chamber B and grow the fifth epitaxial layer Layer5 using the process parameters in Table 13. The second step is to measure its defects, film thickness, and doping concentration parameters, and determine whether they meet the targets. The third step is to send the PL4 wafer into the process chamber B and grow the fifth epitaxial layer Layer5 (recorded as PL5 wafer) using the process parameters in Table 13 if the results of the second step meet the requirements. Otherwise, continue to use the DUMMY substrate to debug the formula B5 until the requirements are met, and then grow the PL5 wafer. The fourth step is to measure the defects and roughness of the PL5 wafer. If the requirements are met, the preparation is completed, the entire process flow is ended, and the wafer is cleaned and ready for use. Otherwise, the cause is analyzed and the wafer is grown again.

[0138] Table 13 Main process parameters of the fifth epitaxial layer Layer 5

[0139]

[0140] The results of growing Layer 5 using the process parameters shown in Table 13 are as follows, Table 14 shows the doping concentration data, and Table 15 shows the film thickness data.

[0141] Table 14 Doping concentration measurement data of the fifth epitaxial layer Layer5

[0142]

[0143] The calculated average concentration of Layer 5 is 2.22×10 19 atoms / cm 3 , meeting the requirements.

[0144] Table 15 Thickness measurement data of the fifth epitaxial layer Layer 5

[0145]

[0146] Calculation shows that the average thickness of Layer 5 is 2.46 μm, which meets the requirements.

[0147] In summary, using this five-stage process flow, a 4H-SiC multilayer thick-film epitaxial wafer with multiple PN junctions grown on a PRIME substrate contains five epitaxial layers with a total thickness of 114.64μm. The first and fourth layers are N-type doped, while the second, third, and fifth layers are P-type. Characterization results for defects and surface roughness of the final product (PL5 wafer) are shown below, with a defect density requirement of ≤0.5pcs / cm 2 , surface roughness ≤0.5nm.

[0148] Depend on Figure 6It is known that the final product (PL5 wafer) has four common fatal defects, such as Triangle (triangle defect), Downfall (collapse defect), Micropipe (micropipe defect), and Carrot (carrot defect). The total number of defects is 46, and the defect density is 0.28pcs / cm 2 , meeting the requirements.

[0149] Depend on Figure 7 It is known that the average surface roughness of the final product is 0.284nm, which meets the requirements.

[0150] It should be noted that the present application is not limited to the above-mentioned embodiments. The above-mentioned embodiments are merely examples, and any embodiments having substantially the same structure and effect as the technical concept within the scope of the present application are all included in the technical scope of the present application. In addition, without departing from the scope of the present application, any other embodiments that can be conceived by those skilled in the art and that combine some of the constituent elements in the embodiments are also included in the scope of the present application.

Claims

1. A method for preparing a silicon carbide epitaxial wafer, characterized in that: include: growing a first epitaxial layer on a surface of a silicon carbide substrate in a first cavity; growing a second epitaxial layer on a surface of the first epitaxial layer away from the silicon carbide substrate in a second cavity; growing a third epitaxial layer in the second cavity on a surface of the second epitaxial layer away from the first epitaxial layer; growing a fourth epitaxial layer on a surface of the third epitaxial layer away from the second epitaxial layer in the first cavity; growing a fifth epitaxial layer in the second cavity on a surface of the fourth epitaxial layer away from the third epitaxial layer to obtain the silicon carbide epitaxial wafer; The first epitaxial layer and the fourth epitaxial layer are N-type layers, and the second epitaxial layer, the third epitaxial layer, and the fifth epitaxial layer are P-type layers. The doping source of the N-type layer is nitrogen, and the doping source of the P-type layer is trimethylaluminum. The doping concentration of the first epitaxial layer is 1×10 18 atoms / cm 3 ~5×10 18 atoms / cm 3 , the doping concentration of the second epitaxial layer is 1×10 16 atoms / cm 3 ~2×10 17 atoms / cm 3 The doping concentration of the third epitaxial layer is 1×10 14 atoms / cm 3 ~5×10 14 atoms / cm 3 The doping concentration of the fourth epitaxial layer is 5×10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 The doping concentration of the fifth epitaxial layer is 1×10 19 atoms / cm 3 ~1×10 20 atoms / cm 3 , The thickness of the first epitaxial layer is 1 μm to 5 μm, the thickness of the second epitaxial layer is 1 μm to 3 μm, the thickness of the third epitaxial layer is 100 μm to 110 μm, the thickness of the fourth epitaxial layer is 1 μm to 3 μm, and the thickness of the fifth epitaxial layer is 1 μm to 3 μm.

2. The method according to claim 1, characterized in that measuring the defect density, thickness and doping concentration of the first epitaxial layer after growing the first epitaxial layer; and / or, measuring the defect density, thickness and doping concentration of the second epitaxial layer after growing the second epitaxial layer; and / or, measuring the defect density, thickness and doping concentration of the third epitaxial layer after growing the third epitaxial layer; and / or, measuring the defect density, thickness and doping concentration of the fourth epitaxial layer after growing the fourth epitaxial layer; and / or, After growing the fifth epitaxial layer, the defect density, thickness and doping concentration of the fifth epitaxial layer are measured.

3. The method according to claim 1 or 2, characterized in that The process parameters for growing the first epitaxial layer include: The nitrogen flow rate is 40sccm~60sccm, the growth temperature is 1580℃~1650℃, the growth pressure is 160mbar~280mbar, the growth time is 1200s~2500s, and the growth rate is 5μm×h -1 ~10μm×h -1 .

4. The method according to claim 1 or 2, characterized in that The process parameters for growing the second epitaxial layer include: The amount of trimethylaluminum introduced is 0.1 sccm~0.13 sccm, the water bath temperature of trimethylaluminum is 19℃~20℃, the growth temperature is 1600℃~1660℃, the growth pressure is 50mbar~70mbar, the growth time is 50s~70s, and the growth rate is 80μm×h -1 ~120μm×h -1 .

5. The method according to claim 1 or 2, characterized in that The process parameters for growing the third epitaxial layer include: The amount of trimethylaluminum introduced was 0.0003 sccm~0.0008 sccm, the water bath temperature of trimethylaluminum was 19℃~20℃, the growth temperature was 1600℃~1660℃, the growth pressure was 50mbar~70mbar, the growth time was 3200s~3400s, and the growth rate was 110μm×h -1 ~120μm×h -1 .

6. The method according to claim 1 or 2, characterized in that The process parameters for growing the fourth epitaxial layer include: The nitrogen flow rate is 50sccm~60sccm, the growth temperature is 1580℃~1640℃, the growth pressure is 180mbar~260mbar, the growth time is 100s~200s, and the growth rate is 60μm×h -1 ~70μm×h -1 .

7. The method according to claim 1 or 2, characterized in that The process parameters for growing the fifth epitaxial layer include: The flow rate of trimethylaluminum is 6 sccm~8 sccm, the water bath temperature of trimethylaluminum is 30℃~40℃, the growth temperature is 1580℃~1620℃, the growth pressure is 70mbar~90mbar, the growth time is 120s~240s, and the growth rate is 20μm×h -1 ~40μm×h -1 .

8. A silicon carbide epitaxial wafer, characterized in that: Prepared by the method according to any one of claims 1 to 7, The silicon carbide epitaxial wafer includes a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a fourth epitaxial layer and a fifth epitaxial layer, wherein the first epitaxial layer and the fourth epitaxial layer are N-type layers, and the second epitaxial layer, the third epitaxial layer and the fifth epitaxial layer are P-type layers. The doping source of the N-type layer is nitrogen, and the doping source of the P-type layer is trimethylaluminum. The doping concentration of the first epitaxial layer is 1×10 18 atoms / cm 3 ~5×10 18 atoms / cm 3 , the doping concentration of the second epitaxial layer is 1×10 16 atoms / cm 3 ~2×10 17 atoms / cm 3 The doping concentration of the third epitaxial layer is 1×10 14 atoms / cm 3 ~5×10 14 atoms / cm 3 The doping concentration of the fourth epitaxial layer is 5×10 16 atoms / cm 3 ~8×10 16 atoms / cm 3 The doping concentration of the fifth epitaxial layer is 1×10 19 atoms / cm 3 ~1×10 20 atoms / cm 3 , The thickness of the first epitaxial layer is 1 μm to 5 μm, the thickness of the second epitaxial layer is 1 μm to 3 μm, the thickness of the third epitaxial layer is 100 μm to 110 μm, the thickness of the fourth epitaxial layer is 1 μm to 3 μm, and the thickness of the fifth epitaxial layer is 1 μm to 3 μm.

9. The silicon carbide epitaxial wafer according to claim 8, characterized in that: The defect density of the silicon carbide epitaxial wafer is ≤0.5 pcs / cm 2 .

10. The silicon carbide epitaxial wafer according to claim 8, characterized in that: The surface roughness of the silicon carbide epitaxial wafer is ≤0.5nm.

11. A semiconductor device, characterized in that: The invention comprises a silicon carbide epitaxial wafer prepared by the method according to any one of claims 1 to 7 or a silicon carbide epitaxial wafer according to any one of claims 8 to 10.

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