TEM-imitated copper mesh type thermal and electrical analysis chip and manufacturing method thereof

Abstract

The invention discloses a TEM-imitated copper mesh type thermal and electrical analysis chip and a manufacturing method thereof.The chip comprises a silicon substrate and insulating dielectric layers deposited on the upper surface and the lower surface of the silicon substrate, the shape and the size of the silicon substrate are matched with those of a TEM copper mesh, and hollowed-out areas are arranged on the silicon substrate and the insulating dielectric layers on the lower surface in a penetrating mode to serve as observation windows; a circuit module is deposited on the surface of the upper surface insulating dielectric layer above the hollow area, the circuit module comprises two groups of heating coils, two groups of electrical measuring electrodes and a temperature measuring electrode, the two groups of electrical measuring electrodes are comb-shaped and are arranged between the two groups of heating coils up and down, the temperature measuring electrode is arranged on the outermost side of one group of electrical measuring electrodes, and the temperature measuring electrode is arranged on the outer side of the other group of electrical measuring electrodes. The circuit module is connected with an external measuring circuit. The chip provided by the invention not only adapts to morphology characterization of a TEM conventional sample rod, but also adapts to a special sample rod, can be used for synchronously performing heating and electrical property measurement while observing a sample, and is beneficial to in-situ research on nucleation growth, structural evolution and corresponding physical property change of a material in the TEM.

Description

Technical Field

[0001] The present invention belongs to the fields of electron microscopy, micro-nano processing, and MEMS devices, and particularly relates to a TEM copper mesh-like thermal and electrical analysis chip and a manufacturing method thereof. Background Art

[0002] A transmission electron microscope (TEM) is a microscopic analysis tool that uses a high-energy electron beam to transmit a sample and form an image, and can study the microstructure of materials at the nano- to atomic scale. TEM is widely used in the fields of materials science, physics, chemistry, and biology, and reveals the crystal structure, defects, interfaces, and chemical composition of samples through its high-resolution ability. In-situ TEM technology relies on the TEM sample holder, and while characterizing, an external field action is applied to the sample through the functional modules in the sample holder, such as heating, applying an external force, applying an electric field, or a gas environment, etc. This endows TEM with new functions and can characterize the dynamic evolution of materials in real time under the action of an external field, so as to deeply understand the structure-property relationship of materials and provide key scientific basis for the design and optimization of new materials.

[0003] Currently, the realization of in-situ characterization technology in the TEM system mainly relies on various functional chips adapted to the sample holder. Representative ones include Protochips, DENS Solutions, Zeyou Technology, etc. Basically, the needs for studying the dynamic evolution of materials under the action of an electric field, thermal field, stress field, etc. are covered. However, the existing commercial sample holders and test chips are one-to-one corresponding, that is, one chip corresponds to one dedicated sample holder, and there are great limitations in terms of universality. Moreover, the number of electrodes of the dedicated chip is limited, and it is difficult to measure the electrical characteristics in different length ranges for samples with a relatively large size. In addition, the cost of the dedicated chip-sample holder system is relatively high, which limits its wide application. Therefore, developing an in-situ chip with low cost, strong universality, and reusable multiple times is of great significance for the development of in-situ TEM technology.

[0004] MEMS technology is a technology that uses micro- and nano-scale processing methods to precisely process materials through techniques such as chemical etching and photolithography. It combines microelectronic technology and machining technology and can manufacture micro-devices with both electrical and mechanical properties. MEMS technology has a wide range of applications in the fields of micro sensors, actuators, accelerometers, gyroscopes, optical devices, etc. MEMS processing technology is generally divided into two categories: bulk micromachining process and surface micromachining process. The bulk micromachining process performs three-dimensional processing on the substrate through methods such as deep silicon etching, and is usually used to manufacture complex three-dimensional structures. The surface micromachining process mainly constructs microstructures on the surface of the substrate through means such as thin film deposition and photolithography, and is commonly used to manufacture thin film sensors, etc. Since MEMS technology can be mostly compatible with traditional IC technology, it has a wide range of application prospects in the fields of modern electronic devices and sensors.

[0005] In view of the problems such as limited number of electrodes in commercial in-situ chips, single observation area, low fault tolerance, and poor versatility, it is of great significance to develop a general-purpose electro-thermal analysis chip with multiple groups of electrodes through MEMS technology. At present, there is a lack of in-situ chip products on the market that are adapted to conventional sample holders and can simultaneously perform electro-thermal coupling characterization. Summary of the Invention

[0006] Object of the Invention: An object of the present invention is to provide a TEM copper mesh-like thermal and electrical analysis chip, which has good versatility and supports multiple sample preparations, providing conditions for simulating working conditions in TEM to test and analyze the structural and physical property evolution processes of materials.

[0007] Another object of the present invention is to provide a manufacturing method of the chip.

[0008] Technical Solution: The structure of a TEM copper mesh-like thermal and electrical analysis chip according to the present invention includes a silicon substrate, a dielectric layer deposited on the upper surface of the silicon substrate, a heating coil, an electrical measurement electrode, and a temperature measurement electrode deposited on the surface of the dielectric layer.

[0009] The chip further includes two hollow areas penetrating the silicon substrate as observation windows, and an insulating dielectric layer above each hollow area as a support film for the observation window to support the circuit module composed of the heating coil, the electrical measurement electrode, and the temperature measurement electrode. The circuit module extends to the edge of the chip and can be connected to an external measurement circuit.

[0010] Furthermore, each chip contains two observation windows and two corresponding sets of circuit modules. Each set of circuit modules includes two heating coils on the left and right, and there are two sets of electrical measurement electrodes, one above and one below, in the middle of the heating coils. There is a pair of temperature measurement electrodes outside one set of electrical measurement electrodes. In actual use, the approximate real-time temperature of the observation window can be calculated based on the initial resistance of the temperature measurement electrode, the initial temperature, the temperature coefficient of the metal used, and the real-time resistance of the temperature measurement electrode.

[0011] Furthermore, the heating coil is a convex structure in the observation window area to ensure uniform heating in the observation area.

[0012] Furthermore, each chip has two window areas, and there are multiple (4 - 8) electrical measurement electrodes in each window, which can be adapted to multi-electrode synchronous testing. The electrodes are comb-shaped. For samples with larger scales, the comb-shaped electrodes can measure different lengths and different regions, which is beneficial for analyzing the electrical characteristics of the local range of the sample.

[0013] Further, the overall chip is circular with a diameter of 3 mm, and its size is similar to that of a TEM copper grid. It is suitable for both the conventional TEM sample rod for morphology characterization and the special sample rod for simultaneous heating and electrical property measurement while observing the sample.

[0014] Further, the dielectric layer on the upper surface of the silicon substrate is any one or combination of low-stress Si3N4, Al2O3, and SiO2, with a thickness of 20 - 100 nm.

[0015] Further, the materials of the chip heating coil, electrical measurement electrode, and temperature measurement electrode are any one or combination of nickel, gold, copper, platinum, and tungsten, with a thickness of 100 - 120 nm; among them, the line width of the heating coil is 4 - 8 μm, and the line widths of the electrical measurement electrode and the temperature measurement electrode are 3 - 6 μm.

[0016] A TEM copper grid-like thermal and electrical analysis chip, and its manufacturing method includes the following steps:

[0017] Step 1, deposit and grow insulating dielectric layers on the upper and lower surfaces of the silicon substrate;

[0018] Step 2, use the RIE process to etch a window area on the lower surface of the silicon substrate for further wet etching to form an observation window;

[0019] Step 3, deposit the chip heating coil, electrical measurement electrode, temperature measurement electrode, and contact electrode on the dielectric layer on the upper surface of the silicon substrate through the PVD process;

[0020] Step 4, use the RIE process to scribe an annular dicing groove on the dielectric layer on the upper surface of the silicon substrate;

[0021] Step 5, use the DRIE process to etch and dice the silicon substrate to divide it into multiple chips;

[0022] Step 6, use the wet etching process to etch upward to the dielectric layer to form a hollow area as the observation window of the chip.

[0023] Beneficial effects: Compared with the prior art, the significant technical effects of the present invention are as follows: It provides a general solution for in-situ TEM characterization. This chip is suitable for both the conventional TEM sample rod for morphology characterization and the special sample rod for simultaneous heating and electrical property measurement while observing the sample; this chip also supports multiple sample preparations and multiple experiments, which is conducive to improving the experimental error tolerance and reducing the experimental cost; the present invention provides an important support for studying the reaction mechanism of materials. By effectively observing the reaction and growth process of nanostructures, their behavior laws can be deeply revealed. This technology is of great significance for electron microscopy research, especially in microstructural analysis and characterization, and can provide strong support for related fields. Description of the Drawings

[0024] Figure 1 is the structural diagram of the upper surface size of the TEM copper mesh type thermal and electrical analysis chip of the present invention;

[0025] Figure 2 is the structural diagram of the lower surface size of the TEM copper mesh type thermal and electrical analysis chip of the present invention;

[0026] Figure 3 is the side view of the TEM copper mesh type thermal and electrical analysis chip of the present invention;

[0027] Figure 4 is the partial enlarged view of the heating coil, electrical measurement electrode and temperature measurement electrode in the observation window area on the upper surface of the TEM copper mesh type thermal and electrical analysis chip of the present invention;

[0028] In the figure: 1. Silicon substrate; 2. Dielectric layer on the upper surface of the silicon substrate; 3. Dielectric layer on the lower surface of the silicon substrate; 4. Heating coil; 41. Left heating coil; 42. Right heating coil; 5. Electrical measurement electrode; 51. Upper electrical measurement electrode; 52. Lower electrical measurement electrode; 6. Temperature measurement electrode; 7. Observation window support film; 71. First observation window support film; 72. Second observation window support film; 8. Chip contact electrode; 9. Hollow area; 91. First hollow area; 92. Second hollow area. Detailed implementation mode

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] A TEM copper mesh type thermal and electrical analysis chip; as Figures 1 to 3 shown, the chip includes a silicon substrate 1, a dielectric layer 2 on the upper surface of the silicon substrate, a dielectric layer 3 on the lower surface of the silicon substrate, a heating coil 4, an electrical measurement electrode 5, and a temperature measurement electrode 6. The heating coil 4, the electrical measurement electrode 5, and the temperature measurement electrode 6 form a circuit module; a hollow area 9 is penetrated through the silicon substrate 1 and the dielectric layer 3 on the lower surface of the silicon substrate at the corresponding position of the circuit module, and the dielectric layer 2 on the upper surface of the silicon substrate above the hollow area serves as an observation window support film 7 for supporting the circuit module composed of the heating coil 4, the electrical measurement electrode 5, and the temperature measurement electrode 6. The circuit module extends to the edge of the chip and can be connected to an external measurement circuit through the chip contact electrode 8.

[0031] As Figure 4As shown, the circuit module includes two symmetrically arranged heating coils 4 on the left and right, namely the left heating coil 41 and the right heating coil 42. The heating coils can provide a thermal field for the sample, facilitating sublimation experiments, performance detection at high temperatures, etc. The left and right symmetric coils are arranged in a surrounding heating manner, enabling better temperature uniformity in the observation window. There are two upper and lower groups of electrical measurement electrodes 5 between the two heating coils, namely the upper electrical measurement electrode 51 and the lower electrical measurement electrode 52, which can measure electrical properties such as the resistivity and conductivity of the sample. The two upper and lower groups of measurement electrodes support two measurements of the sample, expanding the available range of the chip. One temperature measurement electrode 6 is arranged on the outermost side of one group of electrical measurement electrodes. Arranging the temperature measurement electrode outside the electrical measurement electrodes can reduce the impact on electrical tests. In actual use, the temperature at the center of the observation window can be calculated based on the initial resistance, initial temperature of the temperature measurement electrode, the temperature coefficient of the metal used, and the real-time resistance of the temperature measurement electrode, thereby inferring the approximate real-time temperature of the observation area.

[0032] The temperature measurement electrode 6 is arranged outside the electrical measurement electrodes, and its advantages are as follows: (1) If the size of the sample to be measured is not that large, it can just be placed on the four electrical measurement electrodes in the middle for four-point measurement or select appropriate electrical measurement electrodes for measurement; (2) If the size of the sample to be measured is large, it may be placed on both the electrical measurement electrodes and the temperature measurement electrode at the same time. The temperature measurement electrode is essentially a short-circuited metal bridge. In this case, it will definitely have a certain impact on the measurement of electrical properties. The outer design has less impact on the measurement of electrical properties. At the same time, the outer design makes the temperature measurement electrode form a gap with the electrical measurement electrodes, enabling the current flowing through the sample to preferentially pass through the preset electrical measurement electrode pair, reducing the influence range of the short-circuit effect of the temperature measurement electrode; and when the current flows through the outer temperature measurement electrode, it needs to travel a longer path. Compared with the inner layout, the impedance of the short-circuit loop is equivalently increased, thereby weakening the interference intensity on the main measurement loop.

[0033] The left heating coil 41 and the right heating coil 42 are convex structures in the observation window area to ensure uniform heating in the observation window area. Multiple upper electrical measurement electrodes 51 and lower electrical measurement electrodes 52 are respectively arranged, which can be adapted to multi-electrode synchronous testing; in addition, the electrical measurement electrodes are in a comb shape, which can be adapted to samples with different morphologies and sizes for electrical property measurement.

[0034] The left heating coil 41, the right heating coil 42, the upper electrical measurement electrode 51, the lower electrical measurement electrode 52, and the temperature measurement electrode 6 respectively extend to the edge of the chip through leads and are connected to the external measurement circuit through the chip contact electrode 8.

[0035] The TEM copper mesh-like thermal and electrical analysis chip may include multiple hollow areas 9, as well as multiple corresponding observation window support films 7 and multiple sets of circuit modules, supporting multiple sample preparations and multiple observations, which is beneficial to improving the chip reusability and reducing the experimental cost. In this embodiment, the chip includes two hollow areas (the first hollow area 91 and the second hollow area 92), as well as two corresponding observation window support films 7 (the first observation window support film 71 and the second observation window support film 72) and two sets of circuit modules. There are two sets of electrical measurement electrodes 5 in each observation window, and each set can be set with 4 - 8 electrodes, which can be adapted to multi-electrode synchronous testing. In this embodiment, there are 6 upper electrical measurement electrodes 51 and 4 lower electrical measurement electrodes 52. The temperature measurement electrode 6 is arranged on the outermost side of the lower electrical measurement electrode 52, making the entire circuit module a left-right symmetric structure.

[0036] The overall shape of the TEM copper mesh-like thermal and electrical analysis chip is a circle with a diameter of 3 mm, which is approximately the same size as a common TEM copper mesh. It is suitable for both the conventional sample rod of TEM for morphology characterization and the special sample rod for simultaneous heating and electrical property measurement while observing the sample.

[0037] The dielectric layer 2 on the upper surface of the silicon substrate is any one or a combination of low-stress Si3N4, Al2O3, and SiO2, with a thickness of 20 - 100 nm.

[0038] The materials of the heating coil 4, the electrical measurement electrode 5, the temperature measurement electrode 6, and the chip contact electrode 8 are any one or a combination of nickel, gold, copper, platinum, and tungsten, with a thickness of 100 - 120 nm; among them, the line width of the heating coil is 4 - 8 μm, and the line widths of the electrical measurement electrode and the temperature measurement electrode are 3 - 6 μm.

[0039] In this embodiment, the chip design is based on the morphology of a 3-mm-diameter universal carrier mesh, and is batch-produced through MEMS technology. This is a low-cost and convenient technical solution, which not only solves the problems of single observation area and low fault tolerance rate of existing in-situ chips, but also overcomes the dependence on special sample rods. The present invention fills the technical gap for the usage requirements in this field.

[0040] The manufacturing method of the TEM copper mesh-like thermal and electrical analysis chip includes the following steps:

[0041] Step 1, deposit the dielectric layer 2 on the upper surface of the silicon substrate 1 and deposit the dielectric layer 3 on the lower surface of the silicon substrate 1;

[0042] Step 2, use the RIE process to etch out the window area on the dielectric layer 3 on the lower surface of the silicon substrate for further wet etching to form the observation window;

[0043] Step 3: Metal electrodes are deposited on the dielectric layer on the upper surface of the silicon substrate using a PVD process. A circuit module containing a heating coil 4, an electrical measurement electrode 5, and a temperature measurement electrode 6 is deposited at the corresponding position of the observation window. The circuit module extends to the edge of the chip to form a chip contact electrode 8 for connecting to an external measurement circuit.

[0044] Step 4: using RIE process to carve a circular scribe groove on the dielectric layer 2 on the upper surface of the silicon substrate;

[0045] Step 5: Using a DRIE process to etch and scribing the silicon substrate 1 to divide it into multiple chips;

[0046] In step 6, a wet etching process is used to etch the silicon substrate 1 from bottom to top, starting from the window area of the dielectric layer 3 on the lower surface of the silicon substrate, until the etching reaches the dielectric layer 2 on the upper surface of the silicon substrate, thereby forming a hollow area 9 in the silicon substrate. The dielectric layer 2 on the upper surface of the silicon substrate above the hollow area 9 serves as the observation window support film 7 of the chip.

[0047] The following examples illustrate the material composition and size range of various parts of a TEM-like copper mesh thermal and electrical analysis chip. It should be noted that the following are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or replacements within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0048] Example 1:

[0049] In this embodiment, the structure of the TEM-like copper mesh thermal and electrical analysis chip is the same as above.

[0050] The dielectric layer 2 on the upper surface of the silicon substrate is low-stress Si3N4 with a thickness of 50nm.

[0051] The heating coil 4 , electrical measurement electrode 5 , temperature measurement electrode 6 and chip contact electrode 8 are made of gold with a thickness of 100 nm. The heating coil line width is 6 μm, and the electrical measurement electrode and temperature measurement electrode line width are 4 μm.

[0052] The method for making the TEM-like copper mesh thermal and electrical analysis chip comprises the following steps:

[0053] Step 1: depositing a silicon substrate upper surface dielectric layer 2 on the upper surface of a silicon substrate 1, and depositing a silicon substrate lower surface dielectric layer 3 on the lower surface of the silicon substrate 1;

[0054] Specifically, a silicon substrate upper surface dielectric layer 2 and a silicon substrate lower surface dielectric layer 3 are formed on the upper and lower surfaces of the silicon substrate 1 by using the LPCVD process. The material is silicon nitride Si3N4 with a thickness of 50 nm.

[0055] Step 2: Use the RIE process to etch a window area on the silicon substrate lower surface dielectric layer 3 to form an observation window by further wet etching;

[0056] Specifically, use the RIE process to etch a window area on the silicon substrate lower surface dielectric layer 3. The etching depth is greater than 50 nm, and the silicon nitride Si3N4 in the window area is removed to expose the silicon.

[0057] Step 3: Deposit and fabricate metal electrodes on the silicon substrate upper surface dielectric layer 2 by using the PVD process. A circuit module including a heating coil 4, an electrical measurement electrode 5, and a temperature measurement electrode 6 is deposited at the corresponding position of the observation window. The circuit module extends to the edge of the chip to form a chip contact electrode 8 for connection with an external measurement circuit;

[0058] Specifically, use the LIFT-OFF process to form a heating coil 4, an electrical measurement electrode 5, a temperature measurement electrode 6, and a chip contact electrode 8 on the silicon substrate upper surface dielectric layer 2. The circuit module composed of the heating coil 4, the electrical measurement electrode 5, and the temperature measurement electrode 6 is located on the observation window support film 7. The circuit module becomes wider outside the observation window and extends to the edge of the chip as the chip contact electrode 8. The electrode material is gold with a thickness of 100 nm.

[0059] Step 4: Use the RIE process to scribe an annular dicing groove on the silicon substrate upper surface dielectric layer 2;

[0060] Specifically, use the RIE process to etch an annular dicing groove on the silicon substrate upper surface dielectric layer 2. The etching depth is greater than 50 nm, and the silicon nitride Si3N4 at the dicing groove is removed to expose the silicon.

[0061] Step 5: Use the DRIE process to etch and dice the silicon substrate 1 to divide it into multiple chips;

[0062] Specifically, use the deep silicon etching process to etch the wafer downward from the dicing groove. The etching depth is 200 μm to obtain multiple independent chips.

[0063] Step 6: Using a wet etching process, start from the window area of the dielectric layer 3 on the lower surface of the silicon substrate, and etch the silicon substrate 1 from bottom to top until the etching reaches the dielectric layer 2 on the upper surface of the silicon substrate and then stop, thereby forming a hollow area 9 in the silicon substrate. Specifically, use potassium hydroxide etching solution to wet-etch the silicon substrate 1 from bottom to top from the window area etched in Step 2 until the etching reaches the dielectric layer 2 on the upper surface of the silicon substrate and stop, forming a hollow area 9 that penetrates the silicon substrate 1. The dielectric layer 2 on the upper surface of the silicon substrate above the hollow area 9 forms an observation window support film 7.

[0064] Example 2:

[0065] In this example, the structure of the TEM copper mesh-like thermal and electrical analysis chip is the same as above.

[0066] The dielectric layer on the upper surface of the silicon substrate is low-stress Si3N4 with a thickness of 100 nm.

[0067] The materials of the heating coil 4, electrical measurement electrode 5, temperature measurement electrode 6, and chip contact electrode 8 are platinum with a thickness of 120 nm; among them, the line width of the heating coil is 6 μm, and the line widths of the electrical measurement electrode and the temperature measurement electrode are 4 μm.

[0068] The manufacturing method of the TEM copper mesh-like thermal and electrical analysis chip includes the following steps:

[0069] Step 1: Deposit a dielectric layer 2 on the upper surface of the silicon substrate 1 and deposit a dielectric layer 3 on the lower surface of the silicon substrate 1;

[0070] Specifically, use the LPCVD process to form a dielectric layer on the upper surface of the silicon substrate and a dielectric layer 3 on the lower surface of the silicon substrate 1. The material is silicon nitride Si3N4 with a thickness of 100 nm.

[0071] Step 2: Use the RIE process to etch a window area on the dielectric layer 3 on the lower surface of the silicon substrate for further wet etching to form an observation window;

[0072] Specifically, use the RIE process to etch a window area on the dielectric layer 3 on the lower surface of the silicon substrate. The etching depth is greater than 1.10 μm, removing the silicon nitride Si3N4 in the window area and exposing the silicon.

[0073] Step 3: Deposit an observation window heating coil 4, an observation window measurement electrode 5, and an observation window temperature measurement electrode 6 on the dielectric layer 2 on the upper surface of the silicon substrate through the PVD process;

[0074] Specifically, use the LIFT-OFF process to form an observation window heating coil 4, an observation window electrical measurement electrode 5, and an observation window temperature measurement electrode 6 on the dielectric layer 2 on the upper surface of the silicon substrate. The material is platinum with a thickness of 120 nm.

[0075] Step 4: Use the RIE process to etch an annular scribing groove on the dielectric layer 2 on the upper surface of the silicon substrate.

[0076] Specifically, use the RIE process to etch an annular scribing groove on the dielectric layer 2 on the upper surface of the silicon substrate. The etching depth is greater than 100 nm. Remove the silicon nitride Si3N4 at the scribing groove to expose the silicon.

[0077] Step 5: Use the DRIE process to etch and scribe the silicon substrate to divide it into multiple chips.

[0078] Specifically, use the deep silicon etching BOSCH process to etch the wafer downward from the scribing groove. The etching depth is 200 μm to obtain multiple independent chips.

[0079] Step 6: Use the wet etching process to start from the window area of the dielectric layer 3 on the lower surface of the silicon substrate and etch the silicon substrate 1 from bottom to top until the etching reaches the dielectric layer 2 on the upper surface of the silicon substrate and then stop, so as to form a hollow area 9 in the silicon substrate.

[0080] Specifically, use potassium hydroxide etching solution to wet-etch the silicon substrate 1 from bottom to top from the window area etched in Step 2 until the etching reaches the dielectric layer 2 on the upper surface of the silicon substrate and then stop, forming a hollow area 9 that penetrates the silicon substrate 1. The dielectric layer 2 on the upper surface of the silicon substrate above the hollow area 9 forms an observation window support film 7.

Claims

1. A TEM copper mesh type thermal and electrical analysis chip, characterized in that, It includes a silicon substrate, insulating dielectric layers deposited on the upper and lower surfaces of the silicon substrate. The shape and size of the silicon substrate match those of a TEM copper mesh. A hollowed-out area is provided through the silicon substrate and the lower-surface insulating dielectric layer as an observation window. A circuit module is deposited on the surface of the upper-surface insulating dielectric layer above the hollowed-out area. The circuit module includes two sets of heating coils, two sets of electrical measurement electrodes, and a temperature measurement electrode. Both sets of electrical measurement electrodes are comb-shaped and are arranged vertically between the two sets of heating coils. The temperature measurement electrode is arranged on the outermost side of one of the sets of electrical measurement electrodes. The two sets of heating coils, the two sets of electrical measurement electrodes, and the temperature measurement electrode are connected to an external measurement circuit.

2. The imitation TEM copper mesh type thermal and electrical analysis chip according to claim 1, characterized in that Each of the chips includes a plurality of observation windows and corresponding sets of circuit modules.

3. The TEM copper mesh type thermal and electrical analysis chip according to claim 1, characterized in that, The two sets of heating coils are provided with convex structures in the observation window area.

4. The imitation TEM copper mesh type thermal and electrical analysis chip according to claim 1, characterized in that, The two sets of heating coils, the two sets of electrical measurement electrodes, and the temperature measurement electrode extend to the edge of the chip and are connected to the external measurement circuit through chip contact electrodes 8.

5. The imitation TEM copper mesh type thermal and electrical analysis chip according to claim 4, characterized in that, The material of the chip contact electrodes is any one or a combination of nickel, gold, copper, platinum, and tungsten, and the thickness is 100 - 120 nm.

6. The imitation TEM copper mesh type thermal and electrical analysis chip according to claim 1, wherein The upper-surface insulating dielectric layer is any one or a combination of low-stress Si3N4, Al2O3, and SiO2, and the thickness is 20 - 100 nm.

7. The TEM copper mesh type thermal and electrical analysis chip according to claim 1, characterized in that The materials of the heating coils, the electrical measurement electrodes, and the temperature measurement electrode are any one or a combination of nickel, gold, copper, platinum, and tungsten, and the thickness is 100 - 120 nm; among them, the line width of the heating coils is 4 - 8 μm, and the line widths of the electrical measurement electrodes and the temperature measurement electrode are 3 - 6 μm.

8. A method for fabricating a thermal and electrical analysis chip in the shape of a TEM copper mesh imitation, characterized in that, It includes the following steps: (1) Deposit a silicon-substrate upper-surface dielectric layer on the upper surface of the silicon substrate and deposit a silicon-substrate lower-surface dielectric layer on the lower surface of the silicon substrate; (2) Use the RIE process to etch a window area in the silicon-substrate lower-surface dielectric layer so as to further form an observation window by wet etching in step (6); (3) Deposit metal electrodes for manufacturing on the silicon-substrate upper-surface dielectric layer by the PVD process. The circuit module including the heating coils, the electrical measurement electrodes, and the temperature measurement electrode is deposited at the corresponding position of the observation window, and the circuit module extends to the edge of the chip to form chip contact electrodes for connection to an external measurement circuit; (4) Use the RIE process to scribe an annular dicing groove on the silicon-substrate upper-surface dielectric layer; (5) Use the DRIE process to etch and dice the silicon substrate to divide it into multiple chips; (6) Use the wet etching process to start from the window area of the silicon-substrate lower-surface dielectric layer and etch the silicon substrate from bottom to top until the etching reaches the silicon-substrate upper-surface dielectric layer and then stop, thereby forming a hollowed-out area in the silicon substrate as the observation window of the chip.

9. The manufacturing method of the TEM copper mesh type thermal and electrical analysis chip according to claim 8, characterized in that Step (5) specifically is: Use the deep silicon etching process to etch the wafer downward from the dicing groove to obtain multiple independent chips.

10. The manufacturing method of the TEM copper mesh-like thermal and electrical analysis chip according to claim 8, characterized in that Step (6) specifically is: Use a potassium hydroxide etching solution to wet-etch the silicon substrate from bottom to top from the window area etched in step (2) until the etching reaches the silicon-substrate upper-surface dielectric layer and stops, forming a hollowed-out area that penetrates the silicon substrate. The silicon-substrate upper-surface dielectric layer above the hollowed-out area forms an observation window support film.

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