Power supply detection circuit and detection method thereof

Abstract

The present invention discloses a power supply detection circuit and detection method. One end of switch SW0 is connected to the VCOMP signal, the other end of switch SW0 is connected to the output end of the voltage clamp circuit CLAMP, the input end of the power supply detection module is connected to the signal VIN, the first output end of the power supply detection module generates the signal STATE1, and the second output end of the power supply detection module generates the signal STATE2. The OR gate G2 of the power control circuit adopts a three-input OR gate, the second input end of OR gate G2 is connected to the signal STATE2, and the third input end of OR gate G2 is connected to the signal STATE1. The present invention can completely and reliably detect the state of the input voltage source of the power supply system and the state of its connection, so that the power supply can adaptively operate in a predetermined operating state.

Description

Technical Field

[0001] The present invention relates to a detection circuit and a detection method thereof, in particular to a power supply detection circuit and a detection method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As the application scenarios of DC / DC power converters continue to expand, the operating conditions and connection states of the DC / DC power converter's input voltage (i.e., power supply) are also increasing. Therefore, DC / DC power converters need to pre-detect and identify their input operating conditions and connection states to enter the operating state predetermined by the application scenario. In addition, the performance requirements for DC / DC power converters are also constantly increasing, and requirements such as power consumption, stability, safety, and reliability need to be taken into account.

[0003] like Figure 6 As shown, the DC / DC power conversion system of the prior art includes a capacitor C1, a capacitor C2, a capacitor C3, a freewheeling diode D1, an inductor L1, a resistor RO, a resistor RS, a power switch M1 and a power controller U1. One end of the capacitor C1 is connected to the VIN pin of the power controller U1, the cathode of the freewheeling diode D1, one end of the capacitor C2 and one end of the resistor R0, the other end of the capacitor C1 is grounded, the VCC pin of the power controller U1 is connected to one end of the capacitor C2, the other end of the capacitor C2 and the GND pin of the power controller U1 are grounded, the GATE pin of the power controller U1 is connected to the gate of the power switch M1, the CS pin of the power controller U1 is connected to one end of the power switch M1 and one end of the resistor RS to generate a signal VCS, the other end of the resistor RS is grounded, the other end of the power switch M1 is connected to the anode of the freewheeling diode D1 and one end of the inductor L1 to generate a signal VDRAIN, and the other end of the inductor L1 is connected to the other end of the capacitor C2 and the other end of the resistor R0.

[0004] like Figure 7As shown, the power control circuit of the prior art is set in the power controller U1, and the power control circuit includes a holding module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver. The input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier module EA, the non-inverting input end of the error amplifier module EA is connected to the reference voltage Reference1, the output end of the error amplifier module EA is connected to the inverting input end of the comparator CMP1 and generates a signal VCOMP, and the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates a signal PWM, and the output end of the driving circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates a signal GATE.

[0005] Existing DC / DC power converters cannot fully and accurately detect and identify the status of their input power (e.g., power supply capacity) and the status of their connection (e.g., good connection or weak connection), and cannot adaptively enter the working state predetermined by the application scenario. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a power supply detection circuit and a detection method thereof, which detect the state and connection state of the input power supply and enable the power supply to adaptively work in a predetermined working state.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A power supply detection circuit includes a power supply control circuit, a switch SW0, a voltage clamping circuit CLAMP, and a power supply detection module Input State Detection. One end of the switch SW0 is connected to the VCOMP signal of the power supply control circuit, and the other end of the switch SW0 is connected to the output end of the voltage clamping circuit CLAMP. The input end of the power supply detection module Input State Detection is connected to the signal VIN. The first output end of the power supply detection module Input State Detection generates a signal STATE1, and the second output end of the power supply detection module Input State Detection generates a signal STATE2. The OR gate G2 of the power supply control circuit adopts a three-input OR gate. The second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1.

[0009] Furthermore, the power control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit RampGenerator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver, the input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier module EA, the non-inverting input end of the error amplifier module EA is connected to the reference voltage Reference1, the output end of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input end of the comparator CMP1 and generates a signal VCOMP, the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the OR gate G2, the second input end of the OR gate G2 is connected to the signal STATE2, the third input end of the OR gate G2 is connected to the signal STATE1, the output end of the OR gate G2 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver, and the output end of the driving circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates the signal GATE.

[0010] Furthermore, the power supply detection module Input State Detection includes an input voltage divider and filter circuit Divider&Filter, comparators CMP3, CMP4, CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample&Hold, a subtractor Subtractor1, a subtractor Subtractor2, an RS trigger G3, an RS trigger G4, a D trigger G5, a D trigger G6, an AND gate G7, a NOT gate G8, an AND gate G9, a switch SW1, a switch SW2, a current source Isource1 and a current source Isource2, and the input end of the input voltage divider and filter circuit Divider&Filter is connected to the signal VI N, the output end of the input voltage divider and filter circuit Divider & Filter is connected to the non-inverting input end of the comparator CMP3 and generates a signal VIN_DET. The inverting input end of the comparator CMP3 is connected to the reference voltage Reference2. The output end of the comparator CMP3 is connected to the EN end of the timer Counter. The output end of the clock generator OSC is connected to the CK end of the timer Counter and generates a clock signal CLK. The T1 end of the timer Counter is connected to the S end of the RS flip-flop G3. The T2 end of the timer Counter is connected to the CK end of the D flip-flop G5. The T3 end of the timer Counter is connected to the R end of the RS flip-flop G3. The T4 terminal of the timer Counter is connected to the S terminal of the RS trigger G4, the T5 terminal of the timer Counter is connected to the CK terminal of the D trigger G6, the T6 terminal of the timer Counter is connected to the R terminal of the RS trigger G4, the Q terminal of the RS trigger G3 is connected to the control terminal of the switch SW1 and generates a control signal CTRL1, the Q terminal of the RS trigger G4 is connected to the first input terminal of the AND gate G7, the output terminal of the AND gate G7 is connected to the control terminal of the switch SW2 and generates a control signal CTRL2, one end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN, the other end of the switch SW1 is connected to one end of the current source Isource1, and the other end of the switch SW2 is connected to the current source One end of Isource2 is connected, the other end of current source Isource1 and the other end of current source Isource2 are grounded, the input end of the sample and hold module Sample&Hold is connected to the signal VIN_DET, the output end of the sample and hold module Sample&Hold is connected to the positive input end of subtractor Subtractor1 and the positive input end of subtractor Subtractor2, the negative input end of subtractor Subtractor1 is connected to the reference voltage Reference3, the output end of subtractor Subtractor1 is connected to the inverting input end of comparator CMP4, and the non-inverting input end of comparator CMP4 is connected to the signal VIN_DET.The output of comparator CMP4 is connected to the D terminal of D flip-flop G5, the negative input of subtractor2 is connected to reference voltage Reference4, the output of subtractor2 is connected to the inverting input of comparator CMP5, the non-inverting input of comparator CMP5 is connected to signal VIN_DET, the output of comparator CMP5 is connected to the D terminal of D flip-flop G6, the Q terminal of D flip-flop G5 is connected to the second input of AND gate G7 and the input of NOT gate G8, the output of NOT gate G8 is connected to the first input of AND gate G9 and generates signal STATE1, the Q terminal of comparator G6 is connected to the second input of AND gate G9, and the output of AND gate G9 generates signal STATE2.

[0011] Furthermore, the waiting time for the signals T1 - T6 generated by the terminals T1 - T6 of the timer Counter to flip from a logic low level to a logic high level becomes longer successively.

[0012] Furthermore, the switch SW1 is turned on before the switch SW2 is turned on.

[0013] Furthermore, the current source Isource1 and the current source Isource2 are both turned on gradually to a set value with an increasing slope, and the current source Isource1 and the current source Isource2 are both turned off gradually to zero with a decreasing slope.

[0014] A power supply detection method for a power supply detection circuit comprises the following steps:

[0015] The first schematic waveform: At time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN flowing into the VIN pin of the power controller U1 gradually increases with an increasing slope to be equal to the current of the current source Isource1, and the rise time is tm1; at this time, since the source connected to the power system is a weak voltage source, the signal VIN begins to be greatly pulled down by the current IVIN and the drop exceeds Reference3*K, where K is the voltage divider ratio of the voltage divider and filter circuit Divider&Filter; at time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. When the signal VIN drops by more than Reference3*K, the signal STATE1 transitions from a logic low to a logic high, enabling the power control circuit and transmitting a switching waveform to the GATE pin of the power controller U1. The switch SW0 is also turned on, clamping the voltage of the signal VCOMP output by the error amplifier module EA, allowing the power control loop to operate within a defined state. At time T3, the T3 terminal of the timer Counter transitions from a logic high to a logic high, turning off the switch SW1. The current IVIN gradually returns to zero with a decreasing slope, with a fall time of tm2. Because the signal STATE1 transitions to a logic high at time T2, the detection circuit for the signal STATE2 is disabled, causing the signal STATE2 to remain at a constant logic low.

[0016] Second schematic waveform: At time T0, signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time tm1. At this time, since the source connected to the power system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to normal with a falling slope. Returns to zero with a fall time of tm2; at time T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope until it is equal to the current of the current source Isource2, with a rise time of tm3; at this time, since the state of the signal VIN connected to the input voltage source is a weak connection state, there is a large connection impedance in the connection path, and the voltage of the signal VIN begins to be significantly pulled down by the current IVIN, with a drop exceeding Reference4*K; at time T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, and detects that the drop of the signal VIN exceeds Reference4*K, so that the signal STATE2 remains at a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1; at time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope with a fall time of tm4;

[0017] The third schematic waveform: at time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN gradually increases with an increasing slope to be equal to the current of the current source Isource1, and the rise time is tm1. At this time, since the source connected to the power system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from a logic level to a logic high level, thereby turning off the switch SW1, and the current I VIN gradually returns to zero with a decreasing slope, and the falling time is tm2. At T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, so that the current IVIN gradually increases with a rising slope to be equal to the current of the current source Isource2, and the rising time is tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance in the connection path, the voltage of the signal VIN begins to be slightly pulled down by IVIN, and the drop does not exceed Reference4*K. At T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, and it is detected that the drop of the signal VIN does not exceed Reference4*K, so that the signal STATE2 changes from a logic low level to a logic high level, thereby enabling the power control circuit and transmitting the switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at a logic low level, the signal VCOMPD output by the error amplifier module EA is not enabled. The voltage is clamped, and the power control loop is not restricted by the clamp. At time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2. The current IVIN gradually returns to zero with a decreasing slope, and the fall time is tm4.

[0018] The input voltage divider and filter circuit Divider&Filter divides the signal VIN and removes high-frequency disturbances through filtering, and outputs a processable signal VIN_DET; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 is turned on and / or before the switch SW2 is turned on, and holds the sample value VHOLD after the switch SW1 is turned on and / or after the switch SW2 is turned on; the held sample value VHOLD is passed through subtractor1 and subtractor2 to generate a reference voltage for the detection state, which serves as the reference voltage for comparator CMP4 and comparator CMP5 respectively; the moment when the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter flip from a logic low level to a logic high level The waiting time becomes longer successively; the moment when the switch SW1 is turned on is before the moment when the switch SW2 is turned on, the current source Isource1 and the current source Isource2 are respectively enabled to pull down the current to detect the power status and connection status of the external VIN pin of the power controller U1, and the detection duration is set by the timer Counter. The current source Isource1 and the current source Isource2 are both turned on in a manner that gradually opens to the set value with an increasing slope, and the current source Isource1 and the current source Isource2 are both turned off in a manner that gradually closes to zero with a decreasing slope; when the signal STATE1 is at a logic level high, the conduction of the switch SW2 and the detection of the external connection status of the VIN pin of the power controller U1 by pulling down the current are not enabled.

[0019] Compared with the prior art, the present invention has the following advantages and effects:

[0020] 1. The present invention can completely and reliably detect the state of the input voltage source of the power supply system and the state of the connection thereto, so that the power supply can adaptively operate in a predetermined working state;

[0021] 2. The present invention does not increase the number of peripheral detection components in the system, thus saving system costs and increasing the power consumption of the chip, thereby keeping the total power consumption of the chip at a very low level.

[0022] 3. The detection current for power status and connection status detection of the present invention is gradually turned on to the set value in an ascending slope manner when enabled, and gradually turned off to zero in a descending slope manner when disabled. This can reduce the downward ringing and / or upward ringing caused by parasitic inductance and capacitance, improve the detection accuracy, and reduce the stress of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of a power supply detection circuit of the present invention.

[0024] Figure 2This is a circuit diagram of the power supply detection module Input State Detection of the present invention.

[0025] Figure 3 This is a first schematic waveform diagram of a power supply detection circuit of the present invention.

[0026] Figure 4 This is a second schematic waveform diagram of a power supply detection circuit of the present invention.

[0027] Figure 5 This is a third schematic waveform diagram of a power supply detection circuit of the present invention.

[0028] Figure 6 Schematic diagram of a DC / DC power conversion system in the prior art.

[0029] Figure 7 Schematic diagram of a power supply control circuit in the prior art. DETAILED DESCRIPTION

[0030] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0031] like Figure 1 As shown, a power supply detection circuit of the present invention includes a power supply control circuit, a switch SW0, a voltage clamping circuit CLAMP and a power supply detection module Input State Detection. One end of the switch SW0 is connected to the VCOMP signal of the power supply control circuit, and the other end of the switch SW0 is connected to the output end of the voltage clamping circuit CLAMP. The input end of the power supply detection module Input State Detection is connected to the signal VIN. The first output end of the power supply detection module Input State Detection generates a signal STATE1, and the second output end of the power supply detection module Input State Detection generates a signal STATE2. The OR gate G2 of the power control circuit adopts a three-input OR gate. The second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1.

[0032] The power supply control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver. The input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier module EA, the non-inverting input end of the error amplifier module EA is connected to the reference voltage Reference1, the output end of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input end of the comparator CMP1 and generates a signal VCOMP. The ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the OR gate G2, the second input end of the OR gate G2 is connected to the signal STATE2, the third input end of the OR gate G2 is connected to the signal STATE1, the output end of the OR gate G2 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver, and the output end of the driving circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates the signal GATE.

[0033] like Figure 2As shown, the power supply detection module Input State Detection includes an input voltage divider and filter circuit Divider&Filter, comparators CMP3, CMP4, and CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample&Hold, subtractors Subtractor1 and Subtractor2, RS flip-flops G3 and G4, D flip-flops G5 and G6, an AND gate G7, a NOT gate G8 and G9, a switch SW1 and a switch SW2, a current source Isource1, and a current source Isource2. The input end of the input voltage divider and filter circuit Divider&Filter is connected to the signal VI. N, the output end of the input voltage divider and filter circuit Divider & Filter is connected to the non-inverting input end of the comparator CMP3 and generates a signal VIN_DET. The inverting input end of the comparator CMP3 is connected to the reference voltage Reference2. The output end of the comparator CMP3 is connected to the EN end of the timer Counter. The output end of the clock generator OSC is connected to the CK end of the timer Counter and generates a clock signal CLK. The T1 end of the timer Counter is connected to the S end of the RS flip-flop G3. The T2 end of the timer Counter is connected to the CK end of the D flip-flop G5. The T3 end of the timer Counter is connected to the R end of the RS flip-flop G3. The T4 terminal of the timer Counter is connected to the S terminal of the RS trigger G4, the T5 terminal of the timer Counter is connected to the CK terminal of the D trigger G6, the T6 terminal of the timer Counter is connected to the R terminal of the RS trigger G4, the Q terminal of the RS trigger G3 is connected to the control terminal of the switch SW1 and generates a control signal CTRL1, the Q terminal of the RS trigger G4 is connected to the first input terminal of the AND gate G7, the output terminal of the AND gate G7 is connected to the control terminal of the switch SW2 and generates a control signal CTRL2, one end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN, the other end of the switch SW1 is connected to one end of the current source Isource1, and the other end of the switch SW2 is connected to the current source One end of Isource2 is connected, the other end of current source Isource1 and the other end of current source Isource2 are grounded, the input end of the sample and hold module Sample&Hold is connected to the signal VIN_DET, the output end of the sample and hold module Sample&Hold is connected to the positive input end of subtractor Subtractor1 and the positive input end of subtractor Subtractor2, the negative input end of subtractor Subtractor1 is connected to the reference voltage Reference3, the output end of subtractor Subtractor1 is connected to the inverting input end of comparator CMP4, and the non-inverting input end of comparator CMP4 is connected to the signal VIN_DET.The output of comparator CMP4 is connected to the D terminal of D flip-flop G5, the negative input of subtractor2 is connected to reference voltage Reference4, the output of subtractor2 is connected to the inverting input of comparator CMP5, the non-inverting input of comparator CMP5 is connected to signal VIN_DET, the output of comparator CMP5 is connected to the D terminal of D flip-flop G6, the Q terminal of D flip-flop G5 is connected to the second input of AND gate G7 and the input of NOT gate G8, the output of NOT gate G8 is connected to the first input of AND gate G9 and generates signal STATE1, the Q terminal of comparator G6 is connected to the second input of AND gate G9, and the output of AND gate G9 generates signal STATE2.

[0034] The waiting time for the signals T1 - T6 generated by the terminals T1 - T6 of the timer Counter to switch from a logic low level to a logic high level becomes longer in sequence.

[0035] When the switch SW1 is turned on before the switch SW2 is turned on, the current sources Isource1 and Isource2 are enabled to pull down the current to detect the power status and connection status of the external power supply of the VIN pin of the power controller U1. The detection duration is set by the timer Counter.

[0036] The current source Isource1 and the current source Isource2 are both turned on gradually to a set value with an increasing slope, and the current source Isource1 and the current source Isource2 are both turned off gradually to zero with a decreasing slope.

[0037] A power supply detection method for a power supply detection circuit comprises the following steps:

[0038] like Figure 3As shown in the first schematic waveform: at time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN flowing into the VIN pin of the power controller U1 gradually increases with a rising slope to be equal to the current of the current source Isource1, with a rise time tm1; at this time, because the source connected to the power system is a weak voltage source, the signal VIN begins to be significantly pulled down by the current IVIN and the drop exceeds Reference3*K, where K is the voltage divider ratio of the voltage divider and filter circuit Divider&Filter; at time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level, At this time, it is detected that the signal VIN drops by more than Reference3*K, causing the signal STATE1 to change from a logic low level to a logic high level, enabling the power control circuit and transmitting the switching waveform to the GATE pin of the power controller U1, and turning on the switch SW0, enabling the voltage clamping of the signal VCOMP output by the error amplifier module EA, so that the power control loop operates in the set limited state; at time T3, the T3 end of the timer Counter changes from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a decreasing slope, and the fall time is tm2; because the signal STATE1 flips to a logic high level at time T2, the detection circuit for the signal STATE2 is disabled, thereby causing the signal STATE2 to be constantly at a logic low level.

[0039] Among them, the signal VIN is the voltage on the VIN pin of the power controller U1, the current IVIN is the current flowing into the VIN pin of the power controller U1, the signal STATE1 is the logic level of the first output end of the power supply detection circuit, the signal STATE2 is the logic level of the second output end of the power supply detection circuit, and the signal GATE is the voltage on the GATE pin of the power controller U1.

[0040] like Figure 4As shown in the second schematic waveform: at time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN gradually increases with an increasing slope to be equal to the current of the current source Isource1, and the rise time is tm1; at this time, since the source connected to the power system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K; at time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is transmitted to the GATE pin of the power controller U1; at time T3, the T3 terminal of the timer Counter changes from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually decreases with a decreasing slope. At time T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase to equal the current of the current source Isource2 with a rising slope, and the rise time is tm3. At this time, because the signal VIN is in a weak connection state with the input voltage source and there is a large connection impedance in the connection path, the voltage of the signal VIN begins to be significantly pulled down by the current IVIN, and the drop exceeds Reference4*K. At time T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, and detects that the drop of the signal VIN exceeds Reference4*K, so that the signal STATE2 remains at a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1. At time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm4.

[0041] like Figure 5As shown in the third schematic waveform: at time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 end of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN gradually increases with an increasing slope to be equal to the current of the current source Isource1, and the rise time is tm1; at this time, since the source connected to the power supply system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K; at time T2, the T2 end of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is transmitted to the GATE pin of the power controller U1; at time T3, the T3 end of the timer Counter changes from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a decreasing slope, and the falling time is tm2. At T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, so that the current IVIN gradually increases with a rising slope to be equal to the current of the current source Isource2, and the rising time is tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance in the connection path, the voltage of the signal VIN begins to be slightly pulled down by IVIN, and the drop does not exceed Reference4*K. At T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, and it is detected that the drop of the signal VIN does not exceed Reference4*K, so that the signal STATE2 changes from a logic low level to a logic high level, thereby enabling the power control circuit and transmitting the switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at a logic low level, the signal VCOMPD output by the error amplifier module EA is not enabled. The voltage is clamped, and the power control loop is not restricted by the clamp. At time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2. The current IVIN gradually returns to zero with a decreasing slope, and the fall time is tm4.

[0042] The input voltage divider and filter circuit Divider&Filter divides the signal VIN and removes high-frequency disturbances through filtering, and outputs a processable signal VIN_DET; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 is turned on and / or before the switch SW2 is turned on, and holds the sample value VHOLD after the switch SW1 is turned on and / or after the switch SW2 is turned on; the held sample value VHOLD is passed through subtractor1 and subtractor2 to generate a reference voltage for the detection state, which serves as the reference voltage for comparator CMP4 and comparator CMP5 respectively; the moment when the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter flip from a logic low level to a logic high level The waiting time becomes longer successively; the moment when the switch SW1 is turned on is before the moment when the switch SW2 is turned on, the current source Isource1 and the current source Isource2 are respectively enabled to pull down the current to detect the power status and connection status of the external VIN pin of the power controller U1, and the detection duration is set by the timer Counter. The current source Isource1 and the current source Isource2 are both turned on in a manner that gradually opens to the set value with an increasing slope, and the current source Isource1 and the current source Isource2 are both turned off in a manner that gradually closes to zero with a decreasing slope; when the signal STATE1 is at a logic level high, the conduction of the switch SW2 and the detection of the external connection status of the VIN pin of the power controller U1 by pulling down the current are not enabled.

[0043] The present invention can completely and reliably detect the state of the input voltage source of the power supply system and the state of the connection thereto, so that the power supply can adaptively operate in a predetermined working state; the present invention does not increase the peripheral detection elements of the system, saves system costs, and does not increase the power consumption of the chip, so that the total power consumption of the chip is at a very low level; the detection current for detecting the power supply state and the connection state of the present invention is gradually turned on to the set value in an increasing slope manner when enabled, and is gradually turned off to zero in a decreasing slope manner when disabled, which can reduce the downward ringing and / or upward ringing caused by parasitic inductance and capacitance, improve the detection accuracy, and reduce the stress of the power device.

[0044] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A power supply detection circuit, characterized in that: The device comprises a power control circuit, a switch SW0, a voltage clamp circuit CLAMP, and a power supply detection module Input State Detection. One end of the switch SW0 is connected to the VCOMP signal of the power control circuit, and the other end of the switch SW0 is connected to the output end of the voltage clamp circuit CLAMP. The input end of the power supply detection module Input State Detection is connected to the signal VIN. The first output end of the power supply detection module Input State Detection generates a signal STATE1, and the second output end of the power supply detection module Input State Detection generates a signal STATE2. The OR gate G2 of the power control circuit adopts a three-input OR gate. The second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1. The power supply detection module Input State Detection includes an input voltage divider and filter circuit Divider & Filter, comparators CMP3, CMP4, CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample & Hold, a subtractor Subtractor1, a subtractor Subtractor2, an RS trigger G3, an RS trigger G4, a D trigger G5, a D trigger G6, an AND gate G7, a NOT gate G8, an AND gate G9, a switch SW1, a switch SW2, a current source Isource1 and a current source Isource2. The input end of the input voltage divider and filter circuit Divider & Filter is connected to the signal VI N, the output end of the input voltage divider and filter circuit Divider & Filter is connected to the non-inverting input end of the comparator CMP3 and generates a signal VIN_DET. The inverting input end of the comparator CMP3 is connected to the reference voltage Reference2. The output end of the comparator CMP3 is connected to the EN end of the timer Counter. The output end of the clock generator OSC is connected to the CK end of the timer Counter and generates a clock signal CLK. The T1 end of the timer Counter is connected to the S end of the RS flip-flop G3. The T2 end of the timer Counter is connected to the CK end of the D flip-flop G5. The T3 end of the timer Counter is connected to the R end of the RS flip-flop G3. The T4 terminal of the timer Counter is connected to the S terminal of the RS trigger G4, the T5 terminal of the timer Counter is connected to the CK terminal of the D trigger G6, the T6 terminal of the timer Counter is connected to the R terminal of the RS trigger G4, the Q terminal of the RS trigger G3 is connected to the control terminal of the switch SW1 and generates a control signal CTRL1, the Q terminal of the RS trigger G4 is connected to the first input terminal of the AND gate G7, the output terminal of the AND gate G7 is connected to the control terminal of the switch SW2 and generates a control signal CTRL2, one end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN, the other end of the switch SW1 is connected to one end of the current source Isource1, and the other end of the switch SW2 is connected to the current source One end of Isource2 is connected, the other end of current source Isource1 and the other end of current source Isource2 are grounded, the input end of the sample and hold module Sample&Hold is connected to the signal VIN_DET, the output end of the sample and hold module Sample&Hold is connected to the positive input end of subtractor Subtractor1 and the positive input end of subtractor Subtractor2, the negative input end of subtractor Subtractor1 is connected to the reference voltage Reference3, the output end of subtractor Subtractor1 is connected to the inverting input end of comparator CMP4, and the non-inverting input end of comparator CMP4 is connected to the signal VIN_DET.The output of comparator CMP4 is connected to the D terminal of D flip-flop G5, the negative input of subtractor2 is connected to reference voltage Reference4, the output of subtractor2 is connected to the inverting input of comparator CMP5, the non-inverting input of comparator CMP5 is connected to signal VIN_DET, the output of comparator CMP5 is connected to the D terminal of D flip-flop G6, the Q terminal of D flip-flop G5 is connected to the second input of AND gate G7 and the input of NOT gate G8, the output of NOT gate G8 is connected to the first input of AND gate G9 and generates signal STATE1, the Q terminal of comparator G6 is connected to the second input of AND gate G9, and the output of AND gate G9 generates signal STATE2.

2. A power supply detection circuit according to claim 1, characterized in that: The power control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver. The input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier module EA, the non-inverting input end of the error amplifier module EA is connected to the reference voltage Reference1, the output end of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input end of the comparator CMP1 to generate a signal VCOMP, and the ramp generating circuit Ramp Generator is connected to the inverting input end of the comparator CMP1 to generate a signal VCOMP. The output end of the ator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the OR gate G2, the second input end of the OR gate G2 is connected to the signal STATE2, the third input end of the OR gate G2 is connected to the signal STATE1, the output end of the OR gate G2 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver, and the output end of the driving circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates the signal GATE.

3. The power supply detection circuit according to claim 1, wherein: The waiting time for the signals T1 - T6 generated by the terminals T1 - T6 of the timer Counter to flip from a logic low level to a logic high level becomes longer in sequence.

4. The power supply detection circuit according to claim 1, wherein: The switch SW1 is turned on before the switch SW2 is turned on.

5. The power supply detection circuit according to claim 1, wherein: The current source Isource1 and the current source Isource2 are both turned on gradually to a set value with an increasing slope, and are both turned off gradually to zero with a decreasing slope.

6. A power supply detection method based on the power supply detection circuit according to claim 1, characterized in that The following steps are involved: The first schematic waveform: At time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN flowing into the VIN pin of the power controller U1 gradually increases with a rising slope until it is equal to the current of the current source Isource1, and the rise time is tm1. At this time, because the source connected to the power system is a weak voltage source, the signal VIN begins to be significantly pulled down by the current IVIN and the drop exceeds Reference3*K , where K is the voltage divider ratio of the Divider & Filter circuit; at time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the signal VIN drops by more than Reference3*K, causing the signal STATE1 to change from a logic low level to a logic high level, enabling the power control circuit and transmitting the switching waveform to the GATE pin of the power controller U1. The switch SW0 is also turned on, enabling the voltage clamping of the signal VCOMP output by the error amplifier module EA, so that the power control loop operates in the set limit state; At time T3, the T3 terminal of the timer Counter changes from a logic low level to a logic high level, turning off the switch SW1. The current IVIN gradually returns to zero with a decreasing slope, and the falling time is tm2. Because the signal STATE1 flips to a logic high level at time T2, the detection circuit for the signal STATE2 is disabled, causing the signal STATE2 to remain at a constant logic low level. Second schematic waveform: At time T0, signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time tm1. At this time, since the source connected to the power system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually decreases with a falling slope. Returns to zero, with a fall time of tm2; at time T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope until it is equal to the current of the current source Isource2, with a rise time of tm3; at this time, because the state of the signal VIN connected to the input voltage source is a weak connection state, there is a large connection impedance in the connection path, and the voltage of the signal VIN begins to be significantly pulled down by the current IVIN, with a drop exceeding Reference4*K; at time T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, detecting that the drop of the signal VIN exceeds Reference4*K, so that the signal STATE2 remains at a logic low level, and the power control circuit is still not enabled and the switching waveform is not transmitted to the GATE pin of the power controller U1; at time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm4; The third schematic waveform: at time T0, the signal VIN is powered on and stabilized, and the timer Counter starts working. At time T1, the T1 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW1, so that the current IVIN gradually increases with an increasing slope to be equal to the current of the current source Isource1, and the rise time is tm1. At this time, since the source connected to the power system is a powerful voltage source, the signal VIN begins to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, so that the signal STATE1 still maintains a logic low level, and the power control circuit is still not enabled and the switching waveform is transmitted to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW1, and the current I VIN gradually returns to zero with a decreasing slope, and the falling time is tm2. At T4, the T4 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning on the switch SW2, so that the current IVIN gradually increases with a rising slope to be equal to the current of the current source Isource2, and the rising time is tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance in the connection path, the voltage of the signal VIN begins to be slightly pulled down by IVIN, and the drop does not exceed Reference4*K. At T5, the T5 terminal of the timer Counter changes from a logic low level to a logic high level, and it is detected that the drop of the signal VIN does not exceed Reference4*K, so that the signal STATE2 changes from a logic low level to a logic high level, thereby enabling the power control circuit and transmitting the switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at a logic low level, the signal VCOMPD output by the error amplifier module EA is not enabled. The voltage is clamped, and the power control loop is not restricted by the clamp. At time T6, the T6 terminal of the timer Counter changes from a logic low level to a logic high level, thereby turning off the switch SW2. The current IVIN gradually returns to zero with a decreasing slope, and the fall time is tm4. The input voltage divider and filter circuit Divider&Filter divides the signal VIN and removes high-frequency disturbances through filtering, and outputs a processable signal VIN_DET; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 is turned on and / or before the switch SW2 is turned on, and holds the sample value VHOLD after the switch SW1 is turned on and / or after the switch SW2 is turned on; the held sample value VHOLD is passed through subtractor1 and subtractor2 to generate a reference voltage for the detection state, which serves as the reference voltage for comparator CMP4 and comparator CMP5 respectively; the moment when the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter flip from a logic low level to a logic high level The waiting time becomes longer successively; the moment when the switch SW1 is turned on is before the moment when the switch SW2 is turned on, the current source Isource1 and the current source Isource2 are respectively enabled to pull down the current to detect the power status and connection status of the external VIN pin of the power controller U1, and the detection duration is set by the timer Counter. The current source Isource1 and the current source Isource2 are both turned on in a manner that gradually opens to the set value with an increasing slope, and the current source Isource1 and the current source Isource2 are both turned off in a manner that gradually closes to zero with a decreasing slope; when the signal STATE1 is at a logic level high, the conduction of the switch SW2 and the detection of the external connection status of the VIN pin of the power controller U1 by pulling down the current are not enabled.

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