Switching value input circuit

Abstract

The invention provides a switching value input circuit, which comprises a digital quantity acquisition module, an analog quantity acquisition module, a power supply, a power supply monitoring module and a CPU (Central Processing Unit) calculation module, the digital quantity acquisition module and the analog quantity acquisition module are respectively used for acquiring voltage digital quantity and analog quantity of a contact A and transmitting data to an FPGA (Field Programmable Gate Array) and an ARM (Advanced RISC Machines) module in a CPU (Central Processing Unit) calculation module; the power supply and the power supply monitoring module are connected with the contact B to provide an isolation power supply and monitor the voltage analog quantity of the contact B; the FPGA module and the ARM module respectively process the digital quantity and the analog quantity of the voltage to obtain a judgment result whether an external relay is conducted or not, and the judgment result is output when the results are consistent; in addition, the ARM module is also responsible for monitoring power supply abnormity and controlling alarm when the power supply abnormity occurs. Through dual acquisition and judgment, the circuit improves the reliability and safety of switching value input.

Description

Technical Field

[0001] The present invention relates to the field of electrical technology, and particularly to a digital input circuit. Background Art

[0002] Most electrical automatic control products use digital input signals. Its input circuit is an essential part of digital acquisition. The correctness of digital signals is a prerequisite for product functions and automatic control logics. For example, the breaker position, switch position, etc. collected by secondary equipment in the power industry play a decisive role in the correctness of relay protection functions and five-prevention logic actions. Whether the digital signal is reliable directly affects the stability and reliability of the operation of the power digital input circuit.

[0003] In the basic circuit design and input signal determination method, conventional digital input circuits may not be able to meet the influence of complex environments, and there is a probability of misjudgment, thus causing huge losses. Currently, most conventional input circuits consider that 1 is collected when the external relay contact is closed, and 0 is collected when there is no closed digital input contact externally. Therefore, if the circuit is interfered, 0 or 1 may be misjudged as 1 or 0, directly affecting the logical judgment of the control digital input circuit. Therefore, more reliable processing can be performed on important input signals. In response to this, there is currently a method of using 3 input circuits simultaneously to judge the same input signal. If more than 2 circuits are 1, it is considered 1; if more than 2 circuits are 0, it is considered 0. However, this method does not consider the common problems of the 3 input circuits. In the event of electromagnetic interference in the same direction, it is very likely that all 3 circuits will be misjudged simultaneously.

[0004] Therefore, it is necessary to design a highly reliable digital input circuit to avoid environmental interferences in multiple dimensions and meet application scenarios with high reliability and high security. Summary of the Invention

[0005] The purpose of the present invention is to provide a digital input circuit to improve the reliability of digital input.

[0006] To achieve the above purpose, the present invention provides a digital input circuit, including:

[0007] A digital acquisition module, configured to acquire the digital quantity of the voltage at contact A and transmit it to the FPGA module of the CPU calculation module;

[0008] An analog acquisition module, configured to acquire the analog quantity of the voltage at contact A and transmit it to the ARM module of the CPU calculation module;

[0009] A power supply and a power supply monitoring module, which are used to connect to contact B, isolate and output the internal power supply to contact B, and at the same time collect the voltage analog quantity of contact B and transmit it to the ARM module of the CPU calculation module; among them,

[0010] Contact A and contact B are connected through an external relay;

[0011] The CPU calculation module includes an FPGA module and an ARM module. The FPGA module is used to process the voltage digital quantity to obtain a first judgment result on whether the external relay is turned on. The ARM module is used to process the voltage analog quantity to obtain a second judgment result on whether the external relay is turned on. If the second judgment result is consistent with the first judgment result, the first judgment result or the second judgment result is output; the ARM module is also used to judge whether the power supply is abnormal according to the voltage analog quantity of contact B. If it is abnormal, it controls the power supply and the power supply monitoring module to give an alarm.

[0012] Preferably, the digital quantity acquisition module includes:

[0013] The first end of the protection device D1 is connected to contact A, and the second end is connected to the second grounding end GAND2; the first end of the current limiting resistor R1 is connected to the first end of the protection device D1, and the second end is connected to the primary side of the optocoupler U3; the first end of the current limiting resistor R3 is connected to the second end of the protection device D1, and the second end is connected to the secondary side of the optocoupler U4; the first end of the filter capacitor C1 is connected to the second end of the current limiting resistor R1, and the second end is connected to the second end of the current limiting resistor R3; the first end of the pull-up resistor R2 is connected to the power input VCC1, and the second end is connected to the secondary side of the optocoupler U3; the secondary side of the optocoupler U3 is also connected to the first grounding end GAND1; the first end of the current limiting resistor R4 is connected to the primary side of the optocoupler U4, and the second end is connected to the PO output pin of the FPGA module; the primary side of the optocoupler U4 is also connected to the first grounding end GAND1; the first end of the filter capacitor is connected to the secondary side of the optocoupler U3 and the PI output end of the FPGA module, and the second end is connected to the first grounding end GAND1.

[0014] Preferably, the analog quantity acquisition module includes:

[0015] The first end of the protection device D2 is connected to the contact point A and the first end of the current-limiting resistor R5, and the second end is connected to the second ground terminal GAND2 and the first end of the current-limiting resistor R7; the first end of the sampling resistor R13 is connected to the second end of the current-limiting resistor R5 and the non-inverting input terminal of the isolation operational amplifier differential module U5, and the second end is connected to the second end of the current-limiting resistor R7 and the inverting input terminal of the isolation operational amplifier differential module U5; the filter capacitor C4 is connected in parallel with the sampling resistor R13; the first end of the current-limiting resistor R6 is connected to the positive differential signal output terminal of the isolation operational amplifier differential module U5, and the second end is connected to the first end of the filter capacitor C5 and the positive input terminal of the first analog-to-digital conversion module ADC1; the first end of the current-limiting resistor R8 is connected to the negative differential signal output terminal of the isolation operational amplifier differential module U5, and the second end is connected to the second end of the filter capacitor C5 and the negative input terminal of the first analog-to-digital conversion module ADC1.

[0016] Preferably, the power supply and power supply monitoring module includes:

[0017] The first end of the protection device D3 is connected to the contact point B and the first end of the current-limiting resistor R9, and the second end is connected to the second ground terminal GAND2 and the first end of the current-limiting resistor R11; the first end of the sampling resistor R14 is connected to the second end of the current-limiting resistor R9 and the non-inverting input terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the current-limiting resistor R11 and the inverting input terminal of the isolation operational amplifier differential module U6; the filter capacitor C6 is connected in parallel with the sampling resistor R14; the first end of the current-limiting resistor R10 is connected to the positive differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the first end of the filter capacitor C7 and the positive input terminal of the first analog-to-digital conversion module ADC2; the first end of the current-limiting resistor R12 is connected to the negative differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the filter capacitor C7 and the negative input terminal of the second analog-to-digital conversion module ADC2;

[0018] The first input terminal of the isolated DC-DC power module U7 is connected to the internal power supply VCC1, the second input terminal is connected to the first ground terminal GND1, the first output terminal is connected to the contact point B, and the second output terminal is connected to the second ground terminal GND2.

[0019] Preferably, the FPGA module includes an FPGA processing unit, PI input pins, PO output pins, and a ground pin GND, and the ground pin GND of the FPGA module is connected to the first ground terminal GND1.

[0020] Preferably, there are at least one or more empty pins between the PI and PO pins of the FPGA module.

[0021] Preferably, the ARM module includes an ARM processing unit, a first analog-to-digital conversion module ADC1, a second analog-to-digital conversion module ADC2, a power input pin VCC, and a ground pin GND. The power input pin VCC is connected to the internal power supply VCC1, and the ground pin GND of the ARM module is connected to the first ground terminal GND1.

[0022] Preferably, there is at least one empty pin between the first analog-to-digital conversion module ADC1 and the second analog-to-digital conversion module ADC2 of the ARM module.

[0023] A switch input circuit proposed by the present invention has the following beneficial effects:

[0024] Adopting a dual acquisition method of a digital quantity acquisition module and an analog quantity acquisition module to simultaneously acquire the voltage signal of contact point A in digital and analog quantities, so that the authenticity of the input signal can be verified from two different dimensions; the digital quantity acquisition module processes the voltage digital quantity through the FPGA module, and the analog quantity acquisition module processes the voltage analog quantity through the ARM module. The two modules work independently to obtain the first judgment result and the second judgment result of whether it is conducting respectively. By comparing the two results, the accuracy of the judgment can be effectively improved; the design of the power supply and power supply monitoring module not only provides a stable power supply for the circuit, but also monitors the voltage analog quantity of contact point B in real time. The ARM module judges whether the power supply is abnormal, ensuring the reliability of the power supply, and alarming when the power supply is abnormal, enhancing the safety of the switch input circuit; contact point A and contact point B are connected through an external relay and are acquired separately. Even if the signal of contact point A is unstable due to certain reasons of the external relay, the signal of contact point B can still be used as a reference. Through internal power supply monitoring, the reliability of signal acquisition is further improved; if the first judgment result and the second judgment result are consistent, the judgment result is output. If the results are inconsistent, further measures can be taken, such as resampling, issuing a warning, or adopting other error handling mechanisms, to ensure the stable operation of the switch input circuit; through the above technical solutions, the present invention can effectively avoid the misjudgment risk that may be brought by a single acquisition method or a single power supply monitoring, greatly improving the reliability and safety of the switch input circuit, and is applicable to the field of electrical automatic control with extremely high requirements for the correctness of switch signals. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiment descriptions. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1This is the circuit diagram of a digital input circuit in an embodiment of the present invention. Detailed implementation mode

[0027] The detailed description of the drawings is intended as an illustration of the current embodiment of the present invention, rather than being intended to represent the only form in which the present invention can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of the present invention.

[0028] Refer to Figure 1 , an embodiment of the present invention provides a digital input circuit, including:

[0029] A digital quantity acquisition module, configured to acquire the voltage digital quantity of contact point A and transmit it to the FPGA module U1 of the CPU calculation module;

[0030] An analog quantity acquisition module, configured to acquire the voltage analog quantity of contact point A and transmit it to the ARM module U2 of the CPU calculation module;

[0031] A power supply and power supply monitoring module, configured to connect to contact point B, isolate and output the internal power supply to contact point B, and at the same time acquire the voltage analog quantity of contact point B and transmit it to the ARM module U2 of the CPU calculation module; wherein, contact point A and contact point B are connected through an external relay;

[0032] The CPU calculation module includes an FPGA module U1 and an ARM module U2. The FPGA module U1 is configured to process the voltage digital quantity to obtain a first judgment result on whether the external relay is turned on. The ARM module U2 is configured to process the voltage analog quantity to obtain a second judgment result on whether the external relay is turned on. If the second judgment result is consistent with the first judgment result, the first judgment result or the second judgment result is output; the ARM module U2 is further configured to judge whether the power supply is abnormal according to the voltage analog quantity of contact point B. If it is abnormal, the power supply and power supply monitoring module is controlled to give an alarm.

[0033] Further, the digital quantity acquisition module includes:

[0034] The first end of the protection device D1 is connected to the contact point A, and the second end is connected to the second ground terminal GAND2; the first end of the current-limiting resistor R1 is connected to the first end of the protection device D1, and the second end is connected to the primary side of the optocoupler U3; the first end of the current-limiting resistor R3 is connected to the second end of the protection device D1, and the second end is connected to the secondary side of the optocoupler U4; the first end of the filter capacitor C1 is connected to the second end of the current-limiting resistor R1, and the second end is connected to the second end of the current-limiting resistor R3; the first end of the pull-up resistor R2 is connected to the power input VCC1, and the second end is connected to the secondary side of the optocoupler U3; the secondary side of the optocoupler U3 is also connected to the first ground terminal GAND1; the first end of the current-limiting resistor R4 is connected to the primary side of the optocoupler U4, and the second end of the current-limiting resistor R4 is connected to the PO output pin of the FPGA module U1; the primary side of the optocoupler U4 is also connected to the first ground terminal GAND1; the first end of the filter capacitor is connected to the secondary side of the optocoupler U3 and the PI output terminal of the FPGA module U1, and the second end is connected to the first ground terminal GAND1.

[0035] Further, the analog quantity acquisition module includes:

[0036] The first end of the protection device D2 is connected to the contact point A and the first end of the current-limiting resistor R5, and the second end is connected to the second ground terminal GAND2 and the first end of the current-limiting resistor R7; the first end of the sampling resistor R13 is connected to the second end of the current-limiting resistor R5 and the non-inverting input terminal of the isolation operational amplifier differential module U5, and the second end is connected to the second end of the current-limiting resistor R7 and the inverting input terminal of the isolation operational amplifier differential module U5; the filter capacitor C4 is connected in parallel with the sampling resistor R13; the first end of the current-limiting resistor R6 is connected to the positive differential signal output terminal of the isolation operational amplifier differential module U5, and the second end is connected to the first end of the filter capacitor C5 and the positive input terminal of the first analog-to-digital conversion module ADC1; the first end of the current-limiting resistor R8 is connected to the negative differential signal output terminal of the isolation operational amplifier differential module U5, and the second end is connected to the second end of the filter capacitor C5 and the negative input terminal of the first analog-to-digital conversion module ADC1.

[0037] Further, the power supply and power supply monitoring module includes:

[0038] The first end of the protection device D3 is connected to the contact point B and the first end of the current-limiting resistor R9, and the second end is connected to the second grounding end GAND2 and the first end of the current-limiting resistor R11; the first end of the sampling resistor R14 is connected to the second end of the current-limiting resistor R9 and the non-inverting input terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the current-limiting resistor R11 and the inverting input terminal of the isolation operational amplifier differential module U6; the filter capacitor C6 is connected in parallel with the sampling resistor R14; the first end of the current-limiting resistor R10 is connected to the positive differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the first end of the filter capacitor C7 and the positive input terminal of the first analog-to-digital conversion module ADC2; the first end of the current-limiting resistor R12 is connected to the negative differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the filter capacitor C7 and the negative input terminal of the second analog-to-digital conversion module ADC2;

[0039] The first input terminal of the isolated DC-DC power supply module U7 is connected to the internal power supply VCC1, the second input terminal is connected to the first grounding end GND1, the first output terminal is connected to the contact point B, and the second output terminal is connected to the second grounding end GND2.

[0040] Further, the FPGA module U1 includes an FPGA processing unit, a PI input pin, a PO output pin, and a grounding pin GND. The grounding pin GND of the FPGA module U1 is connected to the first grounding end GND1. The FPGA processing unit is configured to process the digital quantity of the voltage at the contact point A to obtain a first judgment result on whether the external relay is turned on.

[0041] Further, there are at least one or more empty pins between the PI and PO pins of the FPGA module U1.

[0042] Further, the ARM module U2 includes an ARM processing unit, a first analog-to-digital conversion module ADC1, a second analog-to-digital conversion module ADC2, a power input pin VCC, and a grounding pin GND. The power input pin VCC is connected to the internal power supply VCC1. The grounding pin GND of the ARM module U2 is connected to the first grounding end GND1; the ARM unit is configured to process the analog quantity of the voltage at the contact point A to obtain a second judgment result on whether the external relay is turned on. If the second judgment result is consistent with the first judgment result, the first judgment result or the second judgment result is output; the ARM unit is further configured to judge whether the power supply is abnormal according to the analog quantity of the voltage at the contact point B. If it is abnormal, the power supply and the power supply monitoring module are controlled to give an alarm.

[0043] Further, there are at least one or more empty pins between the first analog-to-digital conversion module ADC1 and the second analog-to-digital conversion module ADC2 of the ARM module U2.

[0044] When the circuit according to the embodiment of the present invention is actually used, contact point A and contact point B are connected through an external relay contact. When the external relay contact is closed, contact point A and contact point B are conducting. When the external relay is disconnected, contact point A and contact point B are disconnected.

[0045] For the main chips of existing high-end control switch input circuits, especially in relay protection, measurement and control devices, and safety products, ARM chips are often used, plus an FPGA chip, or an SOC chip integrating FPGA and ARM. Therefore, in view of this scenario, the embodiment of the present invention utilizes the characteristics of FPGA and ARM to separately process the signals collected at the front end. Without increasing the cost of the main chip, different characteristics of the main chip are used to achieve a more reliable combined function. Taking U1 as an FPGA chip and U2 as an ARM chip in the CPU calculation module as an example, a conventional ARM chip internally includes an on-chip ADC. When the accuracy requirement is not very strict, the on-chip ADC can be used for voltage acquisition. The FPGA of U1 is good at digital input and output. The PI and PO in U1, as digital pulse output and input, occupy very little FPGA resources. Therefore, the embodiment of the present invention utilizes the conventional multi-core heterogeneous form of existing high-level controllers, occupies less CPU resources, and realizes the CPU reading and calculation of two principles.

[0046] Please refer to Figure 1 , the working principle of the embodiment of the present invention is as follows:

[0047] The switch input circuit of this embodiment is isolated externally. It is optically isolated through optocouplers U3 and U4, and isolated op amps U5 and U6 are isolated externally. U7 is an isolated power supply. Then the entire circuit completely isolates the external switch input circuit from the internal switch input circuit, reducing the possibility of external interference with the internal calculation module. The switch input circuit internally uses VCC1 and GND1 for power supply, and the external of the switch input circuit uses VCC2 and GND2 isolated by U7 for power supply.

[0048] The VCC2 output by U7 is connected to contact point B. When contact point B and contact point A are conducting through an external contact, contact point A connects VCC2 to GND2 through the R1, U3, U4, R3 loop. The primary side of the optocoupler connected by U3 and the secondary side of the optocoupler connected by U4. Then if the secondary side of U4 is conducting, the entire loop is conducting, and the secondary side of U3 will be conducting. The PI of U1 will be connected to GND1, which is digital 0. If the secondary side of U4 is not conducting, no current will pass through the primary side of U3, the secondary side of U3 is disconnected, and then through the pull-up resistor R2, the PO collects the VCC1 voltage, which is digital 1. When the PO of U1 outputs a high level 1, the primary side of U4 is conducting, and the secondary side is conducting. When the PO of U1 outputs a low level 0, the primary side of U4 is not conducting, and the secondary side is not conducting.

[0049] Therefore, when the external contacts A and B are conducting, the digital quantity acquisition module combines with U1 in the CPU calculation module. U1 can control the output of PO, conduct the secondary side of U4 in the digital quantity acquisition module, and then read it back through PI. When PO outputs 1, PI reads back 0; when PO outputs 0, PI reads back 1. When the external contacts A and B are not conducting, contact A has no power supply and is in a floating state. The circuit formed by the primary side of U3, the secondary side of U4, resistor R1, and resistor R3 cannot conduct. No matter whether PO outputs 0 or 1, the secondary side of U3 does not conduct, and PI collects the high level 1 through the pull-up resistor R2.

[0050] PO of U1 continuously outputs a pulse with an encoded 0 or 1 in a loop. For example, 111001001. If PI reads 000110110, which is exactly the bitwise inverse of the PO output code, it proves that contacts AB are conducting and there is an external input. If PI always receives the high level 1, it proves that contacts AB are not conducting and there is no external input.

[0051] Therefore, the digital quantity acquisition module and U1 can judge whether the external relay contacts are conducting through encoded output and input. The pulse output frequency needs to avoid the common interference frequency bands in the application scenario. For example, when applied in the power distribution industry, it is necessary to avoid 50Hz and its high-order harmonic frequencies. Further, its output frequency can use a variable frequency to improve reliability and reduce the possibility of being interfered.

[0052] When contacts A and B are externally conducting, VCC2 forms a conducting loop with GND2 through R5, R13, and R7. At this time, the primary side of the isolation op-amp U5 collects the voltage across R13. The secondary side of U5 will also output according to the voltage situation of the primary side in a specific ratio and output it to the on-chip ADC1 of U2. Through ADC1, a voltage value is collected. Its sampling voltage is VCC2*R13 / (R5 + R13 + R7). This voltage should meet the linear input amplification range of the isolation op-amp. The collected analog quantity needs to be converted into a digital quantity to judge whether contacts AB are conducting externally. Considering the reliability of the sampled switch input circuit, two voltage threshold ranges are selected and represented by V1 and V0.

[0053] V1 = 70% * VCC2 * R13 * U5 turns ratio / (R5 + R13 + R7);

[0054] V0 = 30% * VCC2 * R13 * U6 turns ratio / (R5 + R13 + R7);

[0055] That is, after U2 collects the voltage value, it is compared with V1 and V0. If the voltage value collected by ADC1 of U2 is greater than V1, it is considered as digital quantity 1. If the voltage collected by ADC1 of U2 is less than V0, it is considered as digital quantity 0. If the collected voltage is between V0 and V1, it is considered that the sampling is abnormal, an alarm is given and the person is notified to conduct a check. This processing method actually takes into account the influence of the connection of the external loop, external impedance and external interference, and reserves a 30% rated voltage influence range, which corresponds to the 30% and 70% thresholds of VCC2. Therefore, U2 of the analog quantity acquisition module and the CPU calculation module can be converted into digital quantity acquisition through a specific algorithm using the principle of analog quantity acquisition, while taking into account the influence of interference.

[0056] In the power supply and power supply monitoring module, the voltage acquisition loop of the isolation operational amplifier of U6 is basically the same as the principle of the analog quantity acquisition module, except that the voltage acquisition point is VCC2 output by U7, mainly monitoring the voltage condition of VCC2. Because, no matter how perfect the acquisition loops of connection points A and B are, if VCC2 has an abnormality, misjudgment will occur in the acquisition of the relay contacts of the external loop. And VCC2 is isolated to the outside of the switch quantity input circuit. If there is an abnormality outside the switch quantity input circuit, it may damage the power supply of VCC2. Therefore, in order to ensure the reliability of the switch quantity input circuit, the power supply after the isolation of U7 is monitored. When it is found that VCC2 is abnormal, an alarm is given in time to prevent misjudgment caused by power supply problems.

[0057] In the CPU calculation module, the FPGA chip of U1 and the ARM chip of U2 are used to form a heterogeneous logic judgment architecture through two different processing cores. The heterogeneous architecture can prevent the risk of common misjudgment. At the same time, U1 and U2 can exchange information through the communication bus. U2 obtains the judgment result of U1 in real time through communication and compares the judgment results of U1 and U2. If the judgment results are consistent, it is normal. If the judgment results are inconsistent for a period of time, an abnormal alarm is given to introduce human intervention.

[0058] The following explains the judgment method of the entire switch quantity input circuit from the working angles of U1 and U2 of the entire switch quantity input circuit:

[0059] The PO pin of U1 cyclically sends a pulse quantity with a specific frequency or variable frequency encoded (for example, 111001001), and at the same time reads the input quantity of PI. If PI finds that the high level 1 lasts for a period of time, it is considered that the input between contacts AB is 0 (that is, the external relay contact is disconnected); if PI finds that the pulse quantity obtained by reading is the bitwise inverse of the encoding (for example, 000110110), it is considered that the input between contacts AB is 1 (that is, the external relay contact is closed). At the same time, U1 sends its own judgment result to U2 through communication.

[0060] The ADC1 of U2 has been continuously judging the voltage. When the collected voltage is less than a certain value V0, it is considered that the input between contacts AB is 0 (i.e., the external relay contact is disconnected); when it is found that the collected voltage is greater than a certain value V1, it is considered that the input between contacts AB is 1 (i.e., the external relay contact is closed). At the same time, U2 has been reading the judgment status of U1 through communication and comparing it with its own judgment status. When U1 finds that there is a long difference from the judgment of U2, it sends an alarm message. If it is found that the judgments of U1 and U2 are consistent, it is considered a reliable judgment.

[0061] Based on the above description, it can be seen that the digital input circuit of the embodiment of the present invention has the following advantages:

[0062] (1) In terms of the judgment method: Two different sampling circuits are used, two different CPU judgment methods are used, and they are compared to judge the correctness of the input; Two sets of solutions are used to avoid misjudgment caused by external environmental interference; The pulse input / output coding method can effectively reduce short-term interference;

[0063] (2) Spatial isolation: Between PI and PO, between ADC1 and ACD2, in the circuit design, a certain distance is maintained to prevent IO short circuit and thus misjudgment when welding or foreign object contamination occurs; Isolation design is used in the circuit, and both the power supply and the signal meet the isolation requirements, preventing external interference from entering the CPU logic judgment and ensuring safety at the same time.

[0064] The embodiments of the present invention have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the disclosed embodiments.

Claims

1. A digital input circuit, characterized in that, Comprising: A digital quantity acquisition module, configured to acquire the digital quantity of the voltage of contact point A and transmit it to the FPGA module of the CPU calculation module; An analog quantity acquisition module, configured to acquire the analog quantity of the voltage of contact point A and transmit it to the ARM module of the CPU calculation module; A power supply and power supply monitoring module, configured to connect to contact point B, isolate and output the internal power supply to contact point B, and at the same time acquire the analog quantity of the voltage of contact point B and transmit it to the ARM module of the CPU calculation module; wherein, contact point A and contact point B are connected through an external relay; The CPU calculation module includes an FPGA module and an ARM module. The FPGA module is configured to process the digital quantity of the voltage to obtain a first judgment result on whether the external relay is turned on. The ARM module is configured to process the analog quantity of the voltage to obtain a second judgment result on whether the external relay is turned on. If the second judgment result is consistent with the first judgment result, the first judgment result or the second judgment result is output; the ARM module is further configured to judge whether the power supply is abnormal according to the analog quantity of the voltage of contact point B. If it is abnormal, the power supply and power supply monitoring module is controlled to give an alarm.

2. The digital input circuit according to claim 1, wherein The digital quantity acquisition module includes: The first end of protection device D1 is connected to contact point A, and the second end is connected to the second grounding end GAND2; the first end of current-limiting resistor R1 is connected to the first end of protection device D1, and the second end is connected to the primary side of optocoupler U3; the first end of current-limiting resistor R3 is connected to the second end of protection device D1, and the second end is connected to the secondary side of optocoupler U4; the first end of filter capacitor C1 is connected to the second end of current-limiting resistor R1, and the second end is connected to the second end of current-limiting resistor R3; the first end of pull-up resistor R2 is connected to the power input VCC1, and the second end is connected to the secondary side of optocoupler U3; the secondary side of optocoupler U3 is also connected to the first grounding end GAND1; the first end of current-limiting resistor R4 is connected to the primary side of optocoupler U4, and the second end is connected to the PO output pin of the FPGA module; the primary side of optocoupler U4 is also connected to the first grounding end GAND1; the first end of the filter capacitor is connected to the secondary side of optocoupler U3 and the PI output end of the FPGA module, and the second end is connected to the first grounding end GAND1.

3. The digital input circuit according to claim 2, wherein The analog quantity acquisition module includes: The first end of protection device D2 is connected to contact point A and the first end of current-limiting resistor R5, and the second end is connected to the second grounding end GAND2 and the first end of current-limiting resistor R7; the first end of sampling resistor R13 is connected to the second end of current-limiting resistor R5 and the non-inverting input terminal of isolation operational amplifier differential module U5, and the second end is connected to the second end of current-limiting resistor R7 and the inverting input terminal of isolation operational amplifier differential module U5; filter capacitor C4 is connected in parallel with sampling resistor R13; the first end of current-limiting resistor R6 is connected to the positive differential signal output terminal of isolation operational amplifier differential module U5, and the second end is connected to the first end of filter capacitor C5 and the positive input terminal of the first analog-to-digital conversion module ADC1; the first end of current-limiting resistor R8 is connected to the negative differential signal output terminal of isolation operational amplifier differential module U5, and the second end is connected to the second end of filter capacitor C5 and the negative input terminal of the first analog-to-digital conversion module ADC1.

4. The digital input circuit according to claim 3, wherein The power supply and power supply monitoring module includes: The first end of the protection device D3 is connected to the contact point B and the first end of the current-limiting resistor R9, and the second end is connected to the second ground terminal GAND2 and the first end of the current-limiting resistor R11; the first end of the sampling resistor R14 is connected to the second end of the current-limiting resistor R9 and the non-inverting input terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the current-limiting resistor R11 and the inverting input terminal of the isolation operational amplifier differential module U6; the filter capacitor C6 is connected in parallel with the sampling resistor R14; the first end of the current-limiting resistor R10 is connected to the positive differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the first end of the filter capacitor C7 and the positive input terminal of the first analog-to-digital conversion module ADC2; the first end of the current-limiting resistor R12 is connected to the negative differential signal output terminal of the isolation operational amplifier differential module U6, and the second end is connected to the second end of the filter capacitor C7 and the negative input terminal of the second analog-to-digital conversion module ADC2; The first input terminal of the isolated DC-DC power module U7 is connected to the internal power supply VCC1, the second input terminal is connected to the first ground terminal GND1, the first output terminal is connected to the contact point B, and the second output terminal is connected to the second ground terminal GND2.

5. The digital input circuit according to claim 4, wherein The FPGA module includes an FPGA processing unit, a PI input pin, a PO output pin, and a ground pin GND. The ground pin GND of the FPGA module is connected to the first ground terminal GND1.

6. The digital input circuit according to claim 5, wherein There are at least one or more empty pins between the PI and PO pins of the FPGA module.

7. The digital input circuit according to claim 5, wherein The ARM module includes an ARM processing unit, a first analog-to-digital conversion module ADC1, a second analog-to-digital conversion module ADC2, a power input pin VCC, and a ground pin GND. The power input pin VCC is connected to the internal power supply VCC1. The ground pin GND of the ARM module is connected to the first ground terminal GND1.

8. The digital input circuit according to claim 7, wherein There are at least one or more empty pins between the first analog-to-digital conversion module ADC1 and the second analog-to-digital conversion module ADC2 of the ARM module.

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