Clock circuit and clock circuit synchronization method

Abstract

The invention relates to the technical field of integrated circuits, in particular to a clock circuit and a clock circuit synchronization method, and the clock circuit comprises a synchronization pulse generation module which generates a synchronization pulse signal based on an accessed main clock signal; the target frequency dividers are in one-to-one correspondence with the channels in the clock circuit, the target frequency dividers are connected with the synchronous pulse signals, and frequency divider resetting is carried out based on the synchronous pulse signals; the clock delay module is used for carrying out delay transmission on the accessed main clock signal, the delay duration is greater than or equal to the reset duration of the target frequency divider, and the delayed clock signal is transmitted to the target frequency divider so as to carry out clock reset and synchronization; the clock circuit can well ensure that the frequency divider resetting process and the clock resetting process can be independently carried out, so that the situation that in the clock resetting process, the target frequency divider is still in the frequency divider resetting stage, frequency divider resetting fails, and phases of output signals of multiple channels in the clock circuit are inconsistent is avoided.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a clock circuit and a clock circuit synchronization method. Background Art

[0002] In a multi-channel transceiver system, a clock circuit (high-speed clock distribution circuit) is an essential part, and its synchronization performance directly affects the transmission quality of signals. The synchronization function principle of a common clock circuit is to generate a synchronization pulse signal, reset the frequency dividers in all channels, and force the clock outputs of each channel to align, thereby achieving the frequency and phase synchronization of multi-channel clock signals. To ensure the reliability of synchronization, the synchronization pulse signal needs to remain stable within the setup time (the shortest time for the synchronization pulse signal to remain stable before the clock edge arrives) and hold time (the shortest time for the synchronization pulse signal to remain stable after the clock edge arrives) of the clock signal, to avoid the occurrence of metastability.

[0003] However, when the frequency of the clock signal is increased to the GHz level, the clock period is shortened to the ps (picosecond) level. At this time, the clock transition speed (the switching speed of the clock signal level) increases sharply, while the synchronization pulse signal speed (the frequency or edge speed of the synchronization pulse signal) is slow and cannot match the conversion rate of the high-speed clock. This mismatch increases the likelihood of metastability. Especially in a multi-channel transceiver system, due to the different propagation paths of the synchronization pulse signals in different channels, the signal propagation delays will also be different, further increasing the risk of metastability. This may lead to the failure of multi-channel transceiver system synchronization, affecting the normal operation of the clock circuit, and further affecting the stability of the entire communication system. Summary of the Invention

[0004] The present invention provides a clock circuit and a clock circuit synchronization method to solve the problem in the prior art that when the frequency of the clock signal is relatively high, the clock transition speed does not match the synchronization pulse signal speed, resulting in the clock signal in the frequency divider entering the metastable state and affecting the normal operation of the clock circuit.

[0005] A clock circuit provided by the present invention includes: a synchronization pulse generation module, which generates a synchronization pulse signal based on the accessed master clock signal;

[0006] At least one target frequency divider, which corresponds to the channels in the clock circuit one by one, and the target frequency divider accesses the synchronization pulse signal and performs frequency divider reset based on the synchronization pulse signal;

[0007] A clock delay module, which delays the transmission of the accessed master clock signal, the delay duration is greater than or equal to the reset duration of the target frequency divider, and transmits the delayed clock signal to the target frequency divider for clock reset and synchronization.

[0008] In some embodiments of the present invention, the synchronization pulse generation module includes:

[0009] A first frequency divider, which divides the input main clock signal to obtain a divided clock signal;

[0010] A pulse generation circuit, which generates the synchronization pulse signal based on the divided clock signal, and the pulse width of the synchronization pulse signal is consistent with the clock period of the divided clock signal.

[0011] In some embodiments of the present invention, the clock delay module includes:

[0012] A second frequency divider, which accesses the synchronization pulse signal, divides the synchronization pulse signal to obtain a first pulse signal, and the pulse width of the first pulse signal is greater than the pulse width of the synchronization pulse signal;

[0013] A flip-flop, which accesses the first pulse signal and the main clock signal, latches the first pulse signal based on the rising edge of the main clock signal to obtain a second pulse signal, and outputs the second pulse signal when detecting the rising edge of the main clock signal;

[0014] A buffer, which accesses the main clock signal and delays the main clock signal to obtain a clock delay signal;

[0015] [[ID=2)3]]At least one AND logic unit, which corresponds to each channel in the clock circuit one by one. The AND logic unit accesses the clock delay signal and the inverted second pulse signal, and outputs a target clock signal after performing an AND operation. The target clock signal is the delayed clock signal.

[0016] In some embodiments of the present invention, the signal period of the first pulse signal is greater than or equal to the signal period of the clock delay signal.

[0017] In some embodiments of the present invention, the division ratio coefficient of the second frequency divider is the same as the magnification factor of the buffer for the signal period of the main clock signal.

[0018] In some embodiments of the present invention, the reset terminal of the target frequency divider accesses the synchronization pulse signal, and the data terminal of the target frequency divider accesses the delayed clock signal.

[0019] In some embodiments of the present invention, the output terminal of the target frequency divider is the output terminal of the corresponding channel in the clock circuit

[0020] The present invention also provides a synchronization method for a clock circuit as described in any one of the above, and the method includes:

[0021] Based on the master clock signal, synchronizing pulse generation is performed to obtain the synchronization pulse signal;

[0022] The synchronization pulse signal is respectively transmitted to the target frequency dividers in each channel of the clock circuit to instruct the target frequency dividers to perform frequency divider reset;

[0023] The master clock signal is delayed and transmitted, the delay duration is greater than or equal to the reset duration of the target frequency divider, and the delayed clock signal is transmitted to the target frequency divider to instruct the target frequency divider to perform clock reset and synchronization.

[0024] In some embodiments of the present invention, based on the master clock signal, synchronizing pulse generation is performed to obtain the synchronization pulse signal, including:

[0025] The master clock signal is frequency-divided to obtain a frequency-divided clock signal;

[0026] Based on the frequency-divided clock signal, synchronizing pulse generation is performed to obtain the synchronization pulse signal, and the pulse width of the synchronization pulse signal is consistent with the clock period of the frequency-divided clock signal.

[0027] In some embodiments of the present invention, the delaying and transmitting of the master clock signal includes:

[0028] The synchronization pulse signal is frequency-divided to obtain a first pulse signal, and the pulse width of the first pulse signal is greater than the pulse width of the synchronization pulse signal;

[0029] Based on the rising edge of the master clock signal, the first pulse signal is latched to obtain a second pulse signal;

[0030] When the rising edge of the master clock signal is detected, the second pulse signal is output;

[0031] The master clock signal is clock-delayed to obtain a clock-delayed signal;

[0032] By performing an AND operation on the clock-delayed signal and the inverted second pulse signal, a target clock signal is obtained, and the target clock signal is the delayed clock signal.

[0033] Advantages of the present invention: The clock circuit and the clock circuit synchronization method provided by the present invention. The clock circuit generates a synchronization pulse signal based on the accessed master clock signal by setting a synchronization pulse generation module; at least one target frequency divider, which corresponds to each channel in the clock circuit one by one. The target frequency divider accesses the synchronization pulse signal and resets the frequency divider based on the synchronization pulse signal; a clock delay module, which delays and transmits the accessed master clock signal, and the delay duration is greater than or equal to the reset duration of the target frequency divider, and transmits the delayed clock signal to the target frequency divider for clock reset and synchronization. The clock circuit can preferably ensure that when the frequency of the master clock signal is relatively high, the frequency divider reset process and the clock reset process in the target frequency divider can be independently performed, that is, the reset of the target frequency divider is completed first, and then the clock reset is performed, so as to avoid the situation that the target frequency divider is still in the frequency divider reset stage during the clock reset process, resulting in the failure of the frequency divider reset and further causing the phase inconsistency of the output signals of multiple channels in the clock circuit. Description of the Drawings

[0034] Figure 1 FIG. 6 is a schematic structural diagram of a clock circuit in the prior art provided by an embodiment of the present invention;

[0035] Figure 2 FIG. 10 is a schematic structural diagram of a clock circuit provided by an embodiment of the present invention;

[0036] Figure 3 FIG. 14 is a timing diagram of generating a second pulse signal in a clock circuit provided by an embodiment of the present invention;

[0037] Figure 4 FIG. 18 is a timing diagram of generating a final clock signal in a clock circuit provided by an embodiment of the present invention;

[0038] Figure 5 FIG. 22 is a schematic flowchart of a clock circuit synchronization method provided by an embodiment of the present invention. Detailed Embodiments

[0039] The following specifically illustrates the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0040] It should be noted that the illustrations provided in the following embodiments only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0041] In the following description, numerous details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0042] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the structure of a clock circuit in the prior art provided for an embodiment of the present invention. As Figure 1 shown, the clock circuit includes multiple channels, such as Channel 1, Channel 2... Channel N - 1, and Channel N, etc. Among them, N represents the number of channels. A frequency divider is provided in each channel. The D terminal of the frequency divider represents its data terminal, the RESET terminal represents its reset terminal, and the Q terminal represents its output terminal. The reset terminal RESET of each frequency divider is connected to the synchronization pulse signal generated by the synchronization pulse generation circuit for frequency divider reset, so as to ensure the phase consistency of the signals in each channel and achieve phase synchronization. The data terminal D of each frequency divider is connected to the main clock signal CLKIN to divide and reset the main clock signal, so as to ensure the frequency consistency of the signals in each channel and achieve frequency synchronization. Figure 1CLKOUT1, CLKOUT2......CLKOUT(N - 1), and CLKOUTN in it represent the synchronized clock signals output by each channel. To ensure the reliability of synchronization, the synchronization pulse signal needs to remain stable within the setup time of the clock signal (the shortest time for the synchronization pulse signal to remain stable before the arrival of the clock edge (such as the rising edge)) and the hold time (the shortest time for the synchronization pulse signal to remain stable after the arrival of the clock edge), to avoid the occurrence of metastability. However, when the above clock circuit faces a high-frequency master clock signal, such as a signal with a frequency above GHz, it is very easy to generate a metastable state, resulting in the failure of the multi-channel synchronization function of the clock circuit. It can be understood that the synchronization pulse signal is usually generated by a digital CMOS (Complementary Metal-Oxide-Semiconductor) module, and the pulse signal speed is slow. When the signal frequency of the master clock signal reaches above GHz, it is easy for the rising edge of the master clock to reach the frequency divider while the frequency divider is still in the frequency divider reset state, that is, the frequency divider reset is not completed. At this time, if the frequency divider performs a clock reset, it may cause problems with the phase of the finally output signal, that is, the phases of the signals output by multiple channels are inconsistent, resulting in abnormal multi-channel clock synchronization function of the clock circuit, which has an adverse impact on the stability and reliability of the entire communication system. To solve this problem, the present invention provides a clock circuit and a clock circuit synchronization method, by setting a synchronization pulse generation module, a clock delay module, and at least one target frequency divider in the clock circuit, to better ensure that in the case of a relatively high frequency of the master clock signal, the frequency divider reset process and the clock reset process in the target frequency divider can be carried out independently without interference, avoiding the failure of the frequency divider reset, and effectively improving the stability and reliability of the clock circuit.

[0043] The following combines Figures 2 to 5 to explain the clock circuit and the clock circuit synchronization method provided by the present invention.

[0044] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the clock circuit provided by an embodiment of the present invention. As Figure 2 shown, the clock circuit includes:

[0045] A synchronization pulse generation module 210, which generates a synchronization pulse signal SYNC_Pluse based on the accessed master clock signal CLKIN;

[0046] Target frequency dividers 220, which correspond to the channels in the clock circuit one by one. The target frequency dividers access the synchronization pulse signal SYNC_Pluse and perform frequency divider reset based on the synchronization pulse signal SYNC_Pluse;

[0047] A clock delay module 230 delays and transmits the input main clock signal CLKIN, and the delay duration is greater than or equal to the reset duration of the target frequency divider, and transmits the delayed clock signals (such as Figure 2 CLK_INT1, CLK_INT2......CLK_INT(N - 1), and CLK_INTN in it) to the target frequency divider for clock reset and synchronization.

[0048] It can be understood that the reset duration of the target frequency divider can be set according to the actual situation. By setting the above clock delay module, it can better ensure that when the frequency of the main clock signal CLKIN is relatively high, the frequency divider reset process and the clock reset process in the target frequency divider can be independent or sequential, without interference, so as to avoid the situation that the target frequency divider is still in the frequency divider reset stage during the clock reset process. In this way, the multi-channel clock synchronization accuracy and stability of the clock circuit can be effectively improved, with low cost and convenient implementation.

[0049] In some examples of this embodiment, each channel in the clock circuit is provided with a target frequency divider, and the target frequency divider can be an M-bit frequency divider, etc., where M is the number of bits of the target frequency divider, such as Figure 1 target frequency divider 1, target frequency divider 2......target frequency divider N - 1, and target frequency divider N in it. The frequency division coefficient of the M-bit frequency divider can be 1 to 2 M -1, and the frequency division coefficients of the M-bit frequency dividers in each channel can be independently adjusted, with high flexibility. By adjusting the frequency division coefficients of the M-bit frequency dividers in each channel, the output frequency of the M-bit frequency divider can be adjusted to meet different actual usage requirements.

[0050] It can be understood that Figure 2 CLKOUT1, CLKOUT2......CLKOUT(N - 1), and CLKOUTN in it represent the final clock signals output by each target frequency divider.

[0051] In some embodiments, the synchronization pulse generation module includes:

[0052] A first frequency divider that divides the input main clock signal CLKIN to obtain a divided clock signal;

[0053] A pulse generation circuit that generates the synchronization pulse signal SYNC_Pluse based on the divided clock signal, and the pulse width of the synchronization pulse signal SYNC_Pluse is consistent with the clock period of the divided clock signal.

[0054] In some embodiments of this embodiment, the first frequency divider may be an S-bit frequency divider. S represents the number of bits of the first frequency divider. The frequency division coefficient of the first frequency divider is adjustable. Assume that the S-bit frequency divider divides the input main clock signal CLKIN, and the clock period of the obtained divided clock signal is (1 to 2 S -1)T clk , where T clk is the clock period of the main clock signal CLKIN. It can be understood that by dividing the main clock signal CLKIN to obtain a divided clock signal and generating a synchronous pulse signal SYNC_Pluse based on the divided clock signal, the frequency of the synchronous pulse signal SYNC_Pluse can be effectively reduced, which helps to ensure that the frequency divider reset process and the clock reset process of the target frequency divider are carried out sequentially according to the clock.

[0055] In some examples of this embodiment, the synchronous pulse generation module further has a pulse width control port and a pulse generation control port. The pulse width control port is used to control the frequency division coefficient of the first frequency divider, and the pulse generation control port is used to control the generation of the synchronous pulse signal SYNC_Pluse. The pulse generation control port receives a pulse generation signal, and the pulse width control port receives a pulse width control signal. Based on the pulse generation signal and the pulse width control signal, the synchronous pulse signal SYNC_Pluse is generated. It can be understood that when the level of the pulse generation signal changes from low to high and then to low, the pulse generation circuit is triggered, thereby outputting the synchronous pulse signal SYNC_Pluse.

[0056] In some embodiments, the pulse width of the synchronous pulse signal SYNC_Pluse is the same as the clock period of the main clock signal CLKIN. In actual implementation, the pulse width of the synchronous pulse signal SYNC_Pluse can be adjusted according to actual needs, so as to adjust the signal delay time required in the clock synchronization process.

[0057] In some embodiments, the clock delay module includes:

[0058] A second frequency divider, which accesses the synchronous pulse signal SYNC_Pluse, divides the synchronous pulse signal SYNC_Pluse, and obtains a first pulse signal SYNC_Div2. The pulse width of the first pulse signal SYNC_Div2 is greater than the pulse width of the synchronous pulse signal SYNC_Pluse;

[0059] A trigger, which is connected to the first pulse signal SYNC_Div2 and the main clock signal CLKIN, latches the first pulse signal SYNC_Div2 based on the rising edge of the main clock signal CLKIN to obtain a second pulse signal SYNC_Timing, and outputs the second pulse signal SYNC_Timing when the rising edge of the main clock signal CLKIN is detected;

[0060] A buffer (BUFFER), which is connected to the main clock signal CLKIN, delays the main clock signal CLKIN to obtain a clock delay signal;

[0061] At least one AND logic unit, which corresponds to each channel in the clock circuit one by one. The AND logic unit is connected to the clock delay signal and the inverted second pulse signal SYNC_Timing. After performing an AND operation, it outputs a target clock signal (such as Figure 2 CLK_INT1, CLK_INT2......CLK_INT(N - 1), and CLK_INTN in), and the target clock signal is the delayed clock signal.

[0062] In some examples of this embodiment, the second frequency divider can be a ÷2 frequency divider (a binary frequency divider). The input end of the second frequency divider is connected to the output end of the pulse generation circuit, divides the synchronous pulse signal SYNC_Pluse output by the pulse generation circuit by two, and outputs the first pulse signal SYNC_Div2.

[0063] In some examples of this embodiment, when the rising edge of the main clock signal CLKIN is updated, the trigger resamples and latches the level of the first pulse signal SYNC_Div2. Moreover, the rising edge of the main clock signal CLKIN determines the flip edge of the first pulse signal SYNC_Div2, thereby outputting the second pulse signal SYNC_Timing. In this way, the asynchronous first pulse signal SYNC_Div2 can be converted into the synchronous second pulse signal SYNC_Timing. Figure 2 The D terminal of the trigger in is its data terminal, the CLK terminal is its main clock signal input terminal, and the Q terminal is its output terminal.

[0064] In some examples of this embodiment, the delay time of the buffer for the main clock signal CLKIN is fixed and can be 1 / 2T clkmax etc., T clkmax represents the maximum clock period of the main clock signal CLKIN.

[0065] In some examples of this embodiment, if the level of the second pulse signal SYNC_Timing is high, it indicates that the target frequency divider is performing frequency divider reset; if the level of the second pulse signal SYNC_Timing is low, it indicates that the target frequency divider has completed the frequency divider reset and can perform clock reset. Therefore, by inputting the clock delay signal and the inverted second pulse signal SYNC_Timing into the AND logic unit, it can be ensured that when the clock delay signal is high and the target frequency divider has completed the frequency divider reset (the second pulse signal SYNC_Timing is low), the target clock signal is output to instruct the target frequency divider to perform clock reset. It can be understood that the AND logic unit will generate an output signal only when both input signals are high.

[0066] In some examples of this embodiment, if the delay time of the buffer for the main clock signal CLKIN is 1 / 2T clkmax , then compared with the second pulse signal SYNC_Timing (synchronized with the flip edge of the main clock signal) output by the flip-flop, the flip edge of the clock delay signal output by the buffer differs by 1 / 2T clkmax . In this way, it can avoid the two timings from entering the metastable state, thereby ensuring the accuracy and stability of multi-channel clock synchronization.

[0067] In some examples of this embodiment, the flip-flop can be a high-speed D flip-flop (High-Speed D Flip-Flop, a digital circuit element used for high-frequency clock signal processing). The edge flip speed of the high-speed D flip-flop is relatively fast. By setting the flip-flop as a high-speed D flip-flop, it can better complete the conversion from the first pulse signal SYNC_Div2 (a low-speed digital signal with a slow flip edge speed) to the second pulse signal SYNC_Timing (a high-speed analog signal with a high-speed flip edge). Through the above settings, it can avoid the clock edge from entering the metastable state during clock synchronization.

[0068] It can be understood that in the case where the second frequency divider is a ÷2 frequency divider, the ÷2 frequency divider doubles the pulse width of the input synchronization pulse signal SYNC_Pluse, that is, the first pulse signal SYNC_Div2 is twice the synchronization pulse signal SYNC_Pluse. Through this setting, it can fully meet the requirements of synchronizing the target frequency dividers in multiple channels. Moreover, through this setting, it can better ensure that in the synchronization timing of the clock circuit, the target frequency divider will first complete the frequency divider reset and then complete the reset of the input target clock signal. In this way, it can avoid the situation where the frequency divider is in progress or has not completed the frequency divider reset while the target frequency divider is performing clock reset, resulting in the failure of the frequency divider reset and further causing the phase inconsistency of the final clock signals output by multiple channels.

[0069] Figure 2 AND2_1, AND2_2......AND2_N - 1, and AND2_N in it are the AND gate logic units of each channel.

[0070] In the above - mentioned embodiment, when the level of the synchronous pulse signal SYNC_Pluse is high, the target frequency divider starts to reset the frequency divider, that is, the target frequency dividers in each channel are all cleared in state, and the division coefficient is reset to 1. When the level of the synchronous pulse signal SYNC_Pluse becomes low, the process of clearing the state of the target frequency divider ends, and then the clock is reset.

[0071] It should be mentioned that the clock circuit in the above - mentioned embodiment can adopt a differential structure design. The fully differential circuit can suppress the common - mode mismatch in the circuit, reduce non - linearity and noise.

[0072] In some embodiments, the signal period of the first pulse signal SYNC_Div2 is greater than or equal to the signal period of the clock delay signal.

[0073] It can be understood that through the above settings, it is helpful to ensure that the frequency - divider reset and clock reset of the target frequency divider are carried out in sequence.

[0074] In some embodiments, the division coefficient of the second frequency divider is the same as the magnification factor of the buffer for the signal period of the main clock signal CLKIN.

[0075] It should be noted that through the above settings, it is helpful to improve the accuracy of clock synchronization and is also helpful to improve the performance of the clock circuit.

[0076] In some embodiments, the reset terminal of the target frequency divider is connected to the synchronous pulse signal SYNC_Pluse, and the data terminal of the target frequency divider is connected to the delayed clock signal.

[0077] It should be noted that by connecting the synchronous pulse signal SYNC_Pluse to the reset terminal of the target frequency divider and connecting the delayed clock signal to the data terminal of the target frequency divider, it is helpful to ensure that the frequency - divider reset and clock reset of the target frequency divider are carried out in sequence.

[0078] In some embodiments, the output terminal of the target frequency divider is the output terminal of the corresponding channel in the clock circuit. The final clock signal output by the target frequency divider is the output of the clock circuit.

[0079] Figure 3 For the timing diagram of generating the second pulse signal SYNC_Timing in the clock circuit provided by an embodiment of the present invention, please refer to Figure 3 ,Figure 3 Exemplary displays of the timing waveforms of the master clock signal CLKIN, the pulse generation signal SYNC_Generator, the synchronization pulse signal SYNC_Pluse, the first pulse signal SYNC_Div2, and the second pulse signal SYNC_Timing are provided. Assume that the division factor of the first frequency divider in the synchronization pulse generation module is 256, then the signal period t1 of the generated synchronization pulse signal SYNC_Pluse is t1 = 256T clk . After further division by a ÷2 frequency divider, the signal period of the output first pulse signal SYNC_Div2 is t2 = 512T clk . Subsequently, through a flip-flop, reshaping and triggering are performed again to obtain a second pulse signal SYNC_Timing with a faster edge. The signal period of the second pulse signal SYNC_Timing is the same as that of the first pulse signal SYNC_Div2

[0080] Figure 4 Please refer to the timing schematic diagram for generating the final clock signal in the clock circuit provided by an embodiment of the present invention Figure 4 , Figure 4 Exemplary displays of the timing waveforms of the master clock signal CLKIN, the synchronization pulse signal SYNC_Pluse, the second pulse signal SYNC_Timing, the clock delay signal, the target clock signal CLK_INT, and the final clock signal CLKOUT are provided. From Figure 4It can be seen that since the second pulse signal SYNC_Timing is generated after passing through a ÷2 frequency divider and a flip-flop, the rising edge of SYNC_Timing has a delay time td that is at least twice the clock period of the master clock signal CLKIN compared to the rising edge of the synchronization pulse signal SYNC_Pluse. Therefore, it can be better ensured that during the synchronization process of the target frequency divider, the target frequency divider can first perform the operations of frequency divider reset and synchronization based on the synchronization pulse signal SYNC_Pluse, clearing the states of the target frequency dividers in each channel, and then perform clock reset and synchronization. Additionally, since the ÷2 frequency divider doubles the pulse width of the synchronization pulse signal SYNC_Pluse, the delay time tm generated by the falling edge of the second pulse signal SYNC_Timing compared to the falling edge of the synchronization pulse signal SYNC_Pluse is tm = tp + td, where tp represents the pulse width of the second pulse signal SYNC_Timing. It can be understood that when the synchronization pulse signal SYNC_Pluse is generated, that is, after the rising edge of the synchronization pulse signal SYNC_Pluse flips, the target frequency dividers in each channel all enter the frequency divider reset state, and at this time the clock output of the target frequency divider always remains low. Subsequently, the second pulse signal SYNC_Timing is generated to realize delayed input of the clock signal. At this time, the target frequency divider is still in the frequency divider reset state, and the clock output always remains low. Then, the synchronization pulse signal SYNC_Pluse ends, that is, its falling edge flips, and the target frequency divider completes the frequency divider reset and clears its internal state. However, since there is still no clock input at this time, it remains in the frequency divider reset state. Finally, when the second pulse signal SYNC_Timing ends and its falling edge flips, the AND logic unit outputs the target clock signal, and the target frequency divider ends the frequency divider reset state. At this time, the phases in each channel are consistent, and then based on this target clock signal, clock reset and synchronization are performed to output the final clock signal.

[0081] In summary, the clock circuit in the above embodiments can better meet the requirements of high-speed clock circuit synchronization, effectively solve the problem that the clock signal in the frequency divider enters the metastable state, that is, the problem of inconsistent multi-channel phases, due to the mismatch between the clock conversion speed and the synchronization pulse signal speed. The structure is relatively simple, the implementation is more convenient, and the stability and reliability of clock circuit synchronization are better improved.

[0082] The clock circuit synchronization method provided by the present invention will be described below. The clock circuit synchronization method described below can be mutually corresponding and referred to with the clock circuit described above.

[0083] Please refer to Figure 5 , the clock circuit synchronization method provided in this embodiment includes:

[0084] S510: Generate a synchronization pulse based on the master clock signal CLKIN to obtain the synchronization pulse signal SYNC_Pluse.

[0085] S520: Transmit the synchronization pulse signal SYNC_Pluse to the target frequency divider in each channel of the clock circuit respectively to instruct the target frequency divider to perform frequency divider reset.

[0086] S530: Delay the transmission of the master clock signal CLKIN by a delay duration greater than or equal to the reset duration of the target frequency divider, and transmit the delayed clock signal to the target frequency divider to instruct the target frequency divider to perform clock reset and synchronization. The clock circuit synchronization method in this embodiment can achieve the technical effects achieved by the clock circuit in the above embodiment, which will not be elaborated here.

[0087] In some embodiments, generating a synchronization pulse based on the master clock signal CLKIN to obtain the synchronization pulse signal SYNC_Pluse includes:

[0088] 1. Divide the master clock signal CLKIN to obtain a divided clock signal. ]>

[0089] 2. Generate a synchronization pulse based on the divided clock signal to obtain the synchronization pulse signal SYNC_Pluse, and the pulse width of the synchronization pulse signal SYNC_Pluse is consistent with the clock period of the divided clock signal.

[0090] In some embodiments, delaying the transmission of the master clock signal CLKIN includes:

[0091] 1. Divide the synchronization pulse signal SYNC_Pluse to obtain a first pulse signal SYNC_Div2, and the pulse width of the first pulse signal SYNC_Div2 is greater than the pulse width of the synchronization pulse signal SYNC_Pluse.

[0092] 2. Latch the first pulse signal SYNC_Div2 based on the rising edge of the master clock signal CLKIN to obtain a second pulse signal SYNC_Timing.

[0093] 3. Output the second pulse signal SYNC_Timing when detecting the rising edge of the master clock signal CLKIN.

[0094] 4. Delay the master clock signal CLKIN to obtain a clock delay signal.

[0095] 5. By performing an AND operation on the clock delay signal and the inverted second pulse signal SYNC_Timing, a target clock signal is obtained, and the target clock signal is the delayed clock signal.

[0096] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A clock circuit, characterized in that, Including: A synchronization pulse generation module, which generates a synchronization pulse signal based on the accessed master clock signal; Target frequency dividers, each of which corresponds to a channel in the clock circuit. The target frequency dividers access the synchronization pulse signal and perform frequency divider reset based on the synchronization pulse signal; A clock delay module, which delays and transmits the accessed master clock signal. The delay duration is greater than or equal to the reset duration of the target frequency divider, and transmits the delayed clock signal to the target frequency divider for clock reset and synchronization.

2. The clock circuit according to claim 1, wherein The synchronization pulse generation module includes: A first frequency divider, which divides the accessed master clock signal to obtain a divided clock signal; A pulse generation circuit, which generates the synchronization pulse signal based on the divided clock signal. The pulse width of the synchronization pulse signal is consistent with the clock period of the divided clock signal.

3. The clock circuit according to claim 1, characterized in that, The clock delay module includes: A second frequency divider, which accesses the synchronization pulse signal, divides the synchronization pulse signal to obtain a first pulse signal. The pulse width of the first pulse signal is greater than the pulse width of the synchronization pulse signal; A flip-flop, which accesses the first pulse signal and the master clock signal, latches the first pulse signal based on the rising edge of the master clock signal to obtain a second pulse signal, and outputs the second pulse signal when detecting the rising edge of the master clock signal; A buffer, which accesses the master clock signal and delays the master clock signal to obtain a clock delay signal; At least one AND logic unit, each of which corresponds to a channel in the clock circuit. The AND logic unit accesses the clock delay signal and the inverted second pulse signal, and outputs a target clock signal after performing an AND operation. The target clock signal is the delayed clock signal.

4. The clock circuit according to claim 3, characterized in that, The signal period of the first pulse signal is greater than or equal to the signal period of the clock delay signal.

5. The clock circuit according to claim 3 or 4, characterized in that, The division coefficient of the second frequency divider is the same as the signal period magnification factor of the buffer for the master clock signal.

6. The clock circuit according to claim 1, characterized in that, The reset terminal of the target frequency divider accesses the synchronization pulse signal, and the data terminal of the target frequency divider accesses the delayed clock signal.

7. The clock circuit according to claim 1, wherein The output terminal of the target frequency divider is the output terminal of the corresponding channel in the clock circuit.

8. A synchronization method for a clock circuit according to any one of claims 1 to 7, characterized in that, Including: Based on the master clock signal, generate a synchronization pulse to obtain the synchronization pulse signal; Transmit the synchronization pulse signal to the target frequency dividers in each channel of the clock circuit respectively to instruct the target frequency dividers to perform frequency divider reset; Perform delayed transmission on the master clock signal. The delay duration is greater than or equal to the reset duration of the target frequency divider, and transmit the delayed clock signal to the target frequency divider to instruct the target frequency divider to perform clock reset and synchronization.

9. The synchronization method of the clock circuit according to claim 8, characterized in that, Based on the master clock signal, generate a synchronization pulse to obtain the synchronization pulse signal, including: Divide the master clock signal to obtain a divided clock signal; Based on the divided clock signal, generate a synchronization pulse to obtain the synchronization pulse signal. The pulse width of the synchronization pulse signal is consistent with the clock period of the divided clock signal.

10. The synchronization method of the clock circuit according to claim 8, characterized in that, Performing delayed transmission on the master clock signal, including: Dividing the synchronization pulse signal to obtain a first pulse signal, where the pulse width of the first pulse signal is greater than the pulse width of the synchronization pulse signal; Latching the first pulse signal based on the rising edge of the master clock signal to obtain a second pulse signal; Outputting the second pulse signal when the rising edge of the master clock signal is detected; Performing clock delay on the master clock signal to obtain a clock delay signal; Performing an AND operation on the clock delay signal and the inverted second pulse signal to obtain a target clock signal, where the target clock signal is the delayed clock signal.

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