Short-loop instruction supply optimization method and device and processor

Abstract

The invention provides a short-loop instruction supply optimization method and device and a processor, and relates to the technical field of computer processors, and the method comprises the steps: obtaining an instruction fetch basic block corresponding to a short-loop instruction from an instruction cache through an instruction fetch part when a currently executed code segment is identified as the short-loop instruction; continuously writing the instruction fetch basic block into an instruction buffer queue for at least two times; the short-loop instruction is provided for the rear end of the processor through the instruction buffer queue, the short-loop body instruction is provided in an accelerated mode, the providing bandwidth of the short-loop instruction of the processor is multiplied, the problem that the bandwidth of the short-loop instruction providing instruction of the processor is insufficient is effectively solved, and the performance of the processor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer processors, and in particular, to a method, apparatus, and processor for optimizing the supply of short-loop instructions. Background Art

[0002] Modern high-performance processors generally adopt wide-issue and deep-pipeline designs to achieve higher instruction throughput. The issue width of high-performance processors is generally more than 6-issue, many are 8-issue, or even larger issue widths. To fully utilize the performance of the processor, the instruction fetch unit (IFU) needs to be able to fetch more instructions than the issue width in one cycle to provide sufficient instruction supply bandwidth. However, when the processor executes short loops, due to the small number of instructions in the loop body of the short loop (usually 3-4 instructions) and the jump address being limited within a relatively small basic block range, only the instructions of a single basic block can be fetched each time. For a wide-issue processor, the instruction bandwidth provided by a single fetch is insufficient to meet the requirements of the backend pipeline, resulting in a break in the instruction supply and pipeline stalls. This limits the performance of the processor in scenarios where short loops are executed frequently. Summary of the Invention

[0003] The present invention provides a method, apparatus, and processor for optimizing the supply of short-loop instructions, aiming to solve the defect in the traditional high-performance processor instruction supply method that for short-loop instructions, the instruction bandwidth provided by a single instruction fetch is insufficient to meet the requirements of the backend pipeline, resulting in a break in the instruction supply and pipeline stalls.

[0004] The present invention provides a method for optimizing the supply of short-loop instructions, including: When it is recognized that the currently executed code segment is a short-loop instruction, the fetch basic block corresponding to the short-loop instruction is obtained from the instruction cache through the instruction fetch unit; Writing the fetch basic block into the instruction buffer queue continuously at least twice; Providing short-loop instructions to the backend of the processor through the instruction buffer queue.

[0005] According to the method for optimizing the supply of short-loop instructions provided by the present invention, the recognition conditions for the short-loop instructions include: The loop body of the short-loop instruction is within a single fetch basic block; The target address of the transfer instruction of the short-loop instruction is the starting address of the fetch basic block.

[0006] The number of instructions in the loop body is less than or equal to 1 / 2 of the maximum capacity per cycle of the instruction buffer queue.

[0007] According to the short loop instruction supply optimization method provided by the present invention, when writing the fetch basic block into the instruction buffer queue continuously twice, the number of instructions in the fetch basic block satisfies being less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously within a single cycle. The maximum number of instructions allowed to enter the instruction buffer queue simultaneously within a single cycle is limited by the number of write ports of the instruction buffer queue.

[0008] According to the short loop instruction supply optimization method provided by the present invention, the number of times of writing the fetch basic block is dynamically adjusted according to the ratio of the maximum number of instructions allowed to enter the instruction buffer queue per cycle and the number of instructions in the short loop body.

[0009] According to the short loop instruction supply optimization method provided by the present invention, the number of times of writing the fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter the instruction buffer queue per cycle by the number of instructions in the short loop body, and taking the integer part downward.

[0010] According to the short loop instruction supply optimization method provided by the present invention, during the process of writing the fetch basic block into the instruction buffer queue, after taking the current fetch basic block, skip the fetch operation of the repeated fetch basic block, and directly reuse the fetch basic block that has been written.

[0011] The present invention provides a processor front-end device, including: A branch prediction unit, configured to generate a fetch request and write it into the fetch target queue; A short loop identification unit, integrated in the branch prediction unit, configured to identify short loop instructions from the fetch target queue; A fetch component, configured to extract a fetch basic block from the instruction cache when a short loop instruction is identified; An instruction filling control module, configured to receive the fetch basic block written into the instruction buffer queue continuously at least twice, and provide short loop instructions to the processor backend based on the instruction buffer queue.

[0012] According to the processor front-end device provided by the present invention, the short loop identification unit includes: A basic block boundary detection module, configured to determine whether the loop body of the short loop instruction is located in the same fetch basic block; A jump address matching module, configured to verify whether the target address of the transfer instruction of the short loop instruction is the starting address of the current fetch basic block; An instruction number judgment module, configured to judge whether the number of instructions in the loop body is less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously per cycle.

[0013] In the instruction filling control module of the processor front-end device provided by the present invention, the writing times of the fetch basic block are dynamically adjusted according to the ratio of the maximum number of instructions allowed to enter the instruction buffer queue per cycle and the number of instructions in the short loop body.

[0014] In the processor front-end device provided by the present invention, the writing times of the fetch basic block are equal to the value obtained by dividing the maximum number of instructions allowed to enter per cycle by the number of instructions in the short loop body, and then taking the integer part downward.

[0015] In the processor front-end device provided by the present invention, the fetch component is further configured to, during the process of writing the fetch basic block into the instruction buffer queue, after fetching the current fetch basic block, skip the fetch operation of the repeated fetch basic block and directly reuse the fetched basic block that has been written.

[0016] The present invention also provides a processor, including: the processor front-end device and the processor back-end as described in any one of the above; the processor front-end device provides short loop instructions to the processor back-end.

[0017] The short loop instruction supply optimization method, device and processor provided by the present invention, when identifying that the currently executed code segment is a short loop instruction, obtain the fetch basic block corresponding to the short loop instruction from the instruction cache through the fetch component; write the fetch basic block into the instruction buffer queue continuously at least twice; provide short loop instructions to the processor back-end through the instruction buffer queue, so as to realize the accelerated supply of short loop body instructions, multiply improve the instruction supply bandwidth of the processor for short loops, effectively solve the problem of insufficient instruction supply bandwidth for short loop instructions of the processor, and improve the performance of the processor. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a flowchart of the short loop instruction supply optimization method provided by the embodiment of the present invention; Figure 2 is a functional structure diagram of the processor front-end device provided by the embodiment of the present invention; Figure 3 is a functional structure diagram of the processor provided by the embodiment of the present invention. Detailed Embodiments

[0020] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0021] Figure 1 It is a flowchart of the short loop instruction supply optimization method provided by an embodiment of the present invention. As Figure 1 shown, the short loop instruction supply optimization method provided by an embodiment of the present invention includes: Step 101, when it is recognized that the currently executed code segment is a short loop instruction, obtain the fetch basic block corresponding to the short loop instruction from the instruction cache through the fetch component; Step 102, write the fetch basic block into the instruction buffer queue continuously at least twice; Step 103, provide short loop instructions to the processor backend through the instruction buffer queue.

[0022] In the scenario of high-frequency execution of short loops, the instruction bandwidth provided by a single fetch is insufficient to meet the requirements of the backend pipeline, resulting in an interruption in instruction supply and pipeline stalls. The performance of the processor is restricted in the scenario of high-frequency execution of short loops.

[0023] The short loop instruction supply optimization method provided by an embodiment of the present invention, when it is recognized that the currently executed code segment is a short loop instruction, obtains the fetch basic block corresponding to the short loop instruction from the instruction cache through the fetch component; writes the fetch basic block into the instruction buffer queue continuously at least twice; provides short loop instructions to the processor backend through the instruction buffer queue, realizes the accelerated supply of short loop body instructions, multiplies the instruction supply bandwidth of the short loop of the processor, effectively solves the problem of insufficient instruction bandwidth for the short loop instructions of the processor, and improves the performance of the processor.

[0024] Based on any of the above embodiments, the recognition conditions of the short loop instructions include: The loop body of the short loop instruction is within a single fetch basic block; The target address of the transfer instruction of the short loop instruction is the starting address of the fetch basic block; The number of loop body instructions is less than or equal to 1 / 2 of the maximum number of instructions that are allowed to enter the instruction buffer queue simultaneously in a single cycle.

[0025] In the embodiment of the present invention, an RISC-V assembly code example of a short loop is as follows: 1. Fixed number of loops (similar to for loop) li t0, 5 # Initialize counter t0 = 5 loop_start: # Loop body code addi t0, t0, -1 # t0 = t0 - 1 bnez t0, loop_start # If t0 ≠ 0, jump back to loop_start 2. Conditional loop (similar to while loop) li t1, 0 # Initialize conditional variable t1 = 0 loop_start: li t2, 10 # Set loop termination condition t2 = 10 bge t1, t2, loop_end # If t1 ≥ 10, jump to loop_end # Loop body code (e.g., arithmetic operations) addi t1, t1, 1 # t1 = t1 + 1 j loop_start # Unconditional jump back to the start of the loop loop_end: In the embodiments of the present invention, by taking advantage of the characteristic that the short loop repeatedly executes the instructions in the loop body within the range of one instruction fetch basic block, the short loop instructions are identified, and the acceleration of the loop body instructions of the short loop is realized, which multiplicatively improves the instruction supply bandwidth of the short loop instructions of the processor, effectively solves the problem that the processor cannot supply enough instructions for the short loop, and improves the performance of the processor.

[0026] In the embodiments of the present invention, when the instruction fetch basic block is written into the instruction buffer queue twice continuously, the number of instructions in the instruction fetch basic block satisfies being less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously in one cycle. The maximum number of instructions allowed to enter the instruction buffer queue simultaneously in one cycle is limited by the number of write ports of the instruction buffer queue.

[0027] In the embodiments of the present invention, the number of writes of the instruction fetch basic block is dynamically adjusted according to the ratio of the maximum number of instructions allowed to enter the instruction buffer queue in one cycle and the number of instructions in the loop body of the short loop. The number of writes of the instruction fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter the instruction buffer queue in one cycle by the number of instructions in the loop body of the short loop, and then taking the integer part downwards.

[0028] In a short loop optimization scenario with dynamically adjusted write times, such as a multi-threaded competition scenario, the ratio of the maximum number of instructions allowed to enter the IBuffer per cycle to the number of instructions in the short loop body is relatively large. The short loop optimization steps include: First, monitor the instructions in the short loop body and detect the number of instructions in the short loop body in real time. Make a dynamic decision based on the ratio of the maximum number of instructions allowed to enter per cycle to the number of instructions in the short loop body.

[0029] The write count of the fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter per cycle by the number of instructions in the short loop body, and then taking the integer part downward.

[0030] For example, if the number of instructions in the short loop body is 2 and the maximum number of instructions allowed to enter per cycle is 8, then the write count of the fetch basic block is 8 divided by 2, which is equal to 4. Another example, if the number of instructions in the short loop body is 3 and the maximum number of instructions allowed to enter per cycle is 16, then the write count of the fetch basic block is 16 divided by 3, taking the integer part downward, which is equal to 5.

[0031] In some embodiments of the present invention, during the process of writing the fetch basic block into the instruction buffer queue, after taking the current fetch basic block, skip the fetch operation for the repeated fetch basic block and directly reuse the already written fetch basic block.

[0032] In the short loop optimization scenario with a fixed write count, the processor has an issue width of 8, the IBuffer allows a maximum of 16 instructions to be written per cycle, and the short loop body contains 4 instructions. The recognition conditions are: The loop body is within the same fetch basic block.

[0033] The jump target address is the start address of the fetch basic block.

[0034] The number of instructions in the loop body ≤ 8 (16 / 2).

[0035] Write the fetch basic block continuously into the IBuffer twice, providing 8 instructions per cycle (4×2), which meets the issue width requirement.

[0036] When writing for the second time, directly reuse the cached instructions to reduce the number of ICache accesses. The instruction supply bandwidth is increased from 4 instructions per cycle to 8 instructions per cycle, effectively solving the problem of short loop instruction supply for the processor.

[0037] In an embodiment of the present invention, the conditions for determining a short loop are as follows: The loop body is within a fetch basic block, and the branch instruction jumps to the head address of a fetch basic block. For a short loop, the same fetch basic block is sent to the instruction buffer queue (IBuffer) twice each time, to solve the problem of insufficient instruction supply for the short loop. To make full use of the space of the IBuffer, the number of instructions in the fetch basic block satisfies less than or equal to n / 2, where n is the maximum number allowed to enter the IBuffer simultaneously in one cycle, and n is a positive integer. The maximum number allowed to enter the IBuffer simultaneously in one cycle is limited by the number of write ports of the IBuffer. Let m be the number of instructions in the fetch basic block, and m is a positive integer, that is, when m <= n / 2, two identical fetch basic blocks can be sent to the IBuffer each time.

[0038] For example, for a loop body within a fetch basic block where the branch instruction jumps to the head address of a fetch basic block, it is predicted as a short loop. When the maximum number allowed to enter the IBuffer simultaneously in one cycle is 16 items (n = 16), then n / 2 = 8, and the number of instructions in the fetch basic block of the short loop is 4 (m = 4), satisfying that the number of instructions in the short loop is less than or equal to n / 2, that is, m <= 8. Then the same fetch basic block is sent to the instruction buffer queue (IBuffer) twice each time, to solve the problem of insufficient instruction supply for the short loop. Specifically, after fetching the first fetch basic block of the short loop, the first fetch basic block is sent to the instruction buffer queue IBuffer twice, without fetching the second fetch basic block. Because the second fetch basic block of the short loop is the same as the first one. Similarly, after fetching the third fetch basic block of the short loop, the third fetch basic block is sent to the instruction buffer queue IBuffer twice, without fetching the fourth fetch basic block, and so on. In this way, two fetch basic blocks can be supplied at a time, increasing the instruction supply from 4 instructions in one cycle to 8 instructions in one cycle, doubling the instruction supply.

[0039] The short-loop instruction supply optimization method provided by the embodiment of the present invention can accelerate the supply of loop body instructions for short loops. When the processor backend issues instructions, there will be sufficient instruction supply, enabling the memory access and parallel execution functional units to work at full load. It avoids waste caused by insufficient instruction supply for short loops, resulting in underutilization of the processor backend resources. Therefore, the present invention can multiply increase the instruction supply bandwidth for short loops in the processor, effectively solve the problem of insufficient instruction supply for short loops in the processor, and improve the performance of the processor.

[0040] The processor front-end device provided by the embodiment of the present invention includes: A branch prediction unit for generating a fetch request and writing it into the fetch target queue; A short-loop identification unit integrated in the branch prediction unit for identifying short-loop instructions from the fetch target queue; An instruction fetch component, which is used to extract an instruction fetch basic block from an instruction cache when a short loop instruction is recognized; An instruction filling control module, which is used to receive the instruction fetch basic block written into an instruction buffer queue continuously at least twice, and provide a short loop instruction to a processor backend based on the instruction buffer queue.

[0041] As Figure 2 shown, the processing flow of a processor front-end device includes: a branch prediction component gives an instruction fetch basic block according to a predictor prediction result, inputs it into an instruction fetch target queue, responds to an instruction fetch request, inputs the instruction fetch basic block into the instruction fetch component, and writes two identical instruction fetch basic blocks into an instruction buffer in one short loop.

[0042] In an embodiment of the present invention, a short loop recognition unit is added to a branch prediction component at the processor front end. According to the characteristics of a short loop, the short loop is recognized. The branch prediction component provides an instruction fetch basic block for instruction fetch as an instruction fetch request according to a branch prediction result, writes it into an instruction fetch target queue (Fetch Target Queue, FTQ), the FTQ queue sends the instruction fetch request to an instruction fetch component (Instruction Fetch Unit, IFU) to fetch an instruction from an instruction cache (Instruction Cache, ICache), writes the fetched instruction into an instruction buffer queue (Instruction Buffer, IBuffer), and finally forms an instruction supply for the processor backend. The processor backend is mainly responsible for instruction scheduling, issuing, executing, writing back, committing, etc.

[0043] In an embodiment of the present invention, the short loop recognition unit includes: A basic block boundary detection module, which is used to determine whether a loop body of the short loop instruction is located in the same instruction fetch basic block; A jump address matching module, which is used to verify whether a target address of a transfer instruction of the short loop instruction is a start address of the current instruction fetch basic block; An instruction count judgment module, which is used to judge whether the number of instructions in the loop body is less than or equal to 1 / 2 of a maximum number of instructions allowed to enter the instruction buffer queue in one clock cycle.

[0044] According to the processor front-end device provided by the present invention, in the instruction filling control module, the writing times of the instruction fetch basic block are dynamically adjusted according to a ratio of a maximum number of instructions allowed to enter the instruction buffer queue in one clock cycle and the number of instructions in a short loop body. In an embodiment of the present invention, in the instruction filling control module, the writing times of the instruction fetch basic block are dynamically adjusted according to a ratio of a maximum number of instructions allowed to enter the instruction buffer queue in one clock cycle and the number of instructions in a short loop body.

[0045] In the embodiment of the present invention, the write count of the instruction fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter in a single cycle by the number of instructions in the short loop body, and then taking the integer part downward.

[0046] In the embodiment of the present invention, the instruction fetch component is further configured to, during the process of writing the instruction fetch basic block into the instruction buffer queue, after fetching the current instruction fetch basic block, skip the instruction fetch operation for the repeated instruction fetch basic block, and directly reuse the written instruction fetch basic block.

[0047] The processor front-end device provided by the embodiment of the present invention, when identifying that the currently executed code segment is a short loop instruction, obtains the instruction fetch basic block corresponding to the short loop instruction from the instruction cache through the instruction fetch component; writes the instruction fetch basic block into the instruction buffer queue continuously at least twice; and provides the short loop instruction to the processor back-end through the instruction buffer queue, so as to realize the acceleration of the short loop body instructions, multiply improve the instruction supply bandwidth of the processor for short loops, effectively solve the problem of insufficient instruction supply bandwidth for the processor short loops, and improve the performance of the processor.

[0048] The embodiment of the present invention also provides a processor, as Figure 3 shown, including: the processor front-end device 301 and the processor back-end 302 as described in the above embodiment; the processor front-end device 301 provides short loop instructions to the processor back-end 302.

[0049] In the application scenario of a multi-threaded processor, the optimization strategy for multi-threaded shared instruction cache is: Independently configure a short loop recognition unit and an IBuffer for each thread.

[0050] The embodiment of the present invention can reduce the competition among multiple threads and improve the overall throughput.

[0051] Through the acceleration of the short loop body instructions provided by the embodiment of the present invention, when the processor back-end issues instructions, there will be sufficient instruction supply, enabling the memory access and parallel execution functional units to work at full load. Avoiding waste caused by the insufficient instruction supply of the short loop, resulting in the underutilization of the processor back-end resources. Therefore, the embodiment of the present invention can multiply improve the instruction supply bandwidth of the processor for short loops, effectively solve the problem of insufficient instruction supply for the processor short loops, and improve the performance of the processor.

[0052] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0053] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An optimization method for short loop instruction supply, characterized in that, including: When it is recognized that the currently executed code segment is a short loop instruction, the fetch unit fetches the fetch basic block corresponding to the short loop instruction from the instruction cache; writing the fetch basic block into the instruction buffer queue continuously at least twice; providing the short loop instruction to the processor backend through the instruction buffer queue.

2. The short loop instruction supply optimization method according to claim 1, characterized in that The recognition conditions of the short loop instruction include: the loop body of the short loop instruction is within a single fetch basic block; the target address of the transfer instruction of the short loop instruction is the starting address of the fetch basic block; the number of instructions in the loop body instruction is less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously in one cycle.

3. The short-cycle instruction supply optimization method according to claim 2, characterized in that When writing the fetch basic block into the instruction buffer queue continuously twice, the number of instructions in the fetch basic block satisfies being less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously in one cycle.

4. The short cycle instruction supply optimization method according to claim 1, characterized in that The number of times of writing the fetch basic block is dynamically adjusted according to the ratio of the maximum number of instructions allowed to enter the instruction buffer queue in one cycle and the number of instructions in the short loop body.

5. The short cycle instruction supply optimization method according to claim 4, characterized in that The number of times of writing the fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter in one cycle by the number of instructions in the short loop body, and taking the integer downward.

6. The short cycle instruction supply optimization method according to claim 1, characterized in that, During the process of writing the fetch basic block into the instruction buffer queue, after fetching the current fetch basic block, skip the fetch operation of the repeated fetch basic block and directly reuse the fetched basic block that has been written.

7. A processor front-end device, characterized in that, including: a branch prediction unit for generating a fetch request and writing it into the fetch target queue; a short loop recognition unit integrated in the branch prediction unit for recognizing short loop instructions from the fetch target queue; a fetch unit for fetching the fetch basic block from the instruction cache when a short loop instruction is recognized; an instruction filling control module for receiving the fetch basic block written into the instruction buffer queue continuously at least twice and providing the short loop instruction to the processor backend based on the instruction buffer queue.

8. The front-end device of a processor according to claim 7, wherein The short loop recognition unit includes: a basic block boundary detection module for determining whether the loop body of the short loop instruction is within the same fetch basic block; a jump address matching module for verifying whether the target address of the transfer instruction of the short loop instruction is the starting address of the current fetch basic block; an instruction number judgment module for judging whether the number of instructions in the loop body is less than or equal to 1 / 2 of the maximum number of instructions allowed to enter the instruction buffer queue simultaneously in one cycle.

9. The front-end device of a processor according to claim 7, wherein In the instruction filling control module, the number of times of writing the fetch basic block is dynamically adjusted according to the ratio of the maximum number of instructions allowed to enter the instruction buffer queue in one cycle and the number of instructions in the short loop body.

10. The processor front-end device according to claim 9, characterized in that, In the instruction filling control module, the number of times of writing the fetch basic block is equal to the value obtained by dividing the maximum number of instructions allowed to enter in one cycle by the number of instructions in the short loop body, and taking the integer downward.

11. The processor front-end device according to claim 7, characterized in that, The fetch unit is further used for skipping the fetch operation of the repeated fetch basic block and directly reusing the fetched basic block that has been written during the process of writing the fetch basic block into the instruction buffer queue.

12. A processor, characterized in that, including: the processor front-end device and the processor backend according to any one of claims 7 to 11; The processor front-end device provides short-loop instructions to the processor back-end.

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