Testing device and testing method

Abstract

The invention provides a testing device and a testing method, which can be applied to the technical field of memory testing. The test device comprises a test board which simulates a memory unit inserted in a memory slot to be tested to transmit a test data signal and a test electric signal; the dial-up memory module is used for controlling the dial-up switch to configure a test memory address of the first memory based on a predetermined memory address, so that the control module of the mainboard to be tested performs read-write operation on the first memory through the integrated circuit bus to obtain a test data signal; the function detection module is used for collecting a test electric signal from a power supply module of the mainboard to be tested, and a response signal and log data from the control module, and testing the test electric signal, the response signal and the log data to obtain a function test result; and the plurality of signal lead-out test points are used for leading the test data signals and the test electric signals to external detection equipment, so that the external detection equipment obtains a signal test result according to the test data signals and the test electric signals.

Description

Technical Field

[0001] This application relates to the technical field of memory testing, and more particularly to a testing device and a testing method. Background Art

[0002] With the increasing data processing volume and processing speed of servers, multiple memories are usually configured during the operation of the server to store the data to be calculated and the related data after calculation of the server, so as to better improve the working performance of the server. Therefore, before the memory device operates normally, it is usually necessary to test the memory device so that the memory device can operate normally in cooperation with the server. Summary of the Invention

[0003] In view of the above problems, this application provides a testing device and a testing method.

[0004] According to the first aspect of this application, a testing device is provided, including: a test board, which is used to simulate the memory unit inserted in the memory slot under test of the main board under test to transmit test data signals and test electrical signals when inserted into the memory slot under test of the main board under test; a DIP memory module, which is arranged on the test board and includes a DIP switch and a first memory, and is used to configure the test memory address of the first memory by controlling the DIP switch based on a predetermined memory address, so that the control module of the main board under test performs read and write operations on the first memory through an integrated circuit bus to obtain test data signals; a function detection module, which is arranged on the test board and is used to collect test electrical signals from the power supply module of the main board under test, response signals and log data from the control module, and test the test electrical signals, response signals and log data to obtain a function test result; a plurality of signal extraction test points, which are arranged on the side of the test board away from the memory slot under test and are used to lead out the test data signals and test electrical signals to an external detection device, so that the external detection device obtains a signal test result according to the test data signals and test electrical signals.

[0005] The second aspect of this application provides a testing method, including: when the test board is inserted into the memory slot under test of the main board under test, configuring the test memory address of the first memory by controlling the DIP switch in the DIP memory module based on a predetermined memory address; in response to the control module performing read and write operations on the first memory through an integrated circuit bus, obtaining and transmitting test data signals to a plurality of signal extraction test points; using the function detection module to collect test electrical signals from the power supply module of the main board under test, response signals and log data from the control module of the main board under test, and using the function detection module to test the test electrical signals, response signals and log data to obtain a function test result; transmitting test electrical signals to a plurality of signal extraction test points, so that the external detection device obtains a signal test result according to the test data signals and test electrical signals.

[0006] According to an embodiment of the present application, the test device may include a test board, a DIP memory module, a function detection module, and a plurality of signal extraction test points. The DIP memory module and the function detection module are both arranged on the test board, and the plurality of signal extraction test points are all arranged on the side of the test board away from the memory slot to be tested. The DIP memory module includes a DIP switch and a first memory. When it is necessary to use the test device to test the memory slot to be tested, the memory unit to be tested, and the main board to be tested, one side of the test board can be inserted into the memory slot to be tested, so as to use the test board to simulate the insertion of the memory unit to be tested into the memory slot to be tested, and the test board is used to simulate the memory unit to transmit test data signals and test electrical signals. Therefore, during the test stage, it is not necessary to insert the memory unit to be tested into the memory slot to be tested, so as to avoid damage to the memory unit caused by the failure of the memory slot to be tested and the main board to be tested, and improve the detection efficiency.

[0007] According to an embodiment of the present application, then, according to the predetermined memory address of the memory slot to be tested, a plurality of DIP switches electrically connected to the first memory are adjusted to make the test memory address of the first memory on the test board inserted in the memory slot to be tested match the predetermined memory address, so that the control module on the main board to be tested performs read and write operations on the first memory through the I 2 C signal path or the I 3 C signal path integrated circuit bus, so that the first memory stores binary data instructions corresponding to the signal commands issued by the control module. By contacting an external detection device with a plurality of signal extraction test points located on the upper side of the test board, the binary data instructions are led out to the plurality of signal extraction test points and the external detection device through the signal path in the test board. The external detection device collects the test data signals transmitted by the control module on the main board to be tested via the memory slot to be tested and the test board, thereby realizing leading out the test data signals to the outside of the test board, so that it is convenient for the external detection device to simply and efficiently obtain the test data signals, improve the detection efficiency, and further can detect a batch of memory slots and main boards to be tested.

[0008] According to an embodiment of the present application, according to different test requirements, the function detection module can collect test electrical signals for powering the memory unit via the memory slot under test, or response signals and log data issued by the control module, so as to test the test electrical signals, response signals or log data respectively, and functional test results regarding the memory slot under test and the main board under test can be obtained, thereby realizing the function detection of the power supply function and the control module. At the same time, by contacting an external detection device with a plurality of signal extraction test points located on the upper side of the test board, the test electrical signals can be led out to the plurality of signal extraction test points and the external detection device through the conduction path in the test board, and the power supply signals of the main board under test can be collected by the external detection device, realizing the leading out of the test electrical signals to the outside of the test board for facilitating the analysis and detection of the test electrical signals, so as to perform an overall test on the memory slot under test, the memory unit under test and the main board under test, so that the memory unit can move normally when inserted into the memory slot. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Through the following description of the embodiments of the present application with reference to the drawings, the above content and other objects, features and advantages of the present application will become clearer. In the drawings:

[0010] Figure 1 A schematic diagram of a test device according to an embodiment of the present application is shown;

[0011] Figure 2 A schematic diagram of a DIP switch memory module according to an embodiment of the present application is shown;

[0012] Figure 3 A schematic diagram of a function detection module according to an embodiment of the present application is shown;

[0013] Figure 4 A schematic diagram of a test device according to another embodiment of the present application is shown;

[0014] Figure 5 A flowchart of a test method according to an embodiment of the present application is shown.

[0015] Figure 6 A flowchart of power consumption testing according to an embodiment of the present application is shown;

[0016] Figure 7 A flowchart of memory slot detection according to an embodiment of the present application is shown;

[0017] Figure 8 A flowchart of log detection according to an embodiment of the present application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present application. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present application.

[0019] The terms used herein are merely for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0020] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0021] In the case of using expressions such as "at least one of A, B, and C", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0022] With the increasing data processing volume and processing speed of the server, multiple memories are usually configured during the operation of the server to store the data to be calculated and the related data after calculation of the server, so as to better improve the working performance of the server. Thus, before the memory device operates normally, it is usually necessary to test the memory device so that the memory device can operate normally in cooperation with the server.

[0023] Embodiments of the present application provide a test device, including a test board, which is used to simulate a memory unit inserted in a memory slot under test of a main board under test to transmit test data signals and test electrical signals when inserted into the memory slot under test of the main board under test; a DIP memory module, disposed on the test board, including a DIP switch and a first memory, and is used to configure the test memory address of the first memory by controlling the DIP switch based on a predetermined memory address, so that the control module of the main board under test can perform read and write operations on the first memory through an integrated circuit bus to obtain test data signals; a function detection module, disposed on the test board, is used to collect test electrical signals from the power supply module of the main board under test, response signals and log data from the control module, and test the test electrical signals, response signals and log data to obtain a function test result; and a plurality of signal extraction test points, disposed on a side of the test board away from the memory slot under test, are used to extract the test data signals and test electrical signals to an external detection device, so that the external detection device can obtain a signal test result according to the test data signals and test electrical signals.

[0024] According to an embodiment of the present application, the test device may include a test board, a DIP memory module, a function detection module, and a plurality of signal extraction test points.

[0025] According to an embodiment of the present application, the test board is used to simulate a memory unit inserted in a memory slot under test to transmit test data signals and test electrical signals when inserted into the memory slot under test of the main board under test.

[0026] Multiple conductive paths and I 2 C signal paths and I 3 C signal paths may be arranged in the test board. Through the conductive paths and signal paths, electrical signals and data signals can be transmitted to corresponding detection modules and test points, so as to facilitate the detection of the electrical signals and data signals.

[0027] Before the test, multiple test boards need to be inserted into multiple memory slots under test on the main board under test respectively, so as to use the test board to simulate the memory module under test, that is, the memory unit. Then, the main board under test and the baseboard management controller and processor disposed on the main board under test are in a normal operating state, so as to transmit test electrical signals and test data signals to the memory slot under test and the test board, so that the test board can simulate the memory unit under test to perform signal transmission and other detection work, so as to detect the memory slot under test, the main board under test, and the memory unit under test.

[0028] According to an embodiment of the present application, the DIP memory module, disposed on the test board, includes a DIP switch and a first memory, and is used to configure the test memory address of the first memory by controlling the DIP switch based on a predetermined memory address, so that the control module of the main board under test can perform read and write operations on the first memory through an integrated circuit bus to obtain test data signals.

[0029] The control module of the motherboard to be tested may include a baseboard management controller and a processor provided on the motherboard to be tested.

[0030] The DIP memory module may include a plurality of DIP switches, usually three DIP switches. The plurality of DIP switches are electrically connected to the first memory. By toggling the DIP switches, the 0 / 1 addresses of the first memory are switched, so that the test memory address of the first memory is the same as the predetermined memory address of the memory slot to be tested, facilitating the storage of data signals into the first memory for retrieval. The predetermined memory address may be the memory address pre-allocated by the baseboard management controller or the processor for a plurality of memory slots. Usually, there may be eight memory slots to be tested on each side of the baseboard management controller or the processor. The eight memory slots to be tested on one side may be defined as A0, A1, B0, B1, C0, C1, D0, D1, and the eight memory slots to be tested on the other side may be defined as E0, E1, F0, F1, G0, G1, H0, H1. The predetermined memory addresses of the A0 and E0 memory slots to be tested may be the same. Similarly, the predetermined memory addresses of the A1 and E1, B0 and F0, B1 and F1, C0 and G0, C1 and G1, D0 and H0, D1 and H1 memory slots to be tested may be the same.

[0031] According to an embodiment of the present application, a function detection module is provided on the test board, and is configured to collect test electrical signals from the power supply module of the motherboard to be tested, response signals and log data from the control module, and test the test electrical signals, response signals and log data to obtain a function test result.

[0032] By inserting the test board into the memory slot to be tested, the function detection module is used to collect the test electrical signals provided by the motherboard to be tested to the memory slot and the memory unit to be tested, as well as the response signals and log data from the baseboard management controller or the processor. Then, according to the test requirements, the collected test electrical signals, response signals and log data are respectively detected to obtain function test results corresponding to each detection.

[0033] According to an embodiment of the present application, a plurality of signal extraction test points are provided on the side of the test board away from the memory slot to be tested, and are configured to extract test data signals and test electrical signals to an external detection device, so that the external detection device obtains a signal test result according to the test data signals and test electrical signals.

[0034] The plurality of signal extraction test points are respectively electrically connected to the DIP memory module and the function detection module through signal paths and conductive paths. Thus, when the external detection device is electrically connected to the plurality of signal extraction test points respectively, the test data signals and test electrical signals can be extracted to the external detection device, and thus the external detection device can read and detect the test data signals and test electrical signals. Among them, the external detection device may be an oscilloscope.

[0035] By arranging multiple signal extraction test points on the side of the test board away from the memory slot under test, that is, on the side of the test board away from the side where the memory slot under test is inserted, it is not necessary to make the probe head of the external detection device penetrate to the bottom of the memory module. Especially when there are multiple memory modules inserted on the main board, it is difficult for the probe head of the external detection device to penetrate to the contact test points at the bottom of each memory module, greatly reducing the difficulty of obtaining test data signals and test electrical signals. Multiple external detection devices can be used to simultaneously obtain test electrical signals and test data signals from multiple test boards, facilitating waveform capture.

[0036] According to an embodiment of the present application, the test device may include a test board, a DIP memory module, a function detection module, and multiple signal extraction test points. The DIP memory module and the function detection module are both arranged on the test board, and the multiple signal extraction test points are all arranged on the side of the test board away from the memory slot under test. The DIP memory module includes a DIP switch and a first memory. When it is necessary to use the test device to test the memory slot under test, the memory unit under test, and the main board under test, one side of the test board can be inserted into the memory slot under test to use the test board to simulate the insertion of the memory unit under test into the memory slot under test, and the test board is used to simulate the memory unit to transmit test data signals and test electrical signals. Thus, it is not necessary to insert the memory unit under test into the memory slot under test during the test stage to avoid damage to the memory unit caused by the failure of the memory slot under test and the main board under test, improving the detection efficiency.

[0037] According to an embodiment of the present application, then, according to the predetermined memory address of the memory slot under test, multiple DIP switches electrically connected to the first memory are adjusted to make the test memory address of the first memory on the test board inserted into the memory slot under test match the predetermined memory address. Thus, the control module on the main board under test performs read and write operations on the first memory through the I 2 C circuit bus or the integrated circuit bus of the I 3 C circuit bus, so that the first memory stores binary data instructions corresponding to the signal commands issued by the control module. By contacting the external detection device with multiple signal extraction test points located on the upper side of the test board, the binary data instructions are led out to the multiple signal extraction test points and the external detection device through the signal path in the test board. The external detection device is used to collect the test data signals transmitted by the control module on the main board under test via the memory slot under test and the test board, thus realizing the extraction of the test data signals to the outside of the test board, facilitating the simple and efficient acquisition of test data signals by the external detection device, improving the detection efficiency, and further enabling the detection of a batch of memory slots and main boards under test.

[0038] According to an embodiment of the present application, according to different test requirements, the function detection module can collect test electrical signals for powering the memory unit via the memory slot under test, or response signals and log data issued by the control module, so as to test the test electrical signals, response signals or log data respectively, and functional test results regarding the memory slot under test and the main board under test can be obtained, thereby realizing the function detection of the power supply function and the control module. At the same time, by contacting the external detection device with multiple signal extraction test points located on the upper side of the test board, the test electrical signals can be led out to the multiple signal extraction test points and the external detection device through the conduction path in the test board. The external detection device can collect the power supply signals of the main board under test, realizing the lead-out of the test electrical signals to the outside of the test board, so as to facilitate the analysis and detection of the test electrical signals, and thus the overall test of the memory slot under test, the memory unit under test and the main board under test, so that the memory unit can move normally when inserted into the memory slot.

[0039] Figure 1 FIG. shows a schematic diagram of a test device according to an embodiment of the present application.

[0040] As Figure 1 shown, the test device may include a test board 101, a DIP memory module 102, a function detection module 103, and multiple signal extraction test points 104. The test board 101 is inserted into the memory slot 105 under test.

[0041] According to an embodiment of the present application, the test device may further include multiple test gold finger pins, a warning module, and an information interface.

[0042] According to an embodiment of the present application, the multiple test gold finger pins are arranged on the test board and are used to be electrically connected to the memory slot under test when the test board is inserted into the memory slot under test, so that the test data signals and test electrical signals are transmitted to the test board.

[0043] The multiple test gold finger pins may be multiple memory gold finger pins identical to the bottom of the memory unit. The side provided with the multiple test gold finger pins is inserted into the memory slot under test, so that the multiple test gold finger pins are electrically connected to the pins in the memory slot under test, and thus the test data signals or test electrical signals on the main board under test are transmitted to the test board through the gold finger pins.

[0044] According to an embodiment of the present application, the warning module is arranged on the test board and is used to generate a warning mark according to the functional test result.

[0045] The warning module may include multiple warning lights. According to different test results, the on / off, on / off frequency, and number of times of the multiple warning lights can be controlled to correspond to different test results, so as to facilitate intuitively seeing the current test status and results.

[0046] According to an embodiment of the present application, an information interface is provided on a side of the test board away from the memory slot to be tested, and is used to connect to an external detection device so that the functional test result can be transmitted to the external detection device.

[0047] The information interface can be a USB interface or a Bluetooth interface. By connecting the external detection device to the information interface, the functional test result can be transmitted to the external detection device, so as to facilitate further analysis of the functional test result in the external detection device. Among them, the external detection device connected to the information interface can be a computing processing device, for example, a computer.

[0048] According to an embodiment of the present application, the test device can further include a warning module and an information interface. By cooperating with the warning module, the current functional test result can be displayed, so as to facilitate obtaining the abnormal functional test result by using the external detection device connected to the information interface, and analyzing the test result, debugging the memory slot to be tested and the main board to be tested, etc., to improve the detection efficiency and detection intuitiveness.

[0049] According to an embodiment of the present application, the first memory can also be used when the predetermined memory address is the same as the test memory address. In response to the control module writing to the first memory through the integrated circuit bus, the test data signal is obtained and backed up, so as to read the test data signal when the test device is connected to multiple signal extraction test points.

[0050] The first memory can be an EEPROM (Electrically Erasable Programmable Read-Only Memory). Based on the predetermined memory address of the memory slot to be tested, multiple DIP switches are toggled to make the test memory address the same as the predetermined memory address, and the initialization configuration of the address of the test board is completed.

[0051] The setting relationship between the DIP switches, the test memory address of the first memory, and the memory slot to be tested can be shown in Table 1.

[0052] Table 1

[0053]

[0054] Among them, there can be three DIP switches on each test board, corresponding to the test memory address to be debugged. For example, when it is determined that the current memory slot to be tested is a memory slot with address A0, it can be determined that the predetermined memory address of the memory slot to be tested is 0x00, and the DIP switches need to be toggled so that the test memory address of the first memory is 0x00.

[0055] When the test memory address configuration is completed, control instructions can be sent to the baseboard management controller or the processor in the control module on the motherboard to be tested, so that the baseboard management controller or the processor generates binary data instructions and passes them through the I 2 C circuit bus or I 3 C circuit bus is converted into a data waveform signal corresponding to the binary data instruction to perform a write operation on the first memory, so that the first memory stores the binary data instruction corresponding to it according to the received data waveform signal and performs backup processing. When using an external detection device to be electrically connected to the signal extraction test point, the backup stored binary data instruction passes through the I in the test board 2 C circuit bus or I 3 C circuit bus is converted into a data waveform signal and collected by the external detection device. Among them, the binary data instruction generated by the baseboard management controller in the control module and the data waveform signal corresponding to the binary data instruction generated by the baseboard management controller can pass through the I 2 C circuit bus transmission, the binary data instruction generated by the processor and the data waveform signal corresponding to the binary data instruction generated by the processor can pass through the I 3 C circuit bus transmission.

[0056] According to the embodiments of the present application, by adjusting the 0 / 1 of multiple dip switches on the test board, the test memory address of the first memory is made the same as the predetermined memory address, so that the baseboard management controller or the processor can perform read and write operations on the first memory. By controlling the baseboard management controller or the processor to perform a write operation on the first memory, the binary data instruction is backed up and stored in the first memory. When using an external detection device to obtain the test data signal through multiple signal extraction test points arranged on one side of the test board far from the memory slot to be tested, the binary data instruction stored in the first memory passes through the I in the test board 2 C circuit bus or I 3 C circuit bus is converted into a test data signal and collected by the external detection device, thus realizing the extraction of the test data signal to the external detection device through multiple signal extraction test points arranged on the outside, without the need to insert the probe deep into the test point of one of the multiple memory modules to obtain the acquisition signal, improving the convenience of obtaining the test data signal and enabling the simultaneous acquisition of the test data signals transmitted by multiple memory slots to be tested. Further, by analyzing and detecting the obtained test data signal from the baseboard management controller or the processor, the signal quality of the test data signal transmitted through the I 2 C circuit bus or I 3 C circuit bus can be detected and evaluated to obtain the signal quality detection result of the memory slot to be tested.

[0057] Figure 2Shows a schematic diagram of a DIP memory module according to an embodiment of the present application.

[0058] As Figure 2 shown, the test device may include a test board 101, a DIP memory module 102, a function detection module 103, and a plurality of signal extraction test points 104. The test board 101 is inserted into the memory slot 105 to be tested. The DIP memory module 102 may include three DIP switches 201 and a first memory 202. By adjusting the three DIP switches 201, the test memory address of the first memory 202 can be adjusted.

[0059] According to an embodiment of the present application, the plurality of signal extraction test points may include a first data signal extraction test point and a second data signal extraction test point.

[0060] According to an embodiment of the present application, the first data signal extraction test point is used to extract the first test data signal from the management controller to an external detection device.

[0061] The first data signal extraction test point may be a test point corresponding to the test data signal transmitted by the I 2 C circuit bus. The first test data signal may represent the data signal corresponding to the binary data instruction issued by the baseboard management controller.

[0062] According to an embodiment of the present application, the second data signal extraction test point is used to extract the second test data signal from the processor to an external detection device.

[0063] The second data signal extraction test point may be a test point corresponding to the test data signal transmitted by the I 3 C circuit bus. The second test data signal may represent the data signal corresponding to the binary data instruction issued by the processor.

[0064] According to an embodiment of the present application, by respectively setting up the first data signal extraction test point and the second data signal extraction test point, the external detection device can be electrically connected to different extraction test points to obtain different first test data signals or second test data signals, so as to detect and evaluate the signal quality of the first test data signal transmitted by the I 2 C circuit bus and the signal quality of the second test data signal transmitted by the I 3 C circuit bus respectively.

[0065] According to an embodiment of the present application, the functional test results may include power consumption test sub-results, slot self-detection test sub-results, and log fault test sub-results.

[0066] According to an embodiment of the present application, the function detection module may include an electrical signal acquisition sub-module, a microcontroller, a memory slot self-test sub-module, and a log storage sub-module.

[0067] According to an embodiment of the present application, the electrical signal acquisition sub-module is electrically connected to the microcontroller and is configured to collect and transmit a test electrical signal and signal acquisition time information to the microcontroller, where the test electrical signal includes a test voltage signal and a test current signal.

[0068] The electrical signal acquisition sub-module may include a voltage acquisition unit and a current acquisition unit. The current acquisition unit may include a current measuring resistor. First, the voltage acquisition unit is used to collect the test voltage signal from the main board to be tested, and then the test voltage signal is passed through the current measuring resistor to obtain the test current signal. Thus, in the case where power consumption testing is required, the current power consumption test sub-result can be detected based on the test voltage signal and the test current signal.

[0069] According to an embodiment of the present application, the multiple signal lead-out test points may further include an electrical signal lead-out test point.

[0070] According to an embodiment of the present application, the electrical signal lead-out test point is configured to lead out the test electrical signal to an external detection device.

[0071] The electrical signal lead-out test point may include a voltage signal lead-out test point or a current signal lead-out test point. By electrically connecting the external detection device to the electrical signal lead-out test point, the test electrical signal can be obtained, so as to analyze and process the test electrical signal to obtain the power supply status of the main board to be tested for the memory slot and memory unit to be tested.

[0072] According to an embodiment of the present application, by setting up the electrical signal lead-out test point, even in the case of multiple memory slots to be tested, the external detection device can simply obtain the test electrical signal, so as to detect and evaluate the test voltage signal or test current signal transmitted by the main board to be tested via the conduction path.

[0073] According to an embodiment of the present application, the microcontroller is configured to perform a power consumption test on the test electrical signal in response to receiving the test electrical signal and the signal acquisition time information to obtain a power consumption test sub-result; obtain a response signal and log data, and perform tests on the response signal and the log data respectively to obtain a slot self-test sub-result and a log fault test sub-result.

[0074] When it is necessary to perform slot testing on the memory slot to be tested and fault detection testing on the log data of the mainboard to be tested, the microcontroller can send a slot test request and a fault detection request to the baseboard management controller or the processor on the mainboard to be tested, so that the microcontroller can perform detection based on the received response signal or log data from the baseboard management controller or the processor, and thus the slot self-test sub-result or the log fault test sub-result can be obtained.

[0075] According to an embodiment of the present application, the memory slot self-test sub-module is electrically connected to the microcontroller and is used to store the slot self-test sub-result.

[0076] When it is necessary to perform slot testing on the memory slot to be tested, the microcontroller can store both the obtained response signal and the slot self-test sub-result in the memory slot self-test sub-module, so that the detection result and the response signal can be retrieved from the memory slot self-test sub-module at any time.

[0077] According to an embodiment of the present application, the log storage sub-module is electrically connected to the microcontroller and is used to store the log fault test sub-result.

[0078] When it is necessary to perform fault detection testing on the log data, the microcontroller can store both the obtained log data and the log fault test sub-result in the log storage sub-module, so that the detection result and the log data can be retrieved from the log storage sub-module at any time for analysis and verification.

[0079] According to an embodiment of the present application, the function detection module may include an electrical signal acquisition sub-module, a microcontroller, a memory slot self-check sub-module, and a log storage sub-module. The electrical signal acquisition sub-module is used to collect the test voltage signal and the test current signal in real time. The real-time power supply information from the main board under test to the memory slot under test and the memory unit can be obtained by using an external detection device, so as to analyze the power supply state according to the waveform information of the test electrical signal, and then transmit the test voltage signal and the test current signal to the microcontroller. The microcontroller can obtain and analyze the test electrical signal, the response signal, and the log data according to different test requirements. In the case of power consumption testing, the microcontroller performs power consumption testing based on the received test voltage signal and test current signal to obtain a sub-result of the power consumption test, so as to analyze the power consumption of the current baseboard management controller or the processor. In the case of self-detection testing of the memory slot under test, the microcontroller can obtain the corresponding response signal from the baseboard management controller or the processor, so as to determine whether there is an abnormality in the slot of the memory slot under test. In the case of testing log data, the microcontroller can obtain the corresponding log data from the baseboard management controller or the processor, so as to perform analysis and detection of faults and other aspects on the log data. Even when there are multiple memory slots under test on the main board under test, it is possible to simultaneously obtain the test electrical signals of multiple memory slots under test, and at the same time, different test analyses can be performed using the microcontroller according to different test requirements, so as to perform diversified and multi-dimensional testing on the main board under test, the memory slot under test, and the memory unit, so that the memory unit can operate normally in cooperation with the baseboard management controller or the processor.

[0080] Figure 3 FIG. shows a schematic diagram of a function detection module according to an embodiment of the present application.

[0081] As Figure 3 shown, on the test board 101 inserted into the memory slot 105 under test, there are provided a DIP switch memory module 102, a function detection module 103, and a plurality of signal extraction test points 104. The function detection module 103 includes a voltage acquisition unit 301, a current acquisition unit 302, a microcontroller 303, a memory slot self-check sub-module 304, and a log storage sub-module 305. The voltage acquisition unit 301 and the current acquisition unit 302 are used to collect the test voltage signal and the test current signal, and the microcontroller 303 is used to perform function detection.

[0082] According to an embodiment of the present application, the log fault test sub-result may include power consumption instantaneous state test information and operation state test information.

[0083] The instantaneous power consumption status test information can be characterized as the status information of the instantaneous power consumption provided by the motherboard under test to the memory slot under test. The operating status test information can be characterized as the total power consumption value of the baseboard management controller or the processor per unit time. Based on the operating status test information, the working status of the current baseboard management controller or processor can be judged.

[0084] According to an embodiment of the present application, the microcontroller is further configured to obtain the instantaneous power consumption status test information according to the test instantaneous power consumption value and the first power consumption threshold obtained based on the test voltage signal and the test current signal.

[0085] When the microcontroller receives the test voltage signal and the test current signal, it multiplies the test voltage signal and the test current signal to obtain the test instantaneous power consumption value. According to the test instantaneous power consumption value and the first power consumption threshold, when the test instantaneous power consumption value is greater than or equal to the first power consumption threshold, it is determined that the instantaneous power consumption status test information can be the instantaneous high power consumption state, and when the test instantaneous power consumption value is less than the first power consumption threshold, it is determined that the instantaneous power consumption status test information can be the instantaneous normal power consumption state.

[0086] According to an embodiment of the present application, the operating status test information of the control module is obtained according to the test total power consumption value and the second power consumption threshold obtained based on the test voltage signal, the test current signal, and the signal acquisition period.

[0087] While collecting the measured voltage signal and the measured current signal, the time of collecting the signal is obtained, that is, the signal acquisition period. Integral processing is performed according to the test voltage signal, the test current signal, and the signal acquisition period to obtain the total power consumption value per unit time, that is, the test total power consumption value, and the total power consumption curve is obtained by plotting according to the total power consumption value per unit time.

[0088] According to the total power consumption value and the second power consumption threshold obtained after integral processing, when the test total power consumption value is greater than or equal to the second power consumption threshold, it is determined that the operating status test information can be the full-load working state, and when the test total power consumption value is less than the second power consumption threshold, it is determined that the operating status test information can be the normal working state. Based on the operating status test information, the working status of the current baseboard management controller or processor can be evaluated, so as to adjust the baseboard management controller or the processor.

[0089] According to an embodiment of the present application, while receiving a test voltage signal and a test current signal, the microcontroller acquires a signal acquisition period, multiplies the test voltage signal and the test current signal to obtain an instantaneous test power consumption value, and then performs an integration process on the test voltage signal, the test current signal, and the signal acquisition period to obtain a total test power consumption value. Threshold judgment is performed based on the instantaneous test power consumption value and a first power consumption threshold, as well as the total test power consumption value and a second power consumption threshold, and the current instantaneous power consumption state test information and operating state test information are analyzed to implement the power consumption processing of the test voltage signal and the test current signal by the microcontroller, so as to determine the working operating states of the current memory slot to be tested, the motherboard to be tested, and the baseboard management controller or the processor based on the analyzed instantaneous power consumption state test information and operating state test information, for the purpose of adjustment.

[0090] According to the instantaneous power consumption state test information and the operating state test information, multiple warning lights in the warning module can be used to perform detection and reminder operations. For example, when the instantaneous test power consumption value is greater than or equal to the first power consumption threshold, the red warning light is controlled to be always on; when the instantaneous test power consumption value is less than the first power consumption threshold, the green warning light is controlled to be always on. When the total power consumption value is greater than or equal to the second power consumption threshold, the red warning light is controlled to flash; when the total power consumption value is less than the second power consumption threshold, the green warning light is controlled to flash.

[0091] According to an embodiment of the present application, the microcontroller is further configured to send a handshake signal to the control module through an integrated circuit bus.

[0092] When it is necessary to detect the slot status of the memory slot to be tested, the microcontroller can actively send a handshake signal to the baseboard management controller or the processor, where the slot status may include states such as whether the memory slot to be tested has poor contact or damage, resulting in abnormal signal transmission.

[0093] According to an embodiment of the present application, in response to an affirmative response signal from the control module, it is confirmed that the sub-test result of the slot self-test is that the slot is normal.

[0094] When the slot status of the memory slot to be tested is normal, when the baseboard management controller or the processor receives the handshake signal sent by the microcontroller, it will generate an affirmative response signal corresponding to the handshake signal and send it to the microcontroller, thereby indicating that the slot status of the current memory slot to be tested is normal. When the slot status of the memory slot to be tested is abnormal, the baseboard management controller or the processor may not be able to receive the handshake signal, and thus may not be able to generate and send an affirmative response signal to the microcontroller, or, an abnormality occurs in the integrated circuit bus, resulting in a change in the affirmative response signal generated by the baseboard management controller or the processor, and the microcontroller receives an abnormal response signal, thereby indicating that the slot status of the current memory slot to be tested is abnormal.

[0095] According to an embodiment of the present application, the slot self-check sub-test results and the positive response signal are packaged to obtain and send test self-check information to the memory slot self-check sub-module.

[0096] After receiving the test self-check information, the memory slot self-check sub-module backs up and saves the test self-check information, so as to facilitate retrieving the slot self-check results of the memory slot to be tested at any time for detection and analysis.

[0097] According to an embodiment of the present application, when it is necessary to detect and analyze the slot status of the memory slot to be tested, the microcontroller can autonomously send a handshake signal to the control module. When the baseboard management controller or the processor receives the handshake signal, it will generate a positive response signal corresponding to the handshake signal and send it to the microcontroller. When the microcontroller receives the positive response signal, it can confirm that the slot self-check sub-test result of the current memory slot to be tested is normal for the slot. If the microcontroller fails to receive any response signal or receives an abnormal response signal, it can confirm that the slot self-check sub-test result of the current memory slot to be tested is abnormal for the slot, thereby realizing the slot self-check of the memory slot to be tested, so as to facilitate timely repair of the memory slot to be tested. At the same time, the slot self-check sub-test results and the positive response signal are stored in the memory slot self-check sub-module, so as to facilitate retrieving the historical self-check records and information at any time, thereby performing primary or secondary adjustment on the memory slot to be installed, the memory slot to be tested that has been installed, or the memory slot after detection, and improving the efficiency of detection and maintenance.

[0098] According to the slot self-check sub-test results, it is also possible to cooperate with multiple warning lights in the warning module to perform detection reminder operations. For example, when the slot self-check sub-test result is abnormal for the slot, control the red warning light to flash ten times at a frequency of 1 second interval. When the slot self-check sub-test result is normal for the slot, control the green warning light to flash ten times at a frequency of 1 second interval.

[0099] According to an embodiment of the present application, the microcontroller is further configured to send a log data collection instruction to the control module.

[0100] When it is necessary to detect whether the log data of the baseboard management controller or the processor is correct, the microcontroller can actively send a log data collection instruction to the baseboard management controller or the processor, so as to facilitate detecting the log data.

[0101] According to an embodiment of the present application, in response to the log data from the control module, a fault diagnosis is performed on the log data to obtain a log fault test sub-result.

[0102] After receiving the log data collection instruction, the baseboard management controller or processor can send the log data including the detected temperature, whether the module voltage is stable, whether each module on the motherboard under test is in place, whether the memory is lost, the external devices such as the hard disk, network card speed, and bandwidth information to the microcontroller. The microcontroller performs data fault keyword retrieval or typo detection based on the received log data, so as to obtain the log fault test sub-result according to the detection result.

[0103] According to an embodiment of the present application, the log data and the log fault test sub-result are packaged to obtain and send a test log data packet to the log storage sub-module.

[0104] After receiving the log data and the log fault test sub-result, the log storage sub-module backs up and saves the log data and the log fault test sub-result for easy retrieval of the log data and the log fault test sub-result for detection and analysis at any time. At the same time, the log data and the log fault test sub-result can also be backed up and stored in the first memory.

[0105] According to an embodiment of the present application, in the case where it is necessary to detect and analyze the log data, the microcontroller can be used to send a log data collection instruction to the baseboard management controller or processor. The baseboard management controller or processor sends the log data to the microcontroller according to the received log data collection instruction. The microcontroller performs fault detection on the received log data and stores the detection result in the log storage sub-module, realizing self-checking of the log data, so as to timely confirm the fault of the log data, thereby maintaining the baseboard management controller or processor.

[0106] According to the log fault test sub-result, multiple warning lights in the warning module can also be used for detection reminder operations. For example, when the log fault test sub-result is that there is faulty log data, control the red warning light to flash ten times at a frequency of 0.5 s interval, and according to different fault abnormal situations, control the red warning light to flash at different frequencies. When the log fault test sub-result is that there is no faulty log data, control the green warning light to flash ten times at a frequency of 0.5 s interval. Through warning lights of different colors and different frequencies, the current test result and test process can be quickly prompted.

[0107] Figure 4 The schematic diagram of a test device according to another embodiment of the present application is shown.

[0108] As Figure 4As shown, the test device includes a test board 101, a DIP memory module 102, a function detection module 103, a plurality of signal extraction test points 104, a warning module 401, an information interface 402, and a plurality of test gold finger pins 403. The DIP memory module 102 includes three DIP switches 201 and a first memory 202. The function detection module 103 includes a voltage acquisition unit 301, a current acquisition unit 302, a microcontroller 303, a memory slot self-check sub-module 304, and a log storage sub-module 305. The plurality of signal extraction test points 104 includes a first data signal extraction test point 404, a second data signal extraction test point 405, and an electrical signal extraction test point 406.

[0109] Figure 5 The flowchart of the test method according to an embodiment of the present application is shown.

[0110] As Figure 5 shown, the test method of this embodiment includes operations S510 to S540.

[0111] In operation S510, when the test board is inserted into the memory slot to be tested on the main board to be tested, based on a predetermined memory address, the DIP switches in the DIP memory module are controlled to configure the test memory address of the first memory.

[0112] In operation S520, in response to the control module performing read and write operations on the first memory through the integrated circuit bus, the test data signal is obtained and transmitted to the plurality of signal extraction test points.

[0113] In operation S530, the function detection module is used to collect the test electrical signal from the power supply module of the main board to be tested, the response signal from the control module of the main board to be tested, and the log data. The function detection module tests the test electrical signal, the response signal, and the log data to obtain the function test result.

[0114] In operation S540, the test electrical signal is transmitted to the plurality of signal extraction test points so that the external detection device can obtain the signal test result based on the test data signal and the test electrical signal.

[0115] According to an embodiment of the present application, when the test board is inserted into the memory slot under test of the main board under test, by controlling a plurality of DIP switches in the DIP memory module based on a predetermined memory address to configure the test memory address of the first memory, so that the test memory address of the first memory is the same as the predetermined memory address, the initialization configuration of the first memory is completed. Then, in response to the control module performing read and write operations on the first memory through the integrated circuit bus to obtain a test data signal, the function detection module is used to collect the test electrical signal from the power supply module of the main board under test. By electrically connecting an external detection device to a plurality of signal extraction test points, the test data signal and the test electrical signal are led out to the external detection device, so that the monitoring result of the transmission quality of the data signal of the memory slot under test can be obtained. And because the test data signal and the test electrical signal are led out to a position far from the test board inserted into the memory slot under test, it is convenient for the external detection device to perform detection, so that even when multiple memory slots under test are detected simultaneously, the test data signals and test electrical signals of multiple memory slots under test can be obtained simultaneously. Then, the microcontroller performs corresponding tests based on the collected test electrical signals, response signals, and log data to obtain the function test result, thereby improving the detection efficiency, and further enabling the detection of a batch of memory slots and main boards under test.

[0116] Figure 6 The flowchart of the power consumption test according to an embodiment of the present application is shown.

[0117] As Figure 6As shown, the voltage acquisition unit and the current acquisition unit are used to acquire a test voltage signal and a test current signal S601 respectively, and transmit the acquired test voltage signal and test current signal to the microcontroller S602. The microcontroller performs a multiplication process on the test voltage signal and the test current signal to obtain an instantaneous test power consumption value S603, and determines whether the instantaneous test power consumption value is greater than or equal to a first power consumption threshold S604. When the instantaneous test power consumption value is greater than or equal to the first power consumption threshold, it is determined that the test information on the instantaneous power consumption state can be an instantaneous high power consumption state and the red warning light of the warning module is constantly on S605. When the instantaneous test power consumption value is less than the first power consumption threshold, it is determined that the test information on the instantaneous power consumption state can be an instantaneous normal power consumption state and the green warning light of the warning module is constantly on S606. The instantaneous test power consumption value and the test information on the instantaneous power consumption state are stored in the first memory for easy retrieval S607. Moreover, the microcontroller can also obtain the signal acquisition period during the acquisition of the test voltage signal and the test current signal, perform an integration process on the test voltage signal, the test current signal and the signal acquisition period to obtain a total test power consumption value S608, and determine whether the total test power consumption value is greater than or equal to a second power consumption threshold S609. When the total test power consumption value is greater than or equal to the second power consumption threshold, it is determined that the test information on the operating state can be a full load working state and the red warning light of the warning module is turned on S610. When the total test power consumption value is less than the second power consumption threshold, it is determined that the test information on the operating state can be a normal working state and the green warning light of the warning module is constantly turned on S611. At the same time, a total test power consumption value curve can also be drawn according to the result of the integration process, and the total test power consumption value and the test information on the operating state are stored in the first memory for easy retrieval S612.

[0118] Figure 7 The flowchart of the memory slot detection according to the embodiment of the present application is shown.

[0119] As Figure 7As shown, the microcontroller sends a handshake signal S701 to the control module, determines whether the communication is successful S702. When the slot status of the memory slot to be tested is normal, after receiving the handshake signal, the control module generates and sends an affirmative response signal to the microcontroller, so that the microcontroller can obtain the slot self-test sub-test result according to the received signal. When the slot self-test sub-test result is normal self-test, the green warning light of the warning module can be constantly turned on S703. When the slot status of the memory slot to be tested is abnormal, the baseboard management controller or the processor may not be able to receive the handshake signal, and thus may not be able to generate and send an affirmative response signal to the microcontroller. Or, the integrated circuit bus is abnormal, resulting in a change in the affirmative response signal generated by the baseboard management controller or the processor. The microcontroller receives the abnormal response signal, so that the microcontroller can obtain the slot self-test sub-test result according to the received signal. When the slot self-test sub-test result is abnormal self-test, the red warning light of the warning module can be constantly turned on S704.

[0120] Figure 8 The flowchart of log detection according to an embodiment of the present application is shown.

[0121] As Figure 8 shown, the microcontroller sends a log data collection instruction to the control module. When the control module receives the log data collection instruction, it sends log data to the microcontroller S801. The microcontroller performs a data fault keyword search or spelling error detection on the log data to determine whether there are data fault keywords or spelling errors in the log data S802. When there is a fault anomaly, the red warning light of the warning module can be constantly turned on, and according to the preset fault anomaly result, the red warning light flashes at a predetermined flashing frequency S803. When there is no fault anomaly, the green warning light of the warning module can be constantly turned on S804.

[0122] According to the embodiments of the present application, the program code for executing the computer program provided by the embodiments of the present application can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedures and / or object-oriented programming languages, and / or assembly / machine languages. The programming languages include, but are not limited to, programming languages such as Java, C++, Python, "C" language or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, by using an Internet service provider to connect through the Internet).

[0123] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code, and the above-mentioned module, segment of a program, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0124] Those skilled in the art can understand that the features described in various embodiments of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present application. In particular, without departing from the spirit and teachings of the present application, the features described in various embodiments of the present application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present application.

[0125] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present application.

Claims

1. A test device, characterized in that, The device includes: A test board, which, when inserted into a memory slot under test on a main board under test, simulates a memory unit inserted into the memory slot under test to transmit a test data signal and a test electrical signal; A DIP memory module, arranged on the test board, includes a DIP switch and a first memory, and is used to control the DIP switch to configure the test memory address of the first memory based on a predetermined memory address, so that a control module of the main board under test performs read and write operations on the first memory through an integrated circuit bus to obtain the test data signal; A function detection module, arranged on the test board, is used to collect a test electrical signal from a power supply module of the main board under test, a response signal and log data from the control module, and test the test electrical signal, the response signal and the log data to obtain a function test result; A plurality of signal extraction test points, arranged on a side of the test board away from the memory slot under test, are used to extract the test data signal and the test electrical signal to an external detection device, so that the external detection device obtains a signal test result according to the test data signal and the test electrical signal.

2. The device according to claim 1, wherein The first memory is further used for: When the predetermined memory address is the same as the test memory address, in response to the control module performing a write operation on the first memory through the integrated circuit bus, obtaining a test data signal and performing backup processing on the test data signal, so as to read the test data signal when a test device is connected to a plurality of the signal extraction test points.

3. The device according to claim 1, characterized in that The function test result includes a power consumption test sub-result, a slot self-detection test sub-result and a log fault test sub-result. The function detection module includes: An electrical signal acquisition sub-module, electrically connected to a microcontroller, is used to collect and transmit the test electrical signal and signal acquisition time information to the microcontroller, wherein the test electrical signal includes a test voltage signal and a test current signal; The microcontroller is used to, in response to receiving the test electrical signal and the signal acquisition time information, perform a power consumption test on the test electrical signal to obtain the power consumption test sub-result; obtain the response signal and the log data, and respectively test the response signal and the log data to obtain the slot self-detection test sub-result and the log fault test sub-result; A memory slot self-detection sub-module, electrically connected to the microcontroller, is used to store the slot self-detection test sub-result; A log storage sub-module, electrically connected to the microcontroller, is used to store the log fault test sub-result.

4. The device according to claim 3, characterized in that, The log fault test sub-result includes power consumption instantaneous state test information and operation state test information; the microcontroller is further used for: Obtaining the power consumption instantaneous state test information according to a test power consumption instantaneous value and a first power consumption threshold obtained based on the test voltage signal and the test current signal; Obtaining the operation state test information of the control module according to a test power consumption total value and a second power consumption threshold obtained based on the test voltage signal, the test current signal and a signal acquisition period.

5. The device according to claim 3, characterized in that, The microcontroller is further used for: Send a handshake signal to the control module via the integrated circuit bus; In response to the positive acknowledgment signal from the control module, confirm that the sub-test result of the slot self-test is normal for the slot; Package the sub-test result of the slot self-test and the positive acknowledgment signal, and obtain and send test self-check information to the memory slot self-test sub-module.

6. The device according to claim 3, characterized in that The microcontroller is further configured to: Send a log data collection instruction to the control module; In response to the log data from the control module, perform fault diagnosis on the log data to obtain the sub-result of the log fault test; Package the log data and the sub-result of the log fault test, and obtain and send a test log data packet to the log storage sub-module.

7. The device according to claim 1, characterized in that, The control module includes a management controller and a processor, and the multiple signal extraction test points include: A first data signal extraction test point for extracting a first test data signal sent from the management controller to the external detection device; A second data signal extraction test point for extracting a second test data signal sent from the processor to the external detection device; An electrical signal extraction test point for extracting the test electrical signal to the external detection device.

8. The device according to claim 1, characterized in that, The device further includes: A warning module disposed on the test board for generating a warning identifier according to the function test result; An information interface disposed on a side of the test board away from the memory slot under test for connecting to the external detection device so that the function test result is transmitted to the external detection device.

9. The device according to claim 1, characterized in that The device further includes: Multiple test gold finger pins disposed on the test board for electrically connecting to the memory slot under test when the test board is inserted into the memory slot under test, so that the test data signal and the test electrical signal are transmitted onto the test board.

10. A testing method, applied to the testing device according to any one of claims 1-9, characterized in that The method includes: When the test board is inserted into the memory slot under test of the main board under test, based on a predetermined memory address, control the DIP switches in the DIP memory module to configure the test memory address of the first memory; In response to the control module performing read and write operations on the first memory via the integrated circuit bus, obtain and transmit a test data signal to multiple signal extraction test points; Use the function detection module to collect the test electrical signal from the power supply module of the main board under test, the acknowledgment signal and the log data from the control module of the main board under test, and use the function detection module to test the test electrical signal, the acknowledgment signal and the log data to obtain a function test result; Transmit the test electrical signal to multiple signal extraction test points so that the external detection device obtains a signal test result based on the test data signal and the test electrical signal.

Images