Storage controller control unit and mapping table management method

Abstract

The invention discloses a storage controller control unit and a mapping table management method, and belongs to the technical field of storage controllers. A to-be-updated mapping table is temporarily stored in a static random access memory and is updated to a dynamic random access memory from a hardware IP (Internet Protocol) after being reasonably sorted; therefore, the central processing unit is prevented from updating the dynamic random access memory of scattered small bytes, and the access operation of the dynamic random access memory is more continuous and efficient. Practical tests show that in a typical storage application scene, the running efficiency of the central processing unit can be improved by more than 40%, the data read-write speed is greatly increased, and the storage controller control unit undertakes the updating work of most mapping tables and reverse mapping tables, so that the central processing unit can concentrate on the combined processing of receiving host commands and internal commands, and the data read-write efficiency is greatly improved. And the time consumption of the central processing unit on mapping table operation is reduced. Experimental data show that the load of the central processing unit can be reduced by about 30% when the central processing unit processes and stores related tasks, and the overall response speed of the system is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of storage controllers, and more specifically, to a storage controller control unit and a mapping table management method. Background Art

[0002] With the rapid development of in-vehicle electronics, smartphones, and various computers, consumers' demand for storage media is also increasing rapidly. Since the rewritable non-volatile memory module has the characteristics of data non-volatility, low power consumption, small size, and no mechanical structure, it is suitable for being embedded in various portable multimedia devices exemplified above, such as SD cards, solid-state drives, etc. Such an embedded multimedia device usually has a dynamic random access memory and a static random access memory inside. When performing a data read operation on the rewritable non-volatile memory module, the central processing unit in the storage controller usually needs to read the first-level mapping table from the dynamic random access memory, and then perform a data read operation on the rewritable non-volatile memory module according to the mapping relationship corresponding to the mapping table in the dynamic random access memory. For data access operations, the central processing unit needs to allocate physical storage units for access instructions, thereby generating a new mapping table and a reverse mapping table. The newly generated mapping table and reverse mapping table will be preferentially updated to the dynamic random access memory by the central processing unit, and then the first-level mapping table, second-level mapping table, and third-level mapping table in the dynamic random access memory will be updated to the rewritable non-volatile memory module through each snapshot of the storage controller, and the mapping relationship can be restored after Power Down.

[0003] The storage controller notifies the central processing unit to read and update the required mapping tables in the dynamic random access memory one by one according to the operation instruction set sent by the host. However, if the operation instruction set sent by the host requires frequent and discrete access to the dynamic random access memory, it will cause a great burden on the central processing unit built in the storage controller. In addition, since the central processing unit needs to read and update the mapping table and the reverse mapping table for each data read or access operation, it will cause the originally possibly continuously updated mapping table and reverse mapping table to become random dynamic random access memory operations of a few bytes per single pen, thereby reducing the operating efficiency of the dynamic random access memory. [[ID=?]] [[ID=?]]

[0004] Therefore, it is necessary to invent a storage controller control unit and a mapping table management method to solve the above problems. Summary of the Invention

[0005] To overcome the above-mentioned deficiencies of the prior art, the present invention provides a storage controller control unit and a mapping table management method to solve the problem that, as described in the above background art, since the central processing unit needs to read and update the mapping table and the reverse mapping table for each data read or access operation, the originally possibly continuously updated mapping table and reverse mapping table will become random dynamic random access memory operations of a few bytes per single pen, thereby reducing the operating efficiency of the dynamic random access memory.

[0006] To achieve the above object, the present invention provides the following technical solutions: A storage controller control unit and a mapping table management method, including a mapping table update method for a rewritable non-volatile memory module, which receives a plurality of operation instructions from a host, the operation instructions can span multiple mapping tables, and the central processing unit splits them into sub-operation instructions, and the sub-operation instructions are aligned with the smallest unit of the first-level mapping table mapping relationship;

[0007] As a further description of the above technical solution, the mapping table update method further includes storing the mapping table to be updated in the internal static random access memory of the storage controller, performing a sorting operation on the logical address units, and updating the mapping table in the dynamic random access memory with a continuous access sequence of logical address units;

[0008] As a further description of the above technical solution, in the mapping table update method, after the reverse mapping table accumulates to a certain number in the static random access memory, it is continuously updated to the dynamic random access memory;

[0009] As a further description of the above technical solution, the storage controller control unit is an independent hardware circuit embedded in the multimedia device, receives a plurality of operation instructions from the host, disassembles the instructions, calculates and generates a new mapping relationship and transmits it to the central processing unit;

[0010] As a further description of the above technical solution, the storage controller control unit includes two sub-storage modules. One sub-storage module sorts the logical unit addresses of the sub-operation instructions generated by the operation instructions, combines and temporarily stores the mapping relationship, and then efficiently updates it to the dynamic random access memory;

[0011] As a further description of the above technical solution, the other sub-storage module of the storage controller control unit continuously updates the reverse mapping table of the sub-operation instructions generated by the operation instructions to the static random access memory, and after accumulation, transmits it to the dynamic random access memory;

[0012] As a further description of the above technical solution, the storage controller control unit and the central processing unit perform parallel processing. The storage controller control unit is responsible for updating the mapping table and the reverse mapping table, and the central processing unit is responsible for receiving the command sequence from the host, processing and combining the commands inside the storage controller and sending them to the rewritable non-volatile memory module;

[0013] As a further description of the above technical solution, the operation instructions include, but are not limited to, instructions related to data storage, reading, and erasing, etc., and the number of sub-operation instructions corresponding to each operation instruction is determined according to the instruction complexity and the minimum unit of mapping table management;

[0014] As a further description of the above technical solution, during the process of the storage controller control unit processing the mapping table update, the sorting of the logical address units follows a specific sorting algorithm to ensure that the updated mapping table after sorting can improve the access efficiency of the dynamic random access memory.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0016] 1. By temporarily storing the mapping table to be updated in the static random access memory and updating it to the dynamic random access memory after reasonable sorting, the present invention avoids scattered small-byte update operations, making the access operations of the dynamic random access memory more continuous and efficient. Through actual tests, in typical storage application scenarios, the access efficiency of the dynamic random access memory can be increased by more than 40%, greatly accelerating the data reading and writing speed. The storage controller control unit undertakes most of the update work of the mapping table and the reverse mapping table, enabling the central processing unit to focus on receiving host commands and combined internal command processing, reducing the time consumption of the central processing unit in mapping table operations. Experimental data shows that the load of the central processing unit in processing storage-related tasks can be reduced by about 30%, improving the overall system response speed.

[0017] 2. The method of the present invention ensures the rationality and efficiency of the mapping table update, reduces resource waste and performance loss caused by frequent updates, enables the mapping table management to reach a better state, further improves the stability and reliability of the storage system, reduces the probability of data storage errors, and extends the service life of the storage device. The storage system has significant improvements in aspects such as data reading and writing, processing speed, and stability, and can meet scenarios with higher performance requirements in actual applications, such as big data storage and high-speed data transmission, enhancing the market competitiveness of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0019] Figure 1 is a host system and a host system interface device shown according to the present invention.

[0020] Figure 2It is a schematic diagram of a host system interface drive unit, a storage controller control circuit unit, and a rewritable non-volatile memory module shown according to the present invention.

[0021] Figure 3 It is a schematic diagram of a storage controller device shown according to the present invention.

[0022] Figure 4 It is a schematic diagram of a rewritable non-volatile memory module shown according to the present invention.

[0023] Figure 5 It is a schematic diagram of a logical address mapping relationship shown according to the present invention.

[0024] Figure 6 It is a schematic diagram of the update of a logical address mapping table shown according to the present invention.

[0025] Figure 7 It is a schematic diagram of the operation of a Thanslayer Unit module shown according to the present invention.

[0026] Figure 8 It is a schematic diagram of the operation of a Logical2Pysical Array module shown according to the present invention.

[0027] Figure 9 It is a schematic diagram of a Pysical2Logical Array module shown according to the present invention.

[0028] Figure 10 It is a schematic diagram of a Table Manage Unit module shown according to the present invention.

[0029] Figure 11 It is a flowchart of the operation of a memory control circuit unit shown according to the present invention. Detailed implementation manners

[0030] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application is provided in conjunction with the accompanying drawings and specific implementation manners.

[0032] As Figure 1-2 shown, the host system 10 is connected toFigure 2 A storage interface unit 201 is provided, and the host system and the storage controller device are connected and communicate through an interface protocol. The interface protocol of the present invention includes, but is not limited to, conforming to the Peripheral Component Interconnect Express (PCIE) standard, Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, or other suitable standards. For example, the host system of the current mainstream desktop computer is connected to a PCIE interface solid-state storage hard disk through the PCIE standard protocol or to a SATA interface solid-state storage hard disk through the SATA standard protocol. In addition, the host system 10 shown in the present invention generally may include, but is not limited to, various host systems such as mobile phones, in-vehicle electronics, computers, cameras, smart watches, audio and video devices, etc. It should be noted that the host system 10 mentioned in this embodiment can be any system that can substantially communicate with the storage controller device and store or read data.

[0033] After the host system and the storage controller device establish communication and the handshake is successful, the host side sends data I / O that needs to be stored or read by sending a data packet conforming to the protocol standard through Figure 2 the storage controller control circuit unit 202 shown stores the data into the rewritable non-volatile storage array or reads the stored data from the rewritable non-volatile storage array.

[0034] As Figure 3 shown, after the host system and the storage controller device establish communication and the handshake is successful, the data I / O that needs to be stored or read by the host side by sending a data packet conforming to the protocol standard will pass through Figure 3 the host interface controller 301 shown inside the storage controller device. For details, please refer to what is shown in the present invention Figure 3, the central processing unit (CPU) 308 reasonably schedules the data received by the system data bus 309, and temporarily stores the data in the static random access memory (SRAM) 302 and / or the dynamic random access memory (DRAM) 303 first. Due to the relatively fast access or read rate, usually such an embedded multimedia device requires multiple central processing units (CPUs) 308 to accelerate the operation.

[0035] As Figure 3 shown, due to the rate mismatch of the static random access memory (SRAM) 302, the dynamic random access memory (DRAM) 303, the host interface protocol, and the rewritable non-volatile memory module, the cache controller 306 needs to perform internal scheduling on the static random access memory (SRAM) 302 and / or the dynamic random access memory (DRAM) 303 to ensure the optimal efficiency of data transmission to the storage controller device and the rational allocation of the cache. Usually, in the present invention, the mapping table is stored in the dynamic random access memory (DRAM) 303 with the logical address as the index. Such an embedded multimedia device usually also configures a power management circuit 307 (Power Manage Unit, PMU), which is connected to the inside of the storage controller device and is a circuit module used to control the storage controller device. Since it cannot work after power-off, in addition to providing sufficient voltage and current for the operation of the storage controller device, it also includes a power management IC (Power Manage IC), which plays an important role in power loss protection (Power Loss Protect, PLP). It should be noted that the stored data is recorded by injecting and releasing electron pairs of triodes. As the degree of particle loss increases, the probability of electron escape also increases, which in turn causes the stored data to jump. In view of this, the error correction engine 304 needs to cooperate with the storage controller device to perform error detection and correction on the data. For example, the currently mainstream low-density parity check code (Low Density Parity Check Code, LDPC). When the host system 10 sends a data I / O instruction that needs to be stored or read by sending a data packet that conforms to the protocol standard, the error correction engine 304 calculates a section of low-density parity check code based on the original data, and the storage controller device will write the data corresponding to this write instruction and the corresponding low-density parity check code into the rewritable non-volatile storage array together. When the storage controller device reads data from the rewritable non-volatile storage array later, it will read the low-density parity check code corresponding to this data at the same time, and the error correction engine 304 will perform error checking and correction operations on the read data according to the low-density parity check code.

[0036] As Figure 4 shown, the rewritable non-volatile memory module includes a memory interface 401 and a rewritable non-volatile storage array circuit 402. As shown in the present inventionFigure 3 The 305 flash memory controller in Figure 4 is connected to the 401 memory interface device in Figure 4 After processing the data sent by the host system 10, the storage controller device sends specific operation instructions for each type of memory cell through the memory interface 401, and actually stores the data into the rewritable non-volatile storage array circuit 402 or reads the data from the rewritable non-volatile storage array circuit 402. The rewritable non-volatile storage array circuit 402 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which 1 bit can be stored in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which 2 bits can be stored in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which 3 bits can be stored in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which 4 bits can be stored in one memory cell), other flash memory modules or other memory modules with the same characteristics. As shown in the present invention

[0037]

[0038] Storing data into the rewritable non-volatile storage array circuit 402 is called programming, reading data from the rewritable non-volatile storage array circuit 402 is called reading, and erasing data from the rewritable non-volatile storage array circuit 402 is called erasing. Specifically, the memory cells on the same word line can form one or more physical programming units. For a TLC NAND flash memory, each memory cell can store 3 bits, so the physical programming units on the same word line can be at least classified into a lower physical programming unit, a central physical programming unit, and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, the central significant bit (MSB) of a memory cell belongs to the central physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Such 3 physical pages are called WL (WordLine).The smallest entity unit stored or read by the host system 10 is usually an entity page (usually 16 KByte) or an entity sector (usually 512 Byte, also known as LBA, Logical Block Address), etc. For example, if the host system needs to store 32 entity sectors, the entity units programmed into the rewritable non-volatile storage array circuit 402 may include a data bit area and a redundancy bit area. The data bit area is the size of 32 entity sectors to be stored, used to store user data, and the redundancy bit area is used to store system data (such as low-density parity-check codes, etc.). In addition, the entity erase unit is the smallest unit of erasure. That is, the smallest area of the storage unit erased together with each entity erase unit is an entity block.

[0039] As Figure 5 shown, the figure is a schematic diagram of the storage controller device managing the mapping relationship of the rewritable non-volatile memory module. The host system 10 accesses logical addresses 0 to N, and the rewritable non-volatile memory module is divided into three areas. The first area is the system area, the second area is the mapping table area (Table), and the third area is the data area (Data). Among them, the data area corresponds to the physical address range of 0 to M. Usually, the physical address range of 0 to M is greater than the logical address range of 0 to N, and the part of M - N is called OP (Over-Provision). Additionally, it is worth noting that each physical address within the physical address range of 0 to M can map a logical address unit at the same time. For example, the host system 10 first stores an entity page with a logical address of z, and the corresponding actual physical address unit is x. At this time, the logical address z is mapped to the actual physical address unit x. Subsequently, the host system 10 modifies the data of this entity page, so the data with the logical address of z corresponding to the entity page is stored, and the corresponding actual physical address unit is y. The data in the original actual physical address x is invalidated, and the actual physical address y becomes valid. Due to the characteristics of the storage medium (it needs to be erased before storage), the entity unit block cannot be erased immediately because there is still other valid data in the entity unit block. At this time, the existence of a uniquely corresponding valid mapping table is required, so an area is allocated in the dynamic random access memory to store the mapping table.

[0040] As Figure 6As shown, after the host system establishes communication with the storage controller device and the handshake is successful, the host side sends data I / O that needs to be stored or read by sending data packets that conform to the protocol standard, including Command0, Command1, Command2, and Command3 shown in the legend of the present invention. The corresponding logical address sequences to be stored are LBA(a)-LBA(b), LBA(c)-LBA(d), LBA(e)-LBA(f), and LBA(g)-LBA(h) respectively. The mapping relationship corresponding to LBA(a)-LBA(b) exists in Table(x), and the mapping relationship corresponding to LBA(c)-LBA(d) exists in Table(y). The table is a table with logical addresses as indexes and physical storage units as contents. The table records the unique mapping relationship from logical addresses to physical storage units. If the host system 10 writes data into the rewritable non-volatile memory module, the physical storage unit will be recorded in the table. If the host system 10 wants to read this data, it needs to find the corresponding physical storage unit in the table by using the logical address as an index.

[0041] For the storage controller device without an imported memory control circuit unit, after receiving Command0 sent by the host system 10, the central processing unit disassembles the information of LBA(a)-LBA(b) into LBA(a), LBA(a + 1), LBA(a + 2), …, LBA(b). Then, the central processing unit assigns the physical storage unit address PBA(m) (Physical Block Address) to the logical address unit LBA(a), thereby forming the first storage mapping relationship. The central processing unit updates this pair of storage mapping relationships to the dynamic random access memory and updates the formed first reverse mapping table to another dynamic random access memory area. Then, according to the current data state (such as whether the TLC Program is complete in terms of WL), the central processing unit transmits the data and instructions to the 305 flash controller shown in the present invention. Figure 3 Next, the central processing unit assigns the physical storage unit address PBA(m + 1) to the logical address unit LBA(a + 1), thereby forming the second storage mapping relationship. The central processing unit updates this pair of storage mapping relationships to the dynamic random access memory and also updates the formed second reverse mapping table to another dynamic random access memory area. According to the current data state (such as whether the TLC Program is complete in terms of WL), the central processing unit transmits the data and instructions to the 305 flash controller shown in the present invention. Figure 3In the 305 flash memory controller. Similarly, the CPU finally allocates the physical storage unit address PBA(m+ba) to the logical address unit LBA(b), thereby forming the ba-th storage mapping relationship. The CPU updates this pair of storage mapping relationships to the dynamic random access memory, and also updates the formed ba-th reverse mapping table to another dynamic random access memory area. The CPU transfers data and instructions to the WL shown in the present invention according to the current data status (such as whether the TLC Program is complete). Figure 3 In the flash memory controller 305 in the CPU, during the processing of Command0, the physical page of the WL is sent to the subsequent Figure 3 The data is then written to the rewritable non-volatile memory array circuit 402 by the flash memory controller 305. At this point, Command 0 is considered fully executed. The CPU then begins processing Command 1, Command 2, and Command 3 in sequence according to the aforementioned logic, assigning physical storage unit addresses PBA(n), PBA(n+1), PBA(n+2), PBA(n+dc)… to Command 1, PBA(p), PBA(p+1), PBA(p+2), PBA(p+fe)… to Command 2, and PBA(q), PBA(q+1), PBA(q+2), PBA(q+hg)… to Command 3. All mapping and reverse mapping relationships generated during the process are inserted into the dynamic random access memory. It is worth noting that the CPU needs to generate a mapping table and reverse mapping table for each command, so it needs to process each LBA in a loop.

[0042] The storage controller device with a memory control circuit unit, after receiving Command0 sent by the host system 10, the memory control circuit unit provided by the present invention will disassemble the information of LBA(a)-LBA(b) into LBA(a), LBA(a + 1), LBA(a + 2), …, LBA(b) before the command enters the central processing unit. Then, the memory control circuit unit provided by the present invention assigns the physical storage unit address PBAm (Physical Block Address) to the logical address unit LBA(a), thereby forming the first storage mapping relationship, assigns the physical storage unit address PBA(m + 1) to the logical address unit LBA(a + 1), thereby forming the second storage mapping relationship, and so on, until the physical storage unit address PBA(m + b - a) is assigned to the logical address unit LBA(b), thereby forming the (b - a)-th storage mapping relationship. The memory control circuit unit provided by the present invention returns the disassembled command sequence and the newly generated mapping relationship to the central processing unit. The central processing unit directly obtains the current data status according to the total number of logical address units, divides the data into several TLC Program WLs, and the central processing unit transmits the data and instructions to the 305 flash memory controller shown in the present invention Figure 3 At the same time, when the central processing unit analyzes the data status and sends instructions, the memory control circuit unit provided by the present invention updates the assigned storage mapping relationship and storage reverse mapping relationship to the dynamic random access memory.

[0043] The memory control circuit unit consists of four structures. The first structure is the Translayer Unit module, the second structure is the Logical2Pysical Array module, the third structure is the Pysical 2Logical Array module, and the fourth structure is the Table Manage Unit module. The implementation principle of the memory control circuit unit provided by the present invention is that the Translayer Unit module receives the command sequence signal information from the central processing unit, assigns the physical storage unit address to the logical address in the command sequence signal, then the Translayer Unit module informs the central processing unit of the generated mapping information after disassembling, and finally the Translayer Unit module transmits the generated mapping table and reverse mapping table to the Logical 2Pysical Array module and the Pysical2Logical Array module respectively. Among them, the Pysical 2Logical Array module generates a reverse mapping table composed of logical address units sorted according to the physical storage unit address according to the information of the Translayer Unit module. The Logical 2Pysical Array module sorts the internal mapping relationships according to the logical address information to generate a sequence of logical address unit and physical storage unit address mapping pairs. Then the Logical2Pysical Array module sorts the sequence of logical address unit and physical storage unit address mapping pairs level by level according to the logical address unit. Finally, the last-level sequence of logical address unit and physical storage unit address mapping pairs after sorting is notified to the Table ManageUnit. The Table Manage Unit combines the physical storage unit addresses corresponding to the consecutive logical address units and updates them to the dynamic random access memory together.

[0044] Such as Figure 7As shown, the central processing unit updates the relevant information of instructions Command0, Command1, Command2, and Command3 to the Translayer Unit module of the present invention. The internal register of the Translayer Unit module maintains the address of the physical storage unit to be written currently pointed to, and assigns the next physical storage unit address to each logical address. The Translayer Unit module then sends the generated mapping relationship back to the central processing unit, and then sends the mapping information to the Logical2Pysical Array module and the Pysical2Logical Array module. For example, the central processing unit sends the starting logical address LBA(a) of Command0 instruction and the length b - a of Command0 command to the Translayer Unit module of the present invention. After receiving the instruction sent by the central processing unit, the Translayer Unit module immediately starts to execute the splitting of Command0 command into LBA(a), LBA(a + 1), LBA(a + 2), …, LBA(b), and assigns the physical storage unit addresses PBA(m), PBA(m + 1), PBA(m + 2), …, PBA(m + b - a), and updates the pointer of the physical storage unit address to be written. Subsequently, the Translayer Unit module transmits the generated physical storage unit addresses to the central processing unit. After receiving the physical storage unit addresses returned by the Translayer Unit module, the central processing unit combines the physical storage unit addresses into the smallest granularity unit for storage or reading, such as writing as the above WordLine, and submits the command sequence of the combined smallest granularity unit for storage or reading to the flash memory controller 302. While the Translayer Unit module returns the instruction to the central processing unit and the central processing unit receives it, the Translayer Unit module transmits the mapping pairs generated by the logical address unit and the physical storage unit address (such as LBA(a)->PBA(m), LBA(a + 1)->PBA(m + 1)…) to the Logical 2Pysical Array. Finally, the logical address units sorted according to the physical storage unit addresses (such as LBA(a), LBA(a + 1), …) are transmitted to the Pysical2Logical Array. After the central processing unit transmits the instruction information to the memory control circuit unit provided by the present invention, it combines the split Command0 into the command sequence of the smallest granularity unit for storage or reading and submits it to the flash memory controller 302. After the central processing unit finishes processing, it continues to process the instructions Command1, Command2, and Command3 sent by the host system 10.The central processing unit separately sends the starting logical address LBA(c) of the Command1 instruction and the length d-c of the Command1 instruction, the starting logical address LBA(e) of the Command2 instruction and the length f-e of the Command2 command, and the starting logical address LBA(g) of the Command3 instruction and the length h-g of the Command3 command to the Translayer Unit module. The TranslayerUnit module splits the Command1 instruction into LBA(c), LBA(c+1), LBA(c+2), …, LBA(d), and assigns the physical entity storage unit addresses PBA(n), PBA(n+1), PBA(n+2), …, PBA(n+d-c), and updates the pointer of the physical entity storage unit address to be written. Subsequently, the Translayer Unit module transfers the generated physical entity storage unit addresses to the central processing unit. Then it splits the Command2 command into LBA(e), LBA(e+1), LBA(e+2), …, LBA(f), and assigns the physical entity storage unit addresses PBA(p), PBA(p+1), PBA(p+2), …, PBA(p+f-e), and updates the pointer of the physical entity storage unit address to be written. Subsequently, the Translayer Unit module transfers the generated physical entity storage unit addresses to the central processing unit. Finally, it splits the Command3 command into LBA(g), LBA(g+1), LBA(g+2), …, LBA(h), and assigns the physical entity storage unit addresses PBA(q), PBA(q+1), PBA(q+2), …, PBA(q+h-g), and updates the pointer of the physical entity storage unit address to be written. Subsequently, the Translayer Unit module transfers the generated physical entity storage unit addresses to the central processing unit. The central processing unit sequentially processes the commands obtained by splitting the Command1, Command2, and Command3 instructions and combines them into a command sequence of the smallest storage or reading granularity unit, and submits it to the flash memory controller 302.

[0045] Such as Figure 8As shown, since the Logical 2Pysical Array module needs to sort and combine logical address units, a static random access memory needs to be allocated inside the storage controller. According to the allocated size of the static random access memory, the logical address units are divided into K layers, where each layer contains M sub-units, and each sub-unit contains N logical address unit and physical storage unit address mapping pairs. Specifically, the Logical 2Pysical Array module receives the sequence of logical address unit and physical storage unit address mapping pairs transmitted by the Translayer Unit. Layer1 in the Logical2Pysical Array receives N logical address unit and physical storage unit address mapping pairs, then sorts and combines them into sub-units inside and transmits them to Layer2 to form the first sub-unit of Layer2. Layer1 continues to receive the sequence of logical address unit and physical storage unit address mapping pairs transmitted by the Translayer Unit, then sorts and combines them into sub-units inside and pushes them to Layer2 to form the second sub-unit of Layer2, until the sequence of logical address unit and physical storage unit address mapping pairs transmitted by the Translayer Unit fills all M sub-units in Layer2. After that, Layer2 pushes the M sorted sub-units to the first sub-unit of Layer3. And so on, until the Kth layer is filled, that is, a sequence of logical address unit and physical storage unit address mapping pairs sorted according to the logical address units is obtained. After the Kth layer is filled, the Logical 2Pysical Array module sends a command to update the dynamic random access memory to the Table Manage Unit, and the Table Manage Unit performs further update operations, while the remaining K - 1 layers continue to repeat the above operations. For example, in the present invention Figure 8As shown, the sorted sequence transmitted from the (K-1)th layer has been received in Layer K, and the Logical2Pysical Array module immediately sends an update instruction to the Translayer Unit module. At the same time, Layer 1 sorts the logical address units LBA(g)-LBA(g+n-1), and there already exists a sorted sub-unit of LBA(e)-LBA(e+n-1) transmitted from Layer 1 in Layer 2. After the logical address units LBA(g)-LBA(g+n-1) in Layer 1 are sorted, they will be transmitted to the second sub-unit of Layer 2, and then the Translayer Unit module continues to transmit the logical address unit and physical storage unit address mapping pairs to Layer 1. It should be noted that for the sequence of consecutive logical address unit and physical storage unit address mapping pairs known to the TranslayerUnit module, which are directly inserted into a certain Layer, the present invention does not make any restrictions and functional circuit units can be added according to requirements.

[0046] As Figure 9As shown, the Pysical 2Logical Array module records the reverse mapping table. The reverse mapping table is that the storage controller records the logical address unit corresponding to the physical storage unit address of each written page or sector data to obtain the mapping relationship during writing. Usually, the reverse mapping table and the data sent by the host system are stored in the rewritable non-volatile memory module together. When doing effective data recovery to a new block, the reverse mapping table is one of the criteria for determining effective data. If the reverse mapping table recorded in the rewritable non-volatile memory module is consistent with the mapping table in the current dynamic random access memory, it means the data has not been overwritten, and this data is called effective data. Moving the effective data in different blocks to a new block inside the storage controller is called garbage collection. The Pysical2LogicalArray module receives the sequence of logical address units arranged according to the physical storage unit address sent by the Translayer Unit module. The Pysical 2Logical Array module internally maintains two segments of static random access memory. After the first segment of static random access memory is filled, an update instruction is triggered to the dynamic random access memory. During the instruction response period, the second segment of static random access memory continues to receive the sequence of logical address units sent by the Translayer Unit, and vice versa. At a specific time node of the storage controller, such as when a block is about to be written full, the sequence of logical address units stored in the dynamic random access memory is stored in the rewritable non-volatile memory. The specific implementation of the Pysical2Logical Array module is shown in the following figure. The Translayer Unit module disassembles the command of Command0 into b-a LBAs, and the writing order is PBAm, PBAm+1, PBAm+2, …, PBAm+(b-a) in sequence according to the logical address sequence. Then the Translayer Unit module transmits LBA(a), LBA(a+1), LBA(a+2), …, LBA(b) to the Pysical2Logical Array module in sequence. As shown in Figure 9 of the present invention, the logical address sequence LBA(a)-LBA(a+x) of Command0 fills the first segment of static random access memory, and the Pysical2Logical Array module triggers to merge and write the logical address sequence to a fixed address in the dynamic random access memory. At this time, the subsequent LBAs inserted from the Translayer Unit module, such as LBA(a+x+1), LBA(a+x+2), …, are written into the second segment of static random access memory.

[0047] As Figure 10As shown, after the Table Manage Unit module receives the update instruction from the Logical 2Pysical Array module, it locks the Kth layer in the Logical 2Pysical Array module and prohibits the (K - 1)th layer from continuing to transmit the logical address unit and the entity storage unit address mapping pair sequence to the Kth layer. Subsequently, the Table Manage Unit module updates the logical address unit and the entity storage unit address mapping pair sequence in the Kth layer of the Logical 2Pysical Array module to the mapping table in the dynamic random access memory. The specific implementation of the Table Manage Unit module is shown in the following figure. In LayerK, since it is a sequence sorted according to the logical address unit, Z segments (Z = 1 -) of continuous data will be generated correspondingly. If the logical address unit sorting is all continuous, only the logical address unit and the entity storage unit address mapping pair sequence in LayerK need to be updated to the dynamic random access memory at one time. As shown in the illustration of the present invention, entity storage unit addresses such as PBA(m) are updated to Table(x), and entity storage unit addresses such as PBA(n) are updated to Table(y). This is an example of the update of two segments of continuous logical address units.

[0048] As shown in the accompanying drawings Figure 11 Each step in the above has been described in detail above and will not be elaborated here. It is worth noting that Figure 11 Each step in can be implemented as multiple circuit units, and the present invention does not limit this. In addition, the efficient mapping table update method shown in the present invention can be used in combination with the above memory control circuit units or used alone, and the present invention does not limit this.

[0049] In summary, the embedded multimedia device equipped with the efficient mapping table management method and the memory control unit circuit can improve the access efficiency of the dynamic random access memory and reduce the burden on the central processing unit. The processing efficiency of the embedded multimedia device equipped with the memory control circuit unit in the present invention can reach the effect of doubling the performance at most. In addition, there is also a significant improvement in the mapping table update method, which can optimize the management of the mapping table and further improve the performance of the embedded multimedia device.

[0050] Finally: The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A mapping table management method, characterized in that: Including a mapping table update method for a rewritable non-volatile memory module, which receives a plurality of operation instructions from a host. The operation instructions can span multiple mapping tables. The storage controller control unit splits the operation instructions into sub-operation instructions, and the sub-operation instructions are aligned with the smallest unit related to the mapping of the first-level mapping table.

2. The mapping table management method according to claim 1, wherein: The mapping table update method further includes accessing the mapping table to be updated into the static random access memory inside the storage controller, performing a sorting operation on the logical address units, and updating the mapping table in the dynamic random access memory with a continuous access sequence of the logical address units.

3. The mapping table management method according to claim 2, wherein: In the mapping table update method, after the reverse mapping table accumulates to a certain number in the static random access memory, it is continuously updated to the dynamic random access memory.

4. A storage controller control unit, characterized in that: The storage controller control unit is an independent hardware circuit embedded inside the multimedia device, receives a plurality of operation instructions from the host, disassembles the instructions, calculates and generates a new mapping relationship, and transmits it to the central processing unit.

5. The storage controller control unit according to claim 4, characterized in that: The storage controller control unit includes two sub-storage modules. One sub-storage module sorts the logical unit addresses of the sub-operation instructions generated by the operation instructions, combines and temporarily stores the mapping relationship, and then efficiently updates it to the dynamic random access memory.

6. The storage controller control unit according to claim 5, characterized in that: Another sub-storage module of the storage controller control unit continuously updates the reverse mapping table of the sub-operation instructions generated by the operation instructions to the static random access memory, and after accumulation, transmits it to the dynamic random access memory.

7. The storage controller control unit according to claim 6, wherein: The storage controller control unit processes in parallel with the central processing unit. The storage controller control unit is responsible for updating the mapping table and the reverse mapping table, and the central processing unit is responsible for receiving the command sequence from the host, processing and combining the commands inside the storage controller, and sending them to the rewritable non-volatile memory module.

8. The storage controller control unit according to claim 7, wherein: The operation instructions include, but are not limited to, data storage, read, and erase instructions, and the number of sub-operation instructions corresponding to each operation instruction is determined according to the instruction complexity and the smallest unit of mapping table management.

9. The storage controller control unit according to claim 7, wherein: During the process of processing the mapping table update, the storage controller control unit follows a specific sorting algorithm for sorting the logical address units to ensure that the updated mapping table after sorting can improve the access efficiency of the dynamic random access memory.

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