High-performance semi-physical simulation system IO data transmission method based on FPGA

Abstract

The invention relates to the technical field of real-time I / O (input / output) communication of a semi-physical simulation system, and discloses an FPGA (field programmable gate array)-based high-performance IO (input / output) data transmission method of the semi-physical simulation system, which is characterized in that the FPGA encapsulates acquired data into PCIE (peripheral component interface express) TLP (translation translation protocol) packets, and adds a sequence count value at the tail of the last TLP packet, so that a CPU (central processing unit) can judge whether the TLP packets arrive or not by polling whether the sequence count value increases by one or not; and then periodically and actively initiating a DMA write request to the CPU based on a self hardware clock, and meanwhile, directly writing the TLP packet into the last-stage cache of the CPU by adopting a double-buffer-area mechanism and combining a direct cache access technology. According to the high-performance semi-physical simulation system IO data transmission method based on the FPGA, the problems of operating system interference, interruption overhead and insufficient data consistency in traditional I / O communication are effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of real-time I / O communication in a hardware-in-the-loop simulation system, and particularly to a method for transmitting IO data in a high-performance hardware-in-the-loop simulation system based on FPGA. Background Art

[0002] Hardware-in-Loop (HIL) simulation is a simulation that integrates actual physical devices with a simulation system, different from full digital simulation. In HIL simulation, some devices are replaced by real physical devices, and the physical devices interact with the digital simulation part through I / O interfaces, so as to realize the test and verification of the physical devices, and the physical devices are also called devices under test.

[0003] To ensure the consistency of real-time performance, the progress of the real-time simulation program running on the CPU is synchronized with the real-time clock to simulate the behavior of the modeled system. Generally speaking, the smaller the simulation step size, the more detailed the change performance of the simulation system. At the beginning of each simulation step, the real-time simulation program reads data from I / O, and after the calculation is completed, the result is output to the device under test through I / O. Since it is necessary to interact with real physical devices, the data required for digital simulation needs to be transmitted through specific I / O interfaces, and the real-time performance of data transmission affects the overall real-time performance of the simulation system.

[0004] In a HIL simulation system, fast and accurate I / O data transmission between the simulator and the device under test is the key to ensuring that the simulation environment truly reflects the dynamic behavior of the physical system and allowing the device under test to be accurately tested and verified. Traditional data transmission methods mainly rely on high-speed network cards, USB protocols, and serial ports.

[0005] Among them, network card-based communication usually uses Ethernet technology, but faces inherent limitations:

[0006] 1) It needs to be processed through a complex network protocol stack (such as TCP / IP), resulting in high latency;

[0007] 2) The additional overhead brought by data traversal at the network interface layer across operating systems;

[0008] 3) The uncertain arrival time of data packets caused by network congestion or queuing dynamics.

[0009] USB and serial communications also have defects such as high latency and dependence on the kernel protocol stack, which further limits their applicability in low-latency and high-reliability scenarios. On the other hand, these methods usually rely on periodic interrupt requests to notify the CPU of the arrival of data, which not only introduces additional latency but also causes frequent CPU interrupts, reducing the overall performance of the system.

[0010] Some foreign commercial real-time simulation systems, such as RTDS, RT-Lab, etc., all adopt customized data acquisition cards for I / O data transmission. However, these systems have special designs, and the basic principles and implementation details lack transparency. This closed architecture limits the ability of researchers and developers to adjust or optimize these solutions for specific applications. Therefore, it is necessary to solve the key challenge of achieving fast and accurate data transmission between the simulator and the device under test, which is crucial for ensuring real-time performance, stability, and simulation accuracy. Summary of the Invention

[0011] The purpose of the present invention is to address the deficiencies of the above technologies and provide an FPGA-based high-performance hardware-in-the-loop simulation system IO data transmission method, which effectively solves the problems of operating system interference, interrupt overhead, and insufficient data consistency in traditional I / O communication.

[0012] To achieve the above objective, the FPGA-based high-performance hardware-in-the-loop simulation system IO data transmission method involved in the present invention encapsulates the collected data into PCIE TLP packets by the FPGA, and adds a sequence count value at the end of the last TLP packet, enabling the CPU to determine whether the TLP packet has arrived by polling whether the sequence count value increases incrementally. The CPU can reliably detect the arrival of data without the intervention of the operating system, ensuring deterministic latency and eliminating interrupt overhead. Then, it periodically initiates a DMA write request to the CPU actively based on its own hardware clock. Compared with CPU-based timing, the FPGA clock provides better real-time performance and simplifies synchronization with external signals. At the same time, a dual-buffer mechanism is adopted to minimize the participation of the CPU and ensure high-throughput packet processing. Combining direct cache access technology, it realizes directly writing the TLP packet into the last-level cache of the CPU, avoiding CPU memory copying and buffer competition.

[0013] Preferably, the FPGA hardware supports the PCIE transmission function.

[0014] Preferably, the buffer is the user-layer mapped memory address obtained by the FPGA driver mapping the DMA receive / send memory address in the kernel space to the user space through the mmap system call.

[0015] Preferably, in the dual-buffer mechanism, the FPGA alternately initiates DMA write requests to two buffers at adjacent fixed time intervals. The FPGA performs DMA writes to one of the buffers during the current fixed time interval, enabling the CPU to poll for the sequence count value to increment by one and switch the address pointer corresponding to the buffer. The FPGA performs DMA writes to the other buffer during the next adjacent fixed time interval, and so on in a loop, ensuring that when the FPGA writes to the standby buffer, the CPU always accesses the stable buffer, preventing data competition and ensuring the physical isolation between CPU access and FPGA writes.

[0016] Preferably, in the FPGA data transmission optimization, the PCIE bus operates in a strong-order mode, forcing the transmission of TLP packets in the order of arrival time to ensure that the transmission and processing of TLP packets are exactly consistent with their generation order, and disabling the function option in the BIOS that allows reordering of TLP packets, preventing potential reordering of data packets and ensuring sequential processing.

[0017] Preferably, the CPU hardware supports the direct cache access function, that is, it supports the peripheral to directly write I / O data into the last-level cache of the CPU.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] 1. Effectively solve the problems of operating system interference, interrupt overhead, and insufficient data consistency in traditional I / O communication;

[0020] 2. Significantly improve the real-time performance, throughput, and stability of the hardware-in-the-loop simulation system, and are applicable to high-performance real-time simulation scenarios in fields such as aviation, automotive, and power electronics. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the principle of the IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA of the present invention;

[0022] Figure 2 It is a schematic diagram of the principle of the zero-copy FPGA driver for the dual buffer;

[0023] Figure 3 It is a schematic diagram of the dual-buffer mechanism. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] FPGA has characteristics such as rich I / O interfaces, programmability, and strict real-time performance, and is widely used in real-time simulation. The FPGA that supports PCIe transmission plays a key role in the system. Its main functions include: 1) interacting with the device under test and organizing data; 2) periodically initiating DMA requests. The FPGA collects data from each internal data module according to the descriptor information written by the CPU to the FPGA register. Each descriptor stores information such as the packet address, request type, sequence count value, etc. The FPGA organizes the collected data into a format that conforms to the PCIe protocol, that is, encapsulates it into TLPs. When the data organization is ready, the FPGA actively sends packets periodically based on its own hardware clock and DMA controller.

[0026] As Figure 1 shown, an FPGA encapsulates the collected data into a PCIE TLP packet and adds a sequence count value to the tail of the last TLP packet, so that the CPU can judge whether the TLP packet has arrived by polling whether the sequence count value increases incrementally, and then periodically and actively initiates a DMA write request to the CPU based on its own hardware clock. At the same time, a double-buffer mechanism is adopted, combined with the Direct Cache Access (DCA) technology to realize directly writing the TLP packet into the last-level cache (LLC) of the CPU. The buffer is obtained by the FPGA driver mapping the DMA receive / send memory address in the kernel space to the user space through the mmap system call to get the user-layer mapped memory address.

[0027] The traditional CPU data update notification method based on interrupts involves the operating system, which will interfere with real-time tasks, increase transmission latency, and have a cold start problem when the interrupt handling is blocked. In the present invention, the sequence count value is appended to the tail of the last data packet. This sequence count value comes from the FPGA clock. Compared with the CPU-based timing, the FPGA clock provides better real-time performance and simplifies the synchronization with external signals. By polling the sequence count value, the CPU can reliably detect the arrival of data without the intervention of the operating system, ensuring deterministic latency and eliminating interrupt overhead. The sequence count value is only added to the last data packet in the data stream. This design choice takes into account the max payload size of the PCIe hardware motherboard.

[0028] The max payload size of the hardware motherboard is usually 256 bytes, which means that data larger than 256 bytes will be organized into multiple TLPs. By embedding the sequence count value into the final TLP, the CPU can verify whether all TLPs have arrived completely by monitoring the incremental change of the sequence count.

[0029] In this embodiment, the FPGA hardware supports the PCIE transmission function. In the optimization of FPGA data transmission, the PCIE bus operates in the Strongly Ordered Model, forcing the transmission of TLP packets in the order of arrival time to ensure that the transmission and processing of TLP packets are exactly the same as their generation order. The function option in the BIOS that allows reordering of TLP packets, such as the Relaxed Ordering option in IOAT (I / O Acceleration Technology), is disabled, preventing potential reordering of data packets and ensuring sequential processing.

[0030] Traditional data copying and context switching increase the overhead of memory and clock cycles, reducing system efficiency. To solve this problem, in this embodiment, as Figure 2 shown, the zero-copy DMA technology is adopted to improve the sending and receiving efficiency of data packets. This method minimizes the participation of the CPU and ensures high-throughput data packet processing. In this embodiment, a custom user-space FPGA driver is also designed to manage the interaction between the FPGA and the CPU. The driver is responsible for initializing the FPGA and allocating buffers.

[0031] In traditional technologies, when the data transmission rate of the FPGA is equal to the data access rate of the CPU, there is a risk of data inconsistency in a single buffer: new data from the FPGA may overwrite unprocessed data before the CPU finishes accessing it. To solve this problem, this embodiment adopts a double-buffer mechanism. The FPGA alternately initiates DMA write requests to two buffers at adjacent fixed time intervals, ensuring that when the FPGA writes to the standby buffer, the CPU always accesses the stable buffer, preventing data contention.

[0032] Specifically, as Figure 3 shown, in the double-buffer mechanism, the FPGA performs DMA writes to one of the buffers at the current fixed time interval, enabling the CPU to poll for an increment in the sequence count value and switch the address pointer corresponding to the buffer. The FPGA performs DMA writes to the other buffer at the next adjacent fixed time interval, and so on in a cycle.

[0033] Although increasing the number of buffers can further alleviate the speed mismatch between the FPGA and the CPU, it also introduces additional management overheads, such as buffer status tracking, switching logic, etc. Therefore, the double-buffer design achieves a balance between the performance and practicality of real-time systems.

[0034] In addition, in this embodiment, the CPU hardware supports the direct cache access function, that is, it supports the peripheral to directly write I / O data into the CPU's last-level cache, such as Intel DDIO (Data Direct I / O).

[0035] The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA of the present invention effectively solves the problems of operating system interference, interrupt overhead and insufficient data consistency in traditional I / O communication; significantly improves the real-time performance, throughput and stability of the hardware-in-the-loop simulation system, and is applicable to high-performance real-time simulation scenarios in the fields of aviation, automotive, power electronics, etc.

[0036] In the above embodiments, the descriptions of each embodiment have their own emphases. For parts not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0037] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for IO data transmission of a high-performance hardware-in-the-loop simulation system based on FPGA, characterized in that: The FPGA encapsulates the collected data into PCIE TLP packets and adds a sequence count value at the end of the last TLP packet, enabling the CPU to determine whether the TLP packet has arrived by polling whether the sequence count value increases incrementally. Then, based on its own hardware clock, it periodically initiates a DMA write request to the CPU actively. At the same time, a double-buffer mechanism is adopted, and combined with the direct cache access technology, it realizes directly writing the TLP packet into the CPU's last-level cache.

2. The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA according to claim 1, wherein: The FPGA hardware supports the PCIE transmission function.

3. The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA according to claim 1, characterized in that: The buffer is the user-layer mapped memory address obtained after the FPGA driver maps the DMA receive / send memory address in the kernel space to the user space through the mmap system call.

4. The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA according to claim 1, characterized in that: In the double-buffer mechanism, the FPGA alternately initiates DMA write requests to the two buffers at adjacent fixed time intervals. The FPGA performs DMA writes to one of the buffers during the current fixed time interval, enabling the CPU to poll that the sequence count value increases incrementally and switch the address pointer corresponding to the buffer. The FPGA performs DMA writes to the other buffer in the next adjacent fixed time interval, and so on in a loop.

5. The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA according to claim 1, characterized in that: In the FPGA data transmission optimization, the PCIE bus runs in strong-order mode, forcing the TLP packets to be sent in the order of arrival time, and disabling the function option in the BIOS that allows reordering of TLP packets.

6. The IO data transmission method of the high-performance hardware-in-the-loop simulation system based on FPGA according to claim 1, wherein: The CPU hardware supports the direct cache access function, that is, it supports the peripheral to directly write I / O data into the CPU's last-level cache.

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