Clock control circuit, clock control method, chip and electronic equipment
By configuring high-frequency and low-frequency clock signals in the chip and switching to low-frequency clock signals as the system clock when an abnormality is detected, the chip function circuit unresponsive problem caused by system clock abnormality is solved, and the reliability of chip operation is improved.
Patent Information
- Application Number
- CN202510342993.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, when the system clock is abnormal, the functional circuit in the chip is in an unresponsive state due to the lack of system clock driving, which affects the reliability of the chip operation.
The first clock signal with a high frequency and the second clock signal with a low frequency are configured, and the abnormality of the first clock signal is detected through the clock monitoring module, and when an abnormality is detected, switch to the second clock signal as the system clock signal to ensure that the functional circuit continues to operate before the first clock signal is restored.
Improve the reliability of the chip during system clock abnormality, avoiding the functional circuit from responding due to no system clock driving, and ensuring the normal operation of the circuit.
Smart Images
Figure CN120409380A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock control circuit, a clock control method, a chip, and an electronic device. Background Art
[0002] A stable and reliable clock is the basis for stable operation of the chip. Abnormal system clock will cause the functional circuits in the chip to fail or malfunction.
[0003] Currently, during chip operation, the system clock is monitored in real time to promptly detect system clock anomalies. When the system clock is abnormal, an interrupt signal or alarm signal is generated to enable the chip to handle the system clock anomaly. However, before the system clock recovers, most functional circuits are in an unresponsive state due to the lack of system clock drive, which is not conducive to improving the reliability of chip operation. Summary of the Invention
[0004] In view of the above problems, the embodiments of the present application provide a clock control circuit, a clock control method, a chip and an electronic device to solve the above technical problems that are not conducive to improving the reliability of chip operation.
[0005] In a first aspect, an embodiment of the present application provides a clock control circuit, including a clock monitoring module and a clock control module;
[0006] The clock monitoring module is configured to detect the first clock signal to generate a first detection signal according to the detection result;
[0007] The clock control module is used to control the first clock signal or the second clock signal to be output as a system clock signal according to the first detection signal; wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.
[0008] In a second aspect, an embodiment of the present application provides a clock control method, including:
[0009] detecting the first clock signal to generate a first detection signal according to the detection result;
[0010] The first clock signal or the second clock signal is controlled to be output as a system clock signal according to the first detection signal; wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.
[0011] In a third aspect, an embodiment of the present application provides a chip, which includes the above-mentioned clock control circuit.
[0012] In a fourth aspect, an embodiment of the present application provides an electronic device comprising the above-mentioned chip.
[0013] The clock control circuit, clock control method, chip and electronic device provided by the embodiments of the present application are configured with a first clock signal having a relatively high frequency and a second clock signal having a relatively low frequency, and the first clock signal is detected to generate a first detection signal of the first clock signal according to the detection result; one of the first clock signal or the second clock signal is output as the system clock signal according to the state of the first detection signal; in the above manner, when the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit from being in an unresponsive state due to the lack of the drive of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation.
[0014] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 The structural schematic diagram of the clock control circuit provided by the embodiments of the present application is shown.
[0016] Figure 2 The timing diagram of each signal in the clock control circuit provided by the embodiments of the present application is shown.
[0017] Figure 3 The structural schematic diagram of another implementation manner of the clock control circuit provided by the embodiments of the present application is shown.
[0018] Figure 4 The structural schematic diagram of another implementation manner of the clock control circuit provided by the embodiments of the present application is shown.
[0019] Figure 5 The application scenario diagram of the clock control circuit provided by the embodiments of the present application is shown.
[0020] Figure 6 The flow schematic diagram of the clock control circuit provided by the embodiments of the present application is shown.
[0021] Figure 7 The structural schematic diagram of the chip provided by the embodiments of the present application is shown.
[0022] Figure 8 The structural schematic diagram of the electronic device provided by the embodiments of the present application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] The following details the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.
[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of this application.
[0025] In the embodiments of this application, it should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0026] Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.
[0027] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate examples, explanations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0028] In addition, "a plurality of" in the embodiments of this application means two or more. In view of this, "a plurality of" in the embodiments of this application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B, and C, then what is included can be A, B, C, A and B, A and C, B and C, or A, B, and C.
[0029] It should be noted that in the embodiments of this application, "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the preceding and following associated objects.
[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0031] An embodiment of the present application provides a clock control circuit 100. Please refer to Figure 1 As shown, the clock control circuit 100 of this embodiment includes: a clock monitoring module 11 and a clock control module 12.
[0032] Among them, the clock monitoring module 11 is used to detect the first clock signal, generate a first detection signal of the first clock signal according to the detection result, and output the first detection signal to the clock control module 12.
[0033] Among them, the clock control module 12 is used to control the first clock signal or the second clock signal to be output as the system clock signal according to the first detection signal; among them, the frequency of the first clock signal is greater than the frequency of the second clock signal.
[0034] Among them, the first clock signal can be the main system clock signal, and the second clock signal can be the backup system clock signal. The first detection signal can be used to characterize whether the first clock signal is abnormal. If the first detection signal characterizes that the first clock signal is normal, the first clock signal is output as the system clock signal; if the first detection signal characterizes that the first clock signal is abnormal, the second clock signal is output as the system clock signal. Before the first clock signal is restored, at least one functional circuit can continue to operate based on the second clock signal.
[0035] In this embodiment, a first clock signal with a relatively high frequency and a second clock signal with a relatively low frequency are configured. When the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit from being in an unresponsive state due to the lack of drive of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation; when the system clock signal is switched to the second clock signal, the functional circuit can be driven by the second clock signal. For the functional circuit, only the frequency of the clock signal driving its operation changes.
[0036] As an implementation manner, please refer to Figure 2As shown, the state of the first detection signal can be used to select one of the first clock signal and the second clock signal as the system clock signal. Exemplarily, the first detection signal can have two logical states, namely logical state "1" and logical state "0"; logical state "1" can be used to indicate that the first clock signal is normal, and logical state "0" can be used to indicate that the first clock signal is abnormal, or logical state "1" can be used to indicate that the first clock signal is abnormal, and logical state "0" can be used to indicate that the first clock signal is normal.
[0037] Among them, the clock control module 12 is used to output the second clock signal as the system clock signal when the first detection signal indicates that the first clock signal is abnormal.
[0038] In some embodiments, the clock control module 12 is used to output the first clock signal as the system clock signal when the first detection signal indicates that the first clock signal is normal.
[0039] In this embodiment, characterizing the normality or abnormality of the first clock signal through the state of the first detection signal can improve the judgment speed of the clock control module.
[0040] In some embodiments, the abnormality of the first clock signal may include at least one of frequency abnormality of the first clock signal, loss of the first clock signal, non-inversion of the first clock signal, duty cycle abnormality of the first clock signal, and drift of the first clock signal.
[0041] As an implementation manner, please refer to Figure 3 As shown, the clock monitoring module 11 receives the first clock signal and the second clock signal. The clock monitoring module 11 is used to detect the first clock signal according to the second clock signal, so as to generate the first detection signal of the first clock signal according to the detection result.
[0042] In some embodiments, please refer to Figure 4 As shown, the clock monitoring module 11 includes a frequency divider 111 and a detection unit 112.
[0043] The frequency divider 111 is used to divide the frequency of the first clock signal to generate a divided frequency signal; wherein, the frequency of the divided frequency signal is less than the frequency of the second clock signal.
[0044] The detection unit 112 is used to time according to the second clock signal, detect the inversion edge of the divided frequency signal within each first preset duration, and generate the first detection signal of each first preset duration according to whether there is an inversion edge within the corresponding first preset duration.
[0045] Among them, timing is performed according to the second clock signal. The time series includes multiple sequentially connected time periods, and the duration of each time period is a first preset duration. During each time period, the rising or falling edge of the divided-frequency signal is detected. If no rising or falling edge of the divided-frequency signal is detected within a certain time period, there is no edge change in the divided-frequency signal within the corresponding time period, the first clock signal within this time period is abnormal, and the state of the first detection signal within this time period is a logical state indicating that the first clock signal is abnormal; if at least one rising or falling edge of the divided-frequency signal is detected within a certain time period, there is an edge change in the divided-frequency signal within the corresponding time period, the first clock signal within this time period is normal, and the state of the first detection signal within this time period is a logical state indicating that the first clock signal is normal.
[0046] Among them, the frequency of the divided-frequency signal can be n times the frequency of the first clock signal. Exemplarily, n can be an integer greater than or equal to 50 and less than or equal to 60.
[0047] Among them, the first preset duration can be greater than the period of the divided-frequency signal. For example, the first preset duration can be N times the period of the divided-frequency signal, and N can be an integer greater than or equal to 10 and less than or equal to 20.
[0048] The first preset duration can be selected according to actual needs. If the range of the first preset duration is relatively narrow, the normal jitter of the first clock signal will be misjudged as an abnormal first clock signal; if the range of the first preset duration is relatively wide, it is not conducive to improving the abnormal recognition speed of the first clock signal.
[0049] In this embodiment, according to the edge change state of the divided-frequency signal of the first clock signal within each first preset duration, it is detected whether the first clock signal is abnormal, and the state of the first detection signal is determined according to whether the first clock signal is normal, which is beneficial to improving the detection speed.
[0050] As an implementation manner, please continue to refer to Figure 3 As shown, the clock control circuit 100 further includes a first processing module 13. Among them, the first processing module 13 is used to generate a second detection signal according to the state of the first detection signal and output the second detection signal to at least one first pin.
[0051] Among them, the clock control circuit 100 can be applied to Figure 5 the chip 200 shown. The chip 200 includes at least one first pin and at least one second pin. The chip 200 is connected to an external circuit through the first pin. The external circuit is a functional circuit located outside the chip 200, and there can be data interaction between the external circuit and the chip 200.
[0052] Among them, the first processing module 13 is used to generate a first pulse signal as the second detection signal when the state of the first detection signal indicates that the first clock signal is normal; and generate a first level signal as the second detection signal when the state of the first detection signal indicates that the first clock signal is abnormal. Exemplarily, please refer to Figure 3 As shown, the first pulse signal can be a pulse signal whose state flips every period of the second clock signal, and the first level signal can be a low level signal.
[0053] Among them, the second detection signal can be transmitted to an external circuit through the first pin, so that the external circuit can determine whether the first clock signal is normal or abnormal based on the second detection signal. In some embodiments. When the external circuit determines that the first clock signal is abnormal, it can send a processing signal through the second pin, and this processing signal can process the abnormality of the first clock signal. Exemplarily, this processing signal is used to restart the chip or to restart the functional circuit that generates the first clock signal in the chip.
[0054] In this embodiment, the second detection signal is generated by the first processing module and sent to the first pin, enabling the external circuit to determine whether the first clock signal is normal or abnormal based on the second detection signal. When the first clock signal is abnormal, the external circuit can respond to the abnormality of the first clock signal and send a processing signal to restore the clock function.
[0055] In some embodiments, the first processing module 13 is used for:
[0056] When the state of the first detection signal indicates that the first clock signal is normal, flip the second detection signal every period of the second clock signal;
[0057] When the state of the first detection signal indicates that the first clock signal is abnormal, use the first level signal as the second detection signal, so that the external circuit generates a first processing signal according to the first level signal.
[0058] Among them, please refer to Figure 2 As shown, the first processing module 13 times according to the second clock signal. If the state of the first detection signal indicates that the first clock signal is normal, the second detection signal flips once every period of the second clock signal. The continuous flipping of the second detection signal indicates that the first clock signal is normal; if the state of the first detection signal indicates that the first clock signal is abnormal, the second detection signal is the first level signal, and the stop of the flipping of the second detection signal indicates that the first clock signal is abnormal. Exemplarily, the first level signal can be a high level signal or a low level signal.
[0059] Among them, the first processing signal can be sent to the inside of the chip through the second pin. The first processing signal can handle the abnormality of the first clock signal. Exemplarily, the first processing signal is used to restart the chip or to restart the functional circuit that generates the first clock signal in the chip.
[0060] In some embodiments, please continue to refer to Figure 3 As shown, the clock control circuit further includes a second processing module 14. Among them, the second processing module 14 is used to output a second processing signal when the state of the first detection signal indicates an abnormality of the first clock signal.
[0061] Among them, the second processing signal can handle the abnormality of the first clock signal. Exemplarily, the second processing signal is used to restart the chip or to restart the functional circuit that generates the first clock signal in the chip.
[0062] In this embodiment, a method of disposing of the first clock signal abnormality through an external circuit and a method of disposing of it through an internal second processing module are configured simultaneously, increasing the diversity of clock abnormality responses, which is beneficial to increasing the recovery path of the first clock signal.
[0063] In an alternative application scenario, the first processing module 13 and the second processing module 14 are respectively used for the clock failure response processing of the chip 200, and both the first processing module 13 and the second processing module 14 operate under the drive of the second clock signal.
[0064] As an embodiment, please continue to refer to Figure 4 As shown, the clock control circuit 100 further includes a first clock generator 15 and a second clock generator 16. The first clock generator 15 is used to generate a first clock signal, and the second clock generator 16 is used to generate a second clock signal.
[0065] Among them, the first clock generator 15 can be located in the digital domain of the chip 200. The first clock generator 15 can be a PLL (Phase-Locked Loop) clock source. The first clock signal can be a PLL clock signal. The first clock generator 15 can be used to provide a high-frequency and stable clock signal.
[0066] Among them, the second clock generator 16 can be located in the Always on Domain (AON) of the chip 200. After the chip 200 is powered on and before the first clock generator 15 starts, the second clock generator 16 starts and generates a second clock signal. The second clock signal can be used to drive the start of each digital circuit located in the digital domain of the chip 200, that is, the second clock signal can be used to drive the start process of the first clock generator 15 located in the digital domain of the chip 200.
[0067] Therefore, the first clock generator 15 is also used to execute a startup process according to the second clock signal during the power-on process. After the first clock generator 15 is started, it generates the first clock signal.
[0068] In this embodiment, the low-frequency clock signal in the AON domain is used as the second clock signal, and there is no need to separately set the clock source of the second clock signal, which is beneficial to saving the chip area and simplifying the circuit setup.
[0069] Exemplarily, the above first processing signal can be used to diagnose and / or restart the first clock generator 15, and the second processing signal can be used to diagnose and / or restart the first clock generator 15.
[0070] After troubleshooting or restarting the first clock generator 15, the first clock signal returns to normal. At this time, the status of the first detection signal output by the clock monitoring module 11 indicates that the first clock signal is normal, and the clock control module 12 switches the first clock signal as the system clock signal.
[0071] As an implementation manner, please continue to refer to Figure 4 As shown, the clock control circuit 100 further includes a register 17, and the register 17 is used to store the detection data of the first clock signal. Exemplarily, the detection data can be the status of the first detection signal (e.g., logical status). The external circuit that generates the first processing signal can call the detection data in the register 17 and diagnose the first clock generator 15 according to the detection data; the second processing module 14 that generates the second processing signal can also call the detection data in the register 17 and diagnose the first clock generator 15 according to the detection data.
[0072] An embodiment of the present application provides a clock control method. Please refer to Figure 6 As shown, the clock control method includes the following steps S11 and step S12:
[0073] Step S11: Detect the first clock signal to generate a first detection signal according to the detection result.
[0074] Step S12: Control the first clock signal or the second clock signal to be output as the system clock signal according to the first detection signal; wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.
[0075] Among them, the first clock signal can be the main system clock signal, and the second clock signal can be the backup system clock signal. The first detection signal can be used to characterize whether the first clock signal is abnormal. If the first detection signal characterizes that the first clock signal is normal, the first clock signal is output as the system clock signal; if the first detection signal characterizes that the first clock signal is abnormal, the second clock signal is output as the system clock signal. Before the first clock signal is restored, at least one functional circuit can maintain operation based on the second clock signal; when the system clock signal is switched to the second clock signal, the functional circuit can be driven by the second clock signal. For the functional circuit, only the frequency of the clock signal driving its operation changes.
[0076] In this embodiment, a first clock signal with a relatively high frequency and a second clock signal with a relatively low frequency are configured. The first clock signal is detected to generate a first detection signal of the first clock signal according to the detection result; according to the state of the first detection signal, one of the first clock signal and the second clock signal is output as the system clock signal; in the above manner, when the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit being in an unresponsive state due to the lack of driving of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation.
[0077] As an implementation manner, in step S12, the state of the first detection signal can be used to select and output one of the first clock signal and the second clock signal as the system clock signal. Step S12 specifically includes the following steps:
[0078] Step S121: When the state of the first detection signal indicates that the first clock signal is abnormal, output the second clock signal as the system clock signal.
[0079] In some implementation manners, step S12 further includes the following steps:
[0080] Step S122: When the state of the first detection signal indicates that the first clock signal is normal, output the first clock signal as the system clock signal.
[0081] In some implementation manners, step S11 specifically includes the following steps:
[0082] Step S11a: Detect the first clock signal according to the second clock signal to generate a first detection signal of the first clock signal according to the detection result.
[0083] In some implementation manners, step S11a specifically includes the following steps:
[0084] Step S111: Divide the frequency of the first clock signal to generate a divided signal, where the frequency of the divided signal is less than the frequency of the second clock signal.
[0085] Step S112: Perform timing according to the second clock signal, detect the rising or falling edge of the divided signal within each first preset duration, and generate a first detection signal for each first preset duration according to whether there is a rising or falling edge within the corresponding first preset duration.
[0086] In some embodiments, the clock control method further includes the following steps:
[0087] Step S13: Generate a second detection signal according to the state of the first detection signal, and output the second detection signal to at least one first pin.
[0088] In some embodiments, step S13 specifically includes the following steps:
[0089] Step S131: When the state of the first detection signal indicates that the first clock signal is normal, flip the second detection signal every period of the second clock signal.
[0090] Step S132: When the state of the first detection signal indicates that the first clock signal is abnormal, use the first-level signal as the second detection signal so that the external circuit generates a first processing signal according to the first-level signal.
[0091] In some embodiments, the clock control method further includes the following steps:
[0092] Step S14: Output a second processing signal when the state of the first detection signal indicates that the first clock signal is abnormal.
[0093] In some embodiments, before step S11, the clock control method further includes the following steps:
[0094] Step S10: During the power-on process, execute a startup process according to the second clock signal to generate the first clock signal.
[0095] The clock control method of this embodiment is configured with a first clock signal with a relatively high frequency and a second clock signal with a relatively low frequency, detects the first clock signal, and generates a first detection signal of the first clock signal according to the detection result; outputs one of the first clock signal or the second clock signal as the system clock signal according to the state of the first detection signal; in the above manner, when the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit from being in an unresponsive state due to the lack of the drive of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation.
[0096] An embodiment of the present application provides a chip 300, which can be applied to an electronic device including a hardware interface 21. Please refer to Figure 7 As shown, the chip 300 includes the above-mentioned clock control circuit 100. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level package) chip.
[0097] The chip of this embodiment is configured with a first clock signal with a relatively high frequency and a second clock signal with a relatively low frequency, and the first clock signal is detected to generate a first detection signal of the first clock signal according to the detection result; according to the state of the first detection signal, one of the first clock signal and the second clock signal is output as the system clock signal; in this way, when the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit being in an unresponsive state due to the lack of drive of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation; when the system clock signal is switched to the second clock signal, the functional circuit can be driven by the second clock signal. For the functional circuit, only the frequency of the clock signal driving its operation changes.
[0098] An embodiment of the present application also provides an electronic device 400. Please refer to Figure 8 As shown, the electronic device 400 includes a device main body and the above-mentioned chip 300 disposed in the device main body. The electronic device can be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, a pulse oximeter, a body composition analyzer, a display, a USB (Universal Serial Bus, universal serial bus) docking station, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop computer, a tablet computer, a POS (point of sales terminal, sales point terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, a smart light.
[0099] The electronic device of this embodiment is configured with a first clock signal having a relatively high frequency and a second clock signal having a relatively low frequency, and the first clock signal is detected to generate a first detection signal of the first clock signal according to the detection result; one of the first clock signal or the second clock signal is output as the system clock signal according to the state of the first detection signal; in this way, when the first clock signal is abnormal, the system clock signal is switched to the second clock signal, avoiding the functional circuit being in an unresponsive state due to the lack of the drive of the system clock signal before the first clock signal is restored, which is beneficial to improving the reliability of the chip operation; when the system clock signal is switched to the second clock signal, the functional circuit can be driven by the second clock signal. For the functional circuit, only the frequency of the clock signal driving its operation changes.
[0100] The above are only the implementation manners of the present application. It should be noted here that for those of ordinary skill in the art, improvements can be made without departing from the inventive concept of the present application, but these all belong to the protection scope of the present application.
Claims
1. A clock control circuit, characterized in that, It includes a clock monitoring module and a clock control module; The clock monitoring module is used to detect the first clock signal to generate a first detection signal according to the detection result; The clock control module is used to control the first clock signal or the second clock signal to be output as the system clock signal according to the first detection signal; wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.
2. The clock control circuit according to claim 1, wherein The clock control module is used to output the second clock signal as the system clock signal when the first detection signal indicates that the first clock signal is abnormal.
3. The clock control circuit according to claim 2, wherein The clock control module is used to output the first clock signal as the system clock signal when the first detection signal indicates that the first clock signal is normal.
4. The clock control circuit according to claim 1, wherein The clock monitoring module is used to detect the first clock signal according to the second clock signal to generate the first detection signal according to the detection result.
5. The clock control circuit according to claim 4, wherein The clock monitoring module includes: A frequency divider for dividing the frequency of the first clock signal to generate a divided signal; wherein, the frequency of the divided signal is less than the frequency of the second clock signal; A detection unit for timing according to the second clock signal, detecting the flip edge of the divided signal within each first preset duration, and generating the first detection signal of each first preset duration according to whether there is a flip edge within the corresponding first preset duration.
6. The clock control circuit according to claim 1, characterized in that, The clock control circuit further includes: A first processing module for generating a second detection signal according to the state of the first detection signal and outputting the second detection signal to at least one first pin.
7. The clock control circuit according to claim 6, wherein The first processing module is used for: When the state of the first detection signal indicates that the first clock signal is normal, flipping the second detection signal every period of the second clock signal; When the state of the first detection signal indicates that the first clock signal is abnormal, using a first-level signal as the second detection signal so that an external circuit generates a first processing signal according to the first-level signal.
8. The clock control circuit according to claim 6, wherein The clock control circuit further includes: A second processing module for outputting a second processing signal when the state of the first detection signal indicates that the first clock signal is abnormal.
9. The clock control circuit according to claim 1, characterized in that, The clock control circuit further includes: A first clock generator for generating the first clock signal; The first clock generator is further used to execute a startup process according to the second clock signal during the power-on process.
10. A clock control method, characterized in that, It includes: Detecting the first clock signal to generate a first detection signal according to the detection result; Controlling the first clock signal or the second clock signal to be output as the system clock signal according to the first detection signal; wherein, the frequency of the first clock signal is greater than the frequency of the second clock signal.
11. A chip, characterized in that, It includes the clock control circuit according to any one of claims 1 to 9.
12. An electronic device, characterized in that, It includes the chip according to claim 11.