A circuit analysis and search method and device with gated clock

Abstract

The present invention discloses a circuit analysis and search method and device with a gated clock. The method comprises: S1, distinguishing the timing relationship of triggers based on clock gating, and re-screening and grouping the triggers based on the timing to obtain trigger grouping results; S2, dynamically searching and locating relevant logic gate circuits based on the bidirectional data flow relationship between adders and triggers, and merging and grouping them with corresponding trigger circuits to obtain preliminary grouping results for counters and accumulators; S3, verifying whether the boundaries of the counters and accumulators in the preliminary grouping results are complete to obtain a verified grouping result; S4, reordering and classifying the counters and accumulators in the verified grouping results based on the adder sequence to obtain a final classification result for the counters and accumulators. The present invention improves the search efficiency and accuracy of counters and accumulators with timing correlation, reduces the time and cost of manual analysis of digital integrated circuits.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of circuit analysis, and in particular to a method and device for analyzing and searching a circuit with a gated clock. Background Art

[0002] In the reverse analysis of digital integrated circuits, counters and accumulators are core modules for implementing arithmetic operations and state control. Accurate identification of their functional characteristics is one of the core challenges of reverse engineering.

[0003] Taking counters as an example, they can be implemented synchronously, asynchronously, and using ripple carry, offering features such as variable modulus and gated clocks. Their diverse implementations and dynamic reconfiguration require a coordinated analysis of multiple dimensions, including timing, data paths, and control grids. Accumulators, however, involve multi-level data dependencies and feedback paths, posing a risk of logical disconnection in scenarios such as bus multiplexing and cross-clock domain crossings.

[0004] See also Figure 1 The existing technology can only identify counters with specific structures, but cannot identify the simplified logic contained therein. In addition, there is a generally high misjudgment rate in the recognition, such as misidentifying the accumulator as a general register, incomplete paths, and low efficiency. These problems seriously restrict the efficiency of chip analysis and the reliability of intellectual property analysis. Summary of the Invention

[0005] The present invention provides a circuit analysis and search method and device with a gated clock. By introducing clock gating signal tracing, a data flow bidirectional search mechanism, and a cross-level verification strategy, the problems of counter path ambiguity and accumulator data chain breakage in integrated circuit reverse analysis are solved.

[0006] In a first aspect, an embodiment of the present invention provides a method for analyzing and searching a circuit with a gated clock, comprising:

[0007] S1. In a scattered data netlist with connection relationships, distinguish the timing relationships of triggers according to clock gating circuits, and re-screen and group the triggers based on the timing to obtain a trigger grouping result;

[0008] S2. Dynamically search and locate relevant logic gate circuits based on the bidirectional data flow relationship between the adder and the flip-flop, merge and group the captured logic gate circuits with the corresponding flip-flop circuits, and obtain preliminary grouping results for the counters and accumulators.

[0009] S3. Verify whether the boundaries of the counter and the accumulator in the preliminary grouping result are complete, and obtain a verified grouping result;

[0010] S4. Reorder and classify the counters and accumulators in the verified grouping result according to the adder order to obtain a final classification result of the counters and accumulators.

[0011] Optionally, the S1 specifically includes:

[0012] Classify clock gating circuits according to the number of forward gate-level circuits and reverse gate-level circuits that the clock passes through to the clock input source;

[0013] Group the flip-flops based on the connection relationship between the timing and flip-flops of the same type of clock gating circuits;

[0014] Verify the correctness of the classification of flip-flops and clock gating circuits, and arrange the flip-flops and clock gating circuits.

[0015] Optionally, grouping the triggers according to the post-timing of similar clock gating circuits and the connection relationship between the triggers includes:

[0016] If the same type of clock gating circuit is connected to a flip-flop through a forward logic gate circuit, the corresponding flip-flop and clock gating are considered to be the same logic;

[0017] If the same type of clock gating circuit is sequentially connected to a flip-flop through a reverse logic gate circuit, the corresponding flip-flop and clock gating are regarded as opposite logic.

[0018] Optionally, the S2 specifically includes:

[0019] S21. According to the bidirectional data flow relationship between the adder and the trigger, the adder and related logic gate circuits are captured from the scattered data netlist and added to the corresponding trigger group to obtain an adder-trigger group;

[0020] S22 . Capture a simplified logic circuit of an adder from the scattered data netlist, and add the simplified logic circuit to a corresponding adder-flip-flop group.

[0021] Optionally, the S21 includes:

[0022] Search a preset number of gate-level circuits forward from the grouped trigger input D terminal, and capture the adder and related logic gate circuits in the search path;

[0023] Search backward for a preset number of gate circuits from the carry output port of the captured adder. If it passes through the adder, continue to search backward for a preset number of gate circuits. If the loop can be closed, the adder and logic gate circuits in the path are merged into the group. Otherwise, reserve a search space at the corresponding port.

[0024] Optionally, the S22 includes:

[0025] Searching for a preset number of gate circuits in the group and before the D end of the unmatched trigger of the adder, and continuing to search for a preset number of gate circuits forward after finding an XOR gate or an XNOR gate, and if all gate circuits can be connected to the carry output port in the group, grabbing all the gate circuits found into the group and filling the reserved search space;

[0026] Search for a preset number of gate circuits backward from the output port of the trigger. If it passes through other groups, the search is terminated and the port is retained; if it can return to the group, the found gate circuit is captured into the corresponding group.

[0027] Optionally, the S3 specifically includes:

[0028] Check whether the output port to which the group is connected outward is only the output port Q or the reverse output port QN of the trigger. If not, return to execute S2.

[0029] If so, the input port connected to the outside of the group is checked. If there is a structure where the adder input is connected to the output of another adder SUM, it is divided into a multiplier or other group.

[0030] Optionally, the S4 specifically includes:

[0031] Sort the adders from low to high according to the carry output ports of the adder circuit, connect the ports of the adders to the corresponding ports of the triggers and keep all the output ports short;

[0032] According to the adder type and the logic gate circuit type in the group, the corresponding group is set as a counter or an accumulator to obtain the final classification result of the counter and the accumulator.

[0033] Optionally, the corresponding group is set as a counter or an accumulator according to the type of adder and logic gate circuit in the group, including:

[0034] If there is a full adder or a three-input XOR gate / XNOR gate in the group, the corresponding group is set as an accumulator;

[0035] If there is only a half adder or a two-input XOR gate / XNOR gate in the group, the corresponding group is set as a counter.

[0036] In a second aspect, an embodiment of the present invention further provides a circuit analysis and search device with a gated clock, comprising:

[0037] A trigger grouping module is used to distinguish the timing relationship of triggers in a scattered data netlist with connection relationships according to the clock gating circuit, and re-screen and group the triggers based on the timing to obtain the trigger grouping results;

[0038] The preliminary grouping module is used to dynamically find and locate the relevant logic gate circuits based on the bidirectional data flow relationship between the adder and the trigger, merge and group the captured logic gate circuits with the corresponding trigger circuits, and obtain the preliminary grouping results of the counters and accumulators;

[0039] A verification module, configured to verify whether the boundaries of the counters and accumulators in the preliminary grouping result are complete, and obtain a verified grouping result;

[0040] The classification and sorting module is used to reorder and sort the counters and accumulators in the verified grouping results according to the adder order to obtain the final classification results of the counters and accumulators.

[0041] This invention addresses the issues of ambiguous counter paths and broken accumulator data chains during integrated circuit reverse engineering by introducing clock-gating signal tracing, a bidirectional data flow search mechanism, and a cross-level verification strategy. Furthermore, the invention's technical solution can search for special counters and accumulators containing simplified logic circuits, improving the efficiency and accuracy of searches for timing-dependent counters and accumulators, reducing the time and cost of manual analysis of digital integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural diagram of a conventional counter in the prior art;

[0043] Figure 2 A flowchart of a method for analyzing and searching a circuit with a gated clock provided by an embodiment of the present invention;

[0044] Figure 3 A clock gating circuit diagram provided by an embodiment of the present invention;

[0045] Figure 4 A trigger circuit diagram provided by an embodiment of the present invention;

[0046] Figure 5 A fragmented data netlist diagram provided by an embodiment of the present invention;

[0047] Figure 6 A diagram illustrating trigger grouping provided by an embodiment of the present invention;

[0048] Figure 7 A structural diagram of a half adder provided by an embodiment of the present invention;

[0049] Figure 8 A structural diagram of a full adder provided in an embodiment of the present invention;

[0050] Figure 9 A preliminary crawling result diagram provided by an embodiment of the present invention;

[0051] Figure 10 A structural diagram of an XOR gate provided by an embodiment of the present invention;

[0052] Figure 11 A structural diagram of an XNOR gate provided by an embodiment of the present invention;

[0053] Figure 12 A further captured result graph provided by an embodiment of the present invention;

[0054] Figure 13 A result diagram of verification and sorting completed according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures. Example

[0056] Figure 2 A flowchart of a method for analyzing and searching a circuit with a gated clock provided by an embodiment of the present invention specifically includes the following steps:

[0057] S1. In a scattered data netlist with connection relationships, distinguish the timing relationship of triggers according to the clock gating circuit, and re-screen and group the triggers based on the timing to obtain the grouping results of the triggers.

[0058] See also Figure 3 and Figure 4 , this embodiment is based on Figure 3 Distinguishing clock gating circuits in Figure 4 The timing relationship of the triggers in the trigger, re-filter the triggers and group them based on the timing.

[0059] Figure 5 To illustrate a scattered data netlist with connection relationships, this step mainly pre-processes the functional elements in the data netlist based on timing and other logic, specifically including the following steps:

[0060] 1. Screening clock gating circuits based on clock tree

[0061] Specifically, the clock gating circuit is classified into categories A, B, C, etc. according to the number m of forward gate-level circuits and n of reverse gate-level circuits that the clock passes through from the clock gating to the clock input source.

[0062] Gated clocks with the same m and n values ​​can be considered as one type and will be processed as such in subsequent steps. If a gated clock is still connected to other gated clocks, it will be further classified as A1, A2, and so on.

[0063] 2. Classification-based clock gating circuit screening trigger

[0064] Based on the connections after the same type of clock gating circuits, flip-flops whose timing is directly connected to the clock gating circuits are captured from the flip-flop stack. Specifically, the flip-flops are grouped based on the connections between the timing after the same type of clock gating circuits and the flip-flops. If the timing after the same type of clock gating circuits is connected to the flip-flops through a positive logic gate circuit, the corresponding flip-flops and the clock gating circuits are considered to have the same logic. If the timing after the same type of clock gating circuits is connected to the flip-flops through a negative logic gate circuit, the corresponding flip-flops and the clock gating circuits are considered to have opposite logics and are classified as A1, A1N, and so on, to distinguish them from the previous group of flip-flops.

[0065] 3. Verify classified flip-flops and clock gating circuits

[0066] Specifically, based on the scan control terminal and reset terminal of the classified trigger, as well as the control terminal of the clock gating circuit, check the correctness of the classification of the trigger and the clock gating circuit. For example, the control terminal and reset terminal of the trigger and the gated clock circuit distributed in the same group should be connected to the same line. If not, they should be removed from the group. Furthermore, the trigger and clock gating columns are arranged according to the size of m and n. For example, the trigger groups can be sorted in the order of m and n from small to large. See the grouping of triggers after preprocessing. Figure 6 .

[0067] S2. Based on the bidirectional data flow relationship between the adder and the trigger, dynamically search and locate the relevant logic gate circuits, merge and group the captured logic gate circuits with the corresponding trigger circuits, and obtain the preliminary grouping results of the counters and accumulators.

[0068] Counters and accumulators are inseparable from adders. Counters come in various types, including addition, subtraction, and reversible counters. Adders also have a variety of simplified logic configurations. This embodiment locates and captures the relevant logic gate circuits based on the bidirectional data flow relationship between adders and flip-flops, and merges and groups them with the corresponding flip-flop circuits.

[0069] Specifically, the S2 includes:

[0070] S21. Based on the bidirectional data flow relationship between the adder and the flip-flop, extract the adder and related logic gate circuits from the scattered data netlist and add them to the corresponding flip-flop group to obtain an adder-flip-flop group. S22. Extract the simplified logic circuit of the adder from the scattered data netlist and add the simplified logic circuit to the corresponding adder-flip-flop group. The detailed steps are as follows:

[0071] 1. Search for a preset number of gate-level circuits forward based on the grouped trigger input D terminal. The preset number can be adjusted according to the circuit process node and complexity, so that the key circuit of the counter or accumulator can be found more accurately. The default setting here is 3. If there are three gate-level circuits Figure 7 The half adder or Figure 8 The full adder in the group is then merged into the trigger group along with the logic gates it passes through. This operation is applied to all triggers within the group. If no adder is found in the group of triggers, the trigger group is set as a pending group. The search level can be expanded in the future according to the engineer's needs or it can be treated as a non-counting or accumulating unit. If it passes through other groups, it is terminated and the port is retained.

[0072] 2. In the adder-flip-flop group that has been searched, search three logic gate circuits backward based on the carry CO data port of the captured adder. If it passes through other groups, terminate and retain the port; if it passes through the adder, continue to search three logic gate circuits backward from the adder's sum output port SUM. If it can return to the D input of the trigger in this group, merge the adder together with the passed logic gate circuit into the group; otherwise, draw a frame at the port to reserve a search space. The preliminary captured result is shown in the figure. Figure 9 .

[0073] 3. Based on the adder sum output SUM in the previous step to the trigger input D, match the corresponding adder-flip-flop, and then search three gate circuits forward from the unmatched trigger input D. If Figure 10 The XOR gate in Figure 11 If there is an XOR gate in the group, it is captured into the group and further searched for three gate circuits from the XOR gate and the XOR gate. If it can be connected to the carry output port CO in the group, all the gate circuits found in this sub-step are captured into the group and filled into the corresponding reserved search space in the previous step.

[0074] 4. Continue to search for three gate circuits from the output port Q and the reverse output port QN of the trigger. If it passes through other groups, terminate and retain the port. If it can return to the group, capture the gate circuit found into the group. See the result of further capture in the figure. Figure 12 .

[0075] S3. Verify whether the boundaries of the counters and accumulators in the preliminary grouping result are complete, and obtain a verified grouping result.

[0076] After executing S1 and S2, the functions within the group are basically complete, but there are still some scattered gate circuits that may not be captured, or the multiplier may be mistakenly captured. These need to be improved in this step. The specific method is as follows:

[0077] 1. Check the output ports of the group connected to the outside. In addition to the output port Q of the trigger and the reverse output port QN, are there other output ports? If so, return to S2 and re-capture; if not, proceed to the next step.

[0078] 2. Check the outgoing input ports of the group, excluding the gated clock input CP, flip-flop reset CDN / set input SDN, test chain select input SE, and serial data input SI. Check to see if the same adder input is connected to the sum output of another adder (SUM). If so, classify it as a multiplier or other group, distinct from the counter and accumulator groups in this embodiment. If not, proceed to the next step.

[0079] S4. Reorder and classify the counters and accumulators in the verified grouping result according to the adder order to obtain a final classification result of the counters and accumulators.

[0080] After completing the above steps, the regional division of counters and accumulators is essentially complete. This step primarily distinguishes their functions based on their structure, optimizing and sorting them. First, the adders are sorted from lowest to highest based on their carry output ports. The adder ports are connected to the corresponding ports of the flip-flops, leaving all output ports short. Next, the corresponding groups are assigned to counters or accumulators based on the adder type and logic gate type within the group, resulting in the final classification of counters and accumulators.

[0081] The specific method is as follows:

[0082] 1. Based on the adder and the carry output port CO of the adder circuit that is outlined, sort the adders from low to high, and connect the adder output port SUM to the input D of the trigger accordingly. Connect the output Q or reverse input terminal QN of the trigger to the corresponding input port of the adder, and keep all output ports short.

[0083] 2. Check the filtered and sorted groups. If there is a full adder or a three-input XOR gate / XNOR gate in the group, set the corresponding group as an accumulator; if there is only a half adder or a two-input XOR gate / XNOR gate in the group, set the corresponding group as a counter. See the result of verification and sorting in the figure. Figure 13 .

[0084] The present invention provides a novel circuit analysis and search method, which can search for special counters and accumulators containing logic simplified circuits, improves the search efficiency and accuracy of counters and accumulators with timing correlation, reduces the time and cost of manual analysis of digital integrated circuits.

[0085] The present invention also provides a circuit analysis and search device with a gated clock, comprising:

[0086] A trigger grouping module is used to distinguish the timing relationship of triggers in a scattered data netlist with connection relationships according to the clock gating circuit, and re-screen and group the triggers based on the timing to obtain the trigger grouping results;

[0087] The preliminary grouping module is used to dynamically find and locate relevant logic gate circuits based on the bidirectional data flow relationship between the adder and the trigger, merge and group the captured logic gate circuits with the corresponding trigger circuits, and obtain the preliminary grouping results of the counters and accumulators;

[0088] A verification module, configured to verify whether the boundaries of the counters and accumulators in the preliminary grouping result are complete, and obtain a verified grouping result;

[0089] The classification and sorting module is used to reorder and sort the counters and accumulators in the verified grouping results according to the adder order to obtain the final classification results of the counters and accumulators.

[0090] The preliminary grouping results are specifically used for:

[0091] Classify clock gating circuits according to the number of forward gate-level circuits and reverse gate-level circuits that the clock passes through to the clock input source;

[0092] Group the flip-flops based on the connection relationship between the timing and flip-flops of the same type of clock gating circuits;

[0093] Verify the correctness of the classification of flip-flops and clock gating circuits, and arrange the flip-flops and clock gating circuits.

[0094] Specifically, the triggers are grouped according to the connection relationship between the timing of the same type of clock gating circuit and the triggers, including:

[0095] If the same type of clock gating circuit is connected to a flip-flop through a forward logic gate circuit, the corresponding flip-flop and clock gating are considered to be the same logic;

[0096] If the same type of clock gating circuit is sequentially connected to a flip-flop through a reverse logic gate circuit, the corresponding flip-flop and clock gating are regarded as opposite logic.

[0097] Optionally, the preliminary grouping results may include:

[0098] S21. According to the bidirectional data flow relationship between the adder and the trigger, the adder and related logic gate circuits are captured from the scattered data netlist and added to the corresponding trigger group to obtain an adder-trigger group;

[0099] S22 . Capture a simplified logic circuit of an adder from the scattered data netlist, and add the simplified logic circuit to a corresponding adder-flip-flop group.

[0100] Specifically, the above S21 includes:

[0101] Search a preset number of gate-level circuits forward from the grouped trigger input D terminal, and capture the adder and related logic gate circuits in the search path;

[0102] Search backward for a preset number of gate circuits from the carry output port of the captured adder. If it passes through the adder, continue to search backward for a preset number of gate circuits. If the loop can be closed, the adder and logic gate circuits in the path are merged into the group. Otherwise, reserve a search space at the corresponding port.

[0103] The above-mentioned S22 includes:

[0104] Searching for a preset number of gate circuits from the group and before the D end of the unmatched trigger of the adder, and continuing to search for a preset number of gate circuits forward after finding an XOR gate or an XNOR gate, and if all gate circuits can be connected to the carry output port in the group, grabbing all the gate circuits found into the group and filling the reserved search space;

[0105] Search for a preset number of gate circuits backward from the output port of the trigger. If it passes through other groups, the search is terminated and the port is retained; if it can return to the group, the found gate circuit is captured into the corresponding group.

[0106] The S3 specifically includes:

[0107] Check whether the output port to which the group is connected outward is only the output port Q or the reverse output port QN of the trigger. If not, return to execute the preliminary grouping module;

[0108] If so, the input port connected to the outside of the group is checked. If there is a structure where the adder input is connected to the output of another adder SUM, it is divided into a multiplier or other group.

[0109] Furthermore, the classification and sorting module specifically includes:

[0110] Sort the adders from low to high according to the carry output ports of the adder circuit, connect the ports of the adders to the corresponding ports of the triggers and keep all the output ports short;

[0111] According to the adder type and the logic gate circuit type in the group, the corresponding group is set as a counter or an accumulator to obtain the final classification result of the counter and the accumulator.

[0112] Specifically, according to the adder type and logic gate circuit type in the group, the corresponding group is set as a counter or accumulator, including:

[0113] If there is a full adder or a three-input XOR gate / XNOR gate in the group, the corresponding group is set as an accumulator;

[0114] If there is only a half adder or a two-input XOR gate / XNOR gate in the group, the corresponding group is set as a counter.

[0115] The circuit analysis and search device with a gated clock provided by an embodiment of the present invention can execute the circuit analysis and search method with a gated clock provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0116] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A circuit analysis and search method with a gated clock, characterized in that: include: S1. In a scattered data netlist with connection relationships, distinguish the timing relationships of triggers according to clock gating circuits, and re-screen and group the triggers based on the timing to obtain a trigger grouping result; S2. Dynamically search and locate relevant logic gate circuits based on the bidirectional data flow relationship between the adder and the flip-flop, merge and group the captured logic gate circuits with the corresponding flip-flop circuits, and obtain preliminary grouping results for the counters and accumulators. S3. Verify whether the boundaries of the counter and the accumulator in the preliminary grouping result are complete, and obtain a verified grouping result; S4. Reorder and classify the counters and accumulators in the verified grouping result according to the adder order to obtain a final classification result of the counters and accumulators; The S2 specifically includes: S21. According to the bidirectional data flow relationship between the adder and the trigger, the adder and related logic gate circuits are captured from the scattered data netlist and added to the corresponding trigger group to obtain an adder-trigger group; S22, capturing a simplified logic circuit of an adder from the scattered data netlist, and adding the simplified logic circuit to a corresponding adder-flip-flop group; The S21 includes: Search a preset number of gate-level circuits forward from the grouped trigger input D terminal, and capture the adder and related logic gate circuits in the search path; Search backward for a preset number of gate circuits from the carry output port of the captured adder. If it passes through the adder, continue to search backward for a preset number of gate circuits. If the loop can be closed, the adder and logic gate circuits in the path are merged into the group. Otherwise, reserve a search space at the corresponding port. The S22 includes: Searching for a preset number of gate circuits from the group and before the D end of the unmatched trigger of the adder, and continuing to search for a preset number of gate circuits forward after finding an XOR gate or an XNOR gate, and if all gate circuits can be connected to the carry output port in the group, grabbing all the gate circuits found into the group and filling the reserved search space; Search for a preset number of gate circuits backward from the output port of the trigger. If it passes through other groups, the search is terminated and the port is retained; if it can return to the group, the found gate circuit is captured into the corresponding group.

2. The method according to claim 1, characterized in that Said S1 specifically includes: Classify clock gating circuits according to the number of forward gate-level circuits and reverse gate-level circuits that the clock passes through to the clock input source; Group the flip-flops based on the connection relationship between the timing and flip-flops of the same type of clock gating circuits; Verify the correctness of the classification of flip-flops and clock gating circuits, and arrange the flip-flops and clock gating circuits.

3. The method according to claim 2, characterized in that The triggers are grouped according to the connection relationship between the timing and triggers of the same type of clock gating circuit, including: If the same type of clock gating circuit is connected to a flip-flop through a forward logic gate circuit, the corresponding flip-flop and clock gating are considered to be the same logic; If the same type of clock gating circuit is sequentially connected to a flip-flop through a reverse logic gate circuit, the corresponding flip-flop and clock gating are regarded as opposite logic.

4. The method according to claim 1, wherein The S3 specifically includes: Check whether the output port to which the group is connected outward is only the output port Q or the reverse output port QN of the trigger. If not, return to execute S2. If so, the input port connected to the outside of the group is checked. If there is a structure where the adder input is connected to the output of another adder SUM, it is divided into a multiplier or other group.

5. The method according to claim 1, wherein The S4 specifically includes: Sort the adders from low to high according to the carry output ports of the adder circuit, connect the ports of the adders to the corresponding ports of the triggers and keep all the output ports short; According to the adder type and the logic gate circuit type in the group, the corresponding group is set as a counter or an accumulator to obtain the final classification result of the counter and the accumulator.

6. The method according to claim 5, characterized in that According to the adder type and logic gate type within the group, the corresponding group is set as a counter or accumulator, including: If there is a full adder or a three-input XOR gate / XNOR gate in the group, the corresponding group is set as an accumulator; If there is only a half adder or a two-input XOR gate / XNOR gate in the group, the corresponding group is set as a counter.

7. A circuit analysis and search device with a gated clock, the device being implemented by a circuit analysis and search method with a gated clock according to any one of claims 1 to 6, characterized in that: include: A trigger grouping module is used to distinguish the timing relationship of triggers in a scattered data netlist with connection relationships according to the clock gating circuit, and re-screen and group the triggers based on the timing to obtain the trigger grouping results; The preliminary grouping module is used to dynamically find and locate relevant logic gate circuits based on the bidirectional data flow relationship between the adder and the trigger, merge and group the captured logic gate circuits with the corresponding trigger circuits, and obtain the preliminary grouping results of the counters and accumulators; A verification module, configured to verify whether the boundaries of the counters and accumulators in the preliminary grouping result are complete, and obtain a verified grouping result; The classification and sorting module is used to reorder and sort the counters and accumulators in the verified grouping results according to the adder order to obtain the final classification results of the counters and accumulators.

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