Delay analysis method and system and storage medium

Abstract

The invention relates to the field of integrated circuit design, in particular to a delay analysis method and system and a storage medium, and the method comprises the steps: providing an output voltage waveform of a to-be-analyzed device unit in a circuit, and dividing a low-level voltage value and a high-level voltage value of the output voltage waveform into a plurality of voltage intervals; providing a current sampling point adjacent to the end point of the voltage interval, and performing interpolation calculation on the current sampling point through an interpolation method of introducing a current sampling point derivative value to obtain a current value at the end point of the voltage interval; effective capacitance of the device unit is provided, the voltage jump time of each voltage interval is calculated through the combination of the current value and the effective capacitance, and the voltage conversion time and the delay time of the device unit are calculated through the voltage jump time. According to the invention, the influence of noise data in a voltage interval is reduced, so that a smoother output voltage waveform is obtained, and the obtained output voltage waveform and delay time are more accurate.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to a delay analysis method, system and storage medium.

Background Art

[0002] Timing analysis is a determining factor in the design process of very large scale integrated circuit chips and is an essential part in the entire back-end design process. If the timing analysis of a circuit cannot converge, the designed chip will have functional errors and cannot complete the expected processing work, resulting in a complete failure of the entire design process.

[0003] Timing analysis includes delay analysis, clock analysis, constraint analysis and timing optimization. Among them, delay analysis refers to calculating the propagation delay time of a signal from one component to another, which includes input delay, output delay and internal delay, etc.

[0004] Regarding the delay analysis of gate devices and interconnects in a circuit, currently the delay analysis of gate devices mainly relies on the delay database obtained from experimental simulations provided by manufacturers, and the delay of interconnects is analyzed based on their own capacitance, resistance and inductance characteristics.

[0005] With the progress of modern technology processes and the reduction of transistor sizes, circuit design has become increasingly complex, and it is becoming more and more important to improve the accuracy of circuit timing analysis. The delay databases provided by manufacturers are also becoming increasingly rich, not limited to traditional non-linear fitting table data, but providing relatively more waveform sampling point information data based on the current input transition time and subsequent load circuits as the data input for the delay analysis program.

[0006] Delay analysis checks according to the transition times corresponding to the output voltage waveforms of gate devices and interconnects. However, gate devices and interconnects affect each other, and at the same time, due to the influence of noise data, there are problems with the waveform continuity of the output voltage waveforms during the voltage transition time, resulting in inaccurate final delay analysis results.

Summary of the Invention

[0007] To solve the problem of inaccurate delay analysis in integrated circuit design, the present invention provides a delay analysis method, which includes:

[0008] Providing the output voltage waveform of a device unit to be analyzed in a circuit, and dividing the voltage range between the low-level voltage value and the high-level voltage value of the output voltage waveform into multiple voltage intervals;

[0009] Providing current sampling points adjacent to the endpoints of the voltage intervals, and performing interpolation calculation on the current sampling points by introducing an interpolation method of the derivative values of the current sampling points to obtain the current values at the endpoints of the voltage intervals;

[0010] Provide the effective capacitance of the device unit, calculate the voltage jump time of each voltage interval through the current value combined with the effective capacitance, and calculate the voltage conversion time and delay time of the device unit through the voltage jump time.

[0011] Preferably, parse the timing library to obtain information about the device unit, where the information includes the output current waveform of the device unit, and convert the output current waveform to obtain the output voltage waveform.

[0012] Preferably, the interpolation method includes the Hermite interpolation method.

[0013] Preferably, the device unit includes a gate device and an interconnect network. Provide the information of the gate device and the parasitic parameters of the interconnect network, and comprehensively calculate the effective capacitance.

[0014] Preferably, the low-level voltage value and the high-level voltage value are respectively set to 30% and 70% of the supply voltage of the device unit.

[0015] Preferably, set a voltage threshold point in the voltage interval, and obtain the delay time of the device unit by subtracting the time required for the input voltage to reach the voltage threshold point obtained from the timing library from the actual time required when calculating to the voltage threshold point.

[0016] Preferably, fit the first output voltage waveform of the device unit according to the voltage conversion time and the voltage interval;

[0017] The device unit is connected to the receiving pin of another device unit through an interconnect network, and bring the first output voltage waveform into the input-output conversion function of the interconnect network to obtain the second output voltage waveform of the interconnect network;

[0018] Obtain the corresponding voltage conversion time according to the second output voltage waveform, obtain the corresponding effective capacitance according to the voltage conversion time, and recalculate the first output voltage waveform according to the obtained effective capacitance;

[0019] Preferably, set a convergence threshold. When the difference between the voltage conversion time of the recalculated first output voltage waveform and the voltage conversion time of the previous first output voltage waveform is not less than the convergence threshold, continue to iteratively calculate the second output voltage waveform, obtain a new effective capacitance, and recalculate the first output voltage waveform.

[0020] The present invention also provides a delay analysis system for solving the above problems and for the above-mentioned delay analysis method. The delay analysis system includes:

[0021] A data processing module, configured to provide an output voltage waveform of a device unit to be analyzed in a circuit, and divide a voltage range between a low-level voltage value and a high-level voltage value of the output voltage waveform into a plurality of voltage intervals;

[0022] A calculation module, configured to provide current sampling points adjacent to endpoints of the voltage intervals, and perform interpolation calculation on the current sampling points by an interpolation method introducing derivative values of the current sampling points to obtain current values at the endpoints of the voltage intervals;

[0023] A delay analysis module, configured to provide an effective capacitance of the device unit, calculate voltage jump times of the voltage intervals through the current values in combination with the effective capacitance, and calculate a voltage conversion time and a delay time of the device unit through the voltage jump times.

[0024] The present invention also provides a storage medium for solving the above problems, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the above-described delay analysis method is implemented.

[0025] Compared with the prior art, the delay analysis method, system, and storage medium of the present invention have the following advantages:

[0026] 1. In the calculation process of obtaining the current curve corresponding to the voltage interval by the delay analysis method provided by the present invention, interpolation calculation is performed on the current sampling points by an interpolation method introducing derivative values of the current sampling points to obtain a smoother current curve at the voltage interval, reducing the influence of noise data in the voltage interval, and further obtaining a smoother output voltage waveform, so that the obtained output voltage waveform and delay time are more accurate;

[0027] At the same time, the delay analysis method can obtain accurate delay analysis results through a finite number of divisions of the voltage interval, avoiding more detailed divisions of the voltage interval, thereby reducing the calculation amount and the time required for calculation.

[0028] 2. The interpolation method used in the delay analysis method provided by the present invention includes the Hermite interpolation method. Hermite interpolation not only uses function values of current sampling points for interpolation, but also utilizes derivative information of the function;

[0029] Since Hermite interpolation takes into account derivative values of current sampling points at the same time, the obtained interpolation curve is usually smoother. This smoothness helps to reduce interpolation errors and is more convenient for performing operations and analyses on the curve.

[0030] At the same time, Hermite interpolation can be used for irregular and non-uniform data sets and is applicable to various data distribution situations. It can handle missing data, outliers, and noise, and has strong adaptability and robustness. In the present invention, Hermite interpolation can effectively reduce the influence of noise data in the voltage range on the calculation result and improve the calculation accuracy.

[0031] 3. When analyzing multiple device units by the delay analysis method provided by the present invention, by considering the mutual influence between the gate devices and the interconnect network in the device units, the effective capacitance value of the calculated voltage range is updated to obtain a new output voltage waveform, and the calculation is iterated repeatedly until the output voltage conversion time and the effective capacitance value converge, reducing the mutual influence between the gate devices and the interconnect network, making the output voltage waveform more accurate, and improving the accuracy of delay analysis.

[0032] 4. The present invention also provides a delay analysis system, which has the same beneficial effects as the above delay analysis method and will not be elaborated here.

[0033] 5. The present invention also provides a storage medium, on which a computer program is stored. When the computer program is executed, the above delay analysis method is implemented, and it has the same beneficial effects as the above delay analysis method and will not be elaborated here.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 It is a flowchart of steps S1 - S3 of a delay analysis method provided by the first embodiment of the present invention.

[0036] 1] Figure 2 It is a schematic diagram of voltage range division in the output voltage waveform provided by the first embodiment of the present invention.

[0037] Figure 3 It is a loop flowchart of step S4 of a delay analysis method provided by the first embodiment of the present invention.

[0038] Figure 4 It is a structural diagram of a delay analysis system provided by the second embodiment of the present invention.

[0039] Figure 5 It is a structural diagram of a storage medium provided by the third embodiment of the present invention.

[0040] Description of the reference numerals in the drawings:

[0041] 1. Delay analysis system; 2. Storage medium;

[0042] 201. Data processing module; 202. Calculation module; 203. Delay analysis module;

[0043] 301. Memory; 302. Processor; 303. Computer program.

Specific embodiments

[0044] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0045] Regarding the delay analysis of gate devices and interconnects in a circuit, currently, the delay analysis of gate devices mainly relies on the delay database obtained from experimental simulations provided by manufacturers, and the delay of interconnects is analyzed based on their own capacitance, resistance, and inductance characteristics.

[0046] The delay analysis checks according to the jump times corresponding to the output voltage waveforms of gate devices and interconnects. However, gate devices and interconnects affect each other, and at the same time, due to the influence of noise data, there are problems with the waveform continuity of the output voltage waveforms during the voltage transition time, resulting in inaccurate final delay analysis results.

[0047] Please refer to Figure 1 and Figure 2 For solving the above problems, a first embodiment of the present invention provides a delay analysis method, which includes:

[0048] S1: Provide the output voltage waveform of the device unit to be analyzed in the circuit, and divide the voltage range between the low-level voltage value and the high-level voltage value of the output voltage waveform into multiple voltage intervals;

[0049] S2: Provide the current sampling points adjacent to the endpoints of the voltage intervals, and perform interpolation calculations on the current sampling points by introducing the interpolation method of the derivative values of the current sampling points to obtain the current values at the endpoints of the voltage intervals;

[0050] S3: Provide the effective capacitance of the device unit, calculate the voltage transition time of each voltage interval through the current value in combination with the effective capacitance, and calculate the voltage conversion time and delay time of the device unit through the voltage transition time.

[0051] In the calculation process of obtaining the current curve corresponding to the voltage range by the delay analysis method provided by the present invention, interpolation calculation is performed on the current sampling points by introducing the interpolation method of the derivative value of the current sampling points. By introducing more current sampling points through interpolation, the fitted current curve is made to more closely approximate the actual current change. At the same time, the derivative value of the current sampling point is considered in the interpolation. By adding the derivative information of the interpolation sampling points, the slope of the interpolation function at the known sampling points is made closer to the slope of the actual function. The role of the derivative can provide more local information, making the interpolation function more accurate and smooth within the interpolation region, obtaining a smoother current curve at the voltage range, reducing the influence of noise data in the voltage range, and thus obtaining a smoother output voltage waveform, making the obtained output voltage waveform and delay time more accurate;

[0052] At the same time, this delay analysis method can obtain accurate delay analysis results by dividing the voltage range a finite number of times, avoiding more detailed division of the voltage range, thereby reducing the calculation amount and the time required for calculation.

[0053] Further, in the above step S2, the interpolation method includes the Hermite interpolation method. Since the Hermite interpolation considers the derivative value of the current sampling point at the same time, in the Hermite interpolation, the derivative provides additional information and can better fit the curve or surface. By providing additional derivative information, the interpolation error can be reduced and the accuracy of the interpolation function can be improved. The Hermite interpolation can generate a higher-order interpolation polynomial and use the derivative information to control the derivative value of the interpolation function. This makes the smoothness of the interpolation function better within the interpolation region. This smoothness helps to reduce the interpolation error and is more convenient for performing operations and analysis on the curve;

[0054] At the same time, noise data will be generated during the operation of the device unit. Noise data usually refers to signal interference or errors introduced by factors such as the environment, device characteristics, or electromagnetic interference. The noise data may cause a slight shift in time between the input and output signals. These timing shifts will affect the accuracy of the delay analysis;

[0055] At the same time, the noise data can introduce clock jitter, that is, the periodic change of the clock signal. The clock jitter may cause the arrival time of some signals to be advanced or delayed, thus affecting the result of the delay analysis. The noise signal can have a negative impact on the integrity of the signal. In high-speed signal transmission, the noise may cause waveform distortion, amplitude change, or oscillation of the signal, which will directly affect the accuracy of the delay analysis.

[0056] In the present invention, the derivative allows Hermite interpolation to better handle singularities or discontinuities. By providing derivative information near the singularity, the interpolation function can better adapt to the local characteristics at the singularity. The derivative information enables Hermite interpolation to better control the gradient and curvature of the interpolation function. Hermite interpolation can effectively filter noise data, avoid introducing mutant sampling points caused by noise data, effectively reduce the impact of noise data on the calculation results in the voltage range, and improve the calculation accuracy.

[0057] It should be noted that Hermite interpolation is an interpolation method that uses the function values and derivative values of interpolation nodes to construct a polynomial to approximate a known function. Different from traditional interpolation methods, Hermite interpolation not only uses function values for interpolation but also utilizes the derivative information of the function. In Hermite interpolation, the function values and derivative values at the interpolation nodes are both known. With this information, a polynomial can be constructed such that it exactly matches the known function values and derivative values at each interpolation node. This can more accurately approximate the behavior of the function near the interpolation nodes. At the same time, Hermite interpolation can be used for irregular and non-uniform data sets and is applicable to various data distribution situations. It can handle missing data, outliers, and noise, and has strong adaptability and robustness.

[0058] It can be understood that in step S1, by parsing the timing library, information about the device unit is obtained. The information includes the output current waveform of the device unit, and the output voltage waveform is obtained by converting the output current waveform.

[0059] It should be noted that in chip design, the timing library is a key component that contains the timing information and delay models of various logic elements. The timing library contains the timing characteristics of standard cells, such as the delay data and related timing information of logic gates, clock flip-flops, etc.

[0060] It can be understood that in the above step S3, the device unit includes a gate device and an interconnection network. Information about the gate device and the parasitic parameters of the interconnection network are provided. Parasitic parameters refer to parameters such as capacitance, inductance, and resistance inadvertently introduced into circuit elements or structures. The above parasitic parameters specifically include the capacitance, conductance, and inductance of the interconnection network, etc. The effective capacitance of the device unit is calculated by integrating the parasitic parameters of the interconnection network and the information of the gate device. The effective capacitance refers to the capacitance value within a specific voltage range, which represents the response ability of the capacitor to current within this voltage range.

[0061] It can be understood that in step S1, the low-level voltage value and the high-level voltage value are respectively set to 30% and 70% of the supply voltage of the device unit. The voltage waveform changes smoothly in the range of 30% to 70%, which can reduce the influence of noise data.

[0062] Within this interval, the signal changes at a relatively slow rate. Compared with steeper rising or falling edges, the corresponding current change is also smaller. A smaller current change means fewer high-frequency components and less noise. Noise data refers to the unwanted interference signals in a circuit or system. It can come from multiple sources, such as power supply fluctuations, interfering signal lines, environmental radiation, etc. Noise data will introduce signal uncertainty and distortion, affecting the performance of the system and the reliability of the data. When the voltage waveform changes gently, that is, within the interval of 30% to 70%, the current change is relatively small and the noise immunity is relatively strong. This is because when the voltage changes slowly, the system is less affected by noise signals. A smaller current change means a relatively lower noise response. This makes the signal less likely to be affected by noise during transmission, which is more conducive to maintaining the integrity and accuracy of the signal. It can reduce the interference of noise signals, improve the signal quality and the stability of the system, thereby reducing the negative impact on the results.

[0063] Understandably, a voltage threshold point is set within the voltage interval in step S3 above. By calculating the actual time required when reaching the voltage threshold point and subtracting the time required for the input voltage to reach the voltage threshold point obtained from the timing library, the delay time of the device unit is obtained.

[0064] Furthermore, the voltage threshold point is set to 50% of the supply voltage. By determining the effective edge of the voltage interval, where the effective edge specifically refers to the voltage starting point to the voltage threshold point of the voltage interval when calculating the delay time, the calculation amount of the delay calculation can be further reduced and the accuracy can be improved.

[0065] Understandably, please refer to Figure 3 , this delay analysis method further includes step S4, and S4 specifically includes:

[0066] S41: Fit the first output voltage waveform of the device unit according to the voltage conversion time and the voltage interval;

[0067] S42: The device unit is connected to the receiving pin of another device unit through an interconnection network, and the first output voltage waveform is substituted into the input-output conversion function of the interconnection network to obtain the second output voltage waveform of the interconnection network;

[0068] S43: Obtain the corresponding voltage conversion time according to the second output voltage waveform, obtain the corresponding effective capacitance according to the voltage conversion time, and recalculate the first output voltage waveform according to the obtained effective capacitance.

[0069] S44: Set a convergence threshold. When the difference between the voltage conversion time of the newly calculated first output voltage waveform and the voltage conversion time of the previous first output voltage waveform is not less than the convergence threshold, continue the iterative calculation to obtain a second output voltage waveform, obtain a new effective capacitance, and recalculate the first output voltage waveform.

[0070] S45: When the first output voltage waveform converges, calculate the delay time of the device unit according to the first output voltage waveform.

[0071] When step S4 analyzes multiple device units, by considering the mutual influence between the gate devices and the interconnect network in the device units, update the effective capacitance value of the calculated voltage interval, obtain a new output voltage waveform, and repeatedly perform iterative calculations until the output voltage conversion time and the effective capacitance value converge, reducing the mutual influence between the gate devices and the interconnect network, making the output voltage waveform more accurate, and improving the accuracy of delay analysis.

[0072] In the process of obtaining the current curve corresponding to the voltage interval provided by the delay analysis method of the present invention, for the current sampling points, interpolation calculation is performed by introducing an interpolation method of the derivative value of the current sampling points, obtaining a smoother current curve at the voltage interval, reducing the influence of noise data in the voltage interval, and further obtaining a smoother output voltage waveform, making the obtained output voltage waveform and delay time more accurate;

[0073] At the same time, this delay analysis method can obtain accurate delay analysis results through a finite number of voltage interval divisions, avoiding more detailed divisions of the voltage interval, thereby reducing the calculation amount and the time required for calculation.

[0074] When this delay analysis method analyzes multiple device units, by considering the mutual influence between the gate devices and the interconnect network in the device units, update the effective capacitance value of the calculated voltage interval, obtain a new output voltage waveform, and repeatedly perform iterative calculations until the output voltage conversion time and the effective capacitance value converge, reducing the mutual influence between the gate devices and the interconnect network, making the output voltage waveform more accurate, and improving the accuracy of delay analysis.

[0075] Please refer to Figure 4 , the second embodiment of the present invention further provides a delay analysis system 1, and the delay analysis system 1 includes:

[0076] A data processing module 201, configured to provide an output voltage waveform of a device unit to be analyzed in a circuit, and divide a voltage value between the low-level voltage value and the high-level voltage value of the output voltage waveform into multiple voltage intervals;

[0077] A calculation module 202 is configured to provide current sampling points adjacent to the endpoints of the voltage interval, and perform interpolation calculation on the current sampling points by an interpolation method introducing the derivative values of the current sampling points to obtain the current values at the endpoints of the voltage interval;

[0078] A delay analysis module 203 is configured to provide the effective capacitance of the device unit, calculate the voltage jump time of each voltage interval based on the current value and the effective capacitance, and calculate the voltage conversion time and the delay time of the device unit based on the voltage jump time.

[0079] Please refer to Figure 5 , a third embodiment of the present invention further provides a storage medium 2, including a memory 301, a processor 302, and a computer program 303 stored on the memory 301 and executable on the processor 302. When the processor 302 executes the computer program 303, a delay analysis method is implemented.

[0080] The storage medium 2 provided by the third embodiment of the present invention has the same beneficial effects as the above-mentioned delay analysis method, and will not be elaborated here.

[0081] Understandably, according to the embodiments disclosed in the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the methods of the present application are performed. It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. Computer-readable storage media include, for example, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present application, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program codes. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or component. The program codes contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0082] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or, it can be connected to an external computer (for example, by using an Internet service provider to connect through the Internet).

[0083] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0084] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0085] In various embodiments of the present invention, it should be understood that the magnitude of the sequence numbers of the above processes does not necessarily mean the inevitable sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0086] The flowcharts and block diagrams in the accompanying drawings of the present invention illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0087] Compared with the prior art, a delay analysis method, system, and storage medium of the present invention have the following advantages:

[0088] 1. In the calculation process of obtaining the current curve corresponding to the voltage range in the delay analysis method provided by the present invention, interpolation calculation is performed on the current sampling points by introducing an interpolation method of the derivative value of the current sampling points, obtaining a smoother current curve at the voltage range, reducing the influence of noise data in the voltage range, and thus obtaining a smoother output voltage waveform, making the obtained output voltage waveform and delay time more accurate;

[0089] At the same time, this delay analysis method can obtain accurate delay analysis results by dividing the voltage range a finite number of times, avoiding more detailed division of the voltage range, thereby reducing the calculation amount and the time required for calculation.

[0090] 2. The interpolation method used in the delay analysis method provided by the present invention includes the Hermite interpolation method. Hermite interpolation not only uses the function values of the current sampling points for interpolation, but also utilizes the derivative information of the function;

[0091] Since Hermite interpolation takes into account the derivative values of the current sampling points at the same time, the obtained interpolation curve is usually smoother. This smoothness helps to reduce the interpolation error and is more convenient for performing operations and analysis on the curve.

[0092] At the same time, Hermite interpolation can be used for irregular and uneven data sets and is applicable to various data distribution situations. It can handle missing data, outliers, and noise, and has strong adaptability and robustness. In the present invention, Hermite interpolation can effectively reduce the influence of noise data in the voltage range on the calculation results and improve the calculation accuracy.

[0093] 3. When the delay analysis method provided by the present invention analyzes multiple device units, by considering the mutual influence between the gate devices and the interconnect network in the device units, the effective capacitance value of the calculated voltage range is updated to obtain a new output voltage waveform, and the calculation is iterated repeatedly until the output voltage transition time and the effective capacitance value converge, reducing the mutual influence between the gate devices and the interconnect network, making the output voltage waveform more accurate, and improving the accuracy of delay analysis.

[0094] 4. The present invention also provides a delay analysis system, which has the same beneficial effects as the above delay analysis method and will not be elaborated here.

[0095] 5. The present invention also provides a storage medium, on which a computer program is stored. When the computer program is executed, the above delay analysis method is implemented, and it has the same beneficial effects as the above delay analysis method and will not be elaborated here.

[0096] The above has introduced in detail a delay analysis method, system and storage medium disclosed in the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A delay analysis method, characterized in that, The method includes: Providing an output voltage waveform of a device unit to be analyzed in a circuit, and dividing a range between a low-level voltage value and a high-level voltage value of the output voltage waveform into a plurality of voltage intervals; Providing current sampling points adjacent to endpoints of the voltage intervals, and performing interpolation calculation on the current sampling points by an interpolation method introducing derivative values of the current sampling points to obtain current values at the endpoints of the voltage intervals; Providing an effective capacitance of the device unit, calculating voltage jump times of the voltage intervals through the current values in combination with the effective capacitance, and calculating a voltage conversion time and a delay time of the device unit through the voltage jump times.

2. The delay analysis method according to claim 1, characterized in that: Parsing a timing library to obtain information of the device unit, where the information includes an output current waveform of the device unit, and converting the output current waveform to obtain the output voltage waveform.

3. The delay analysis method according to claim 1, characterized in that: The interpolation method includes the Hermit interpolation method.

4. A delay analysis method according to claim 1, characterized in that: The device unit includes a gate device and an interconnect network. Providing information of the gate device and parasitic parameters of the interconnect network, and comprehensively calculating to obtain the effective capacitance.

5. The delay analysis method according to claim 1, characterized in that: The low-level voltage value and the high-level voltage value are respectively set to 30% and 70% of the supply voltage of the device unit.

6. The delay analysis method according to claim 2, wherein: Setting a voltage threshold point in the voltage interval, and subtracting the time required for the input voltage to reach the voltage threshold point obtained from the timing library from the actual time required when calculating to the voltage threshold point to obtain the delay time of the device unit.

7. A delay analysis method according to claim 4, characterized in that: Fitting the first output voltage waveform of the device unit according to the voltage conversion time and the voltage interval; The device unit is connected to a receiving pin of another device unit through an interconnect network, and substituting the first output voltage waveform into an input-output conversion function of the interconnect network to obtain a second output voltage waveform of the interconnect network; Obtaining a corresponding voltage conversion time according to the second output voltage waveform, obtaining a corresponding effective capacitance according to the voltage conversion time, and recalculating the first output voltage waveform according to the obtained effective capacitance.

8. A delay analysis method according to claim 7, characterized in that: Setting a convergence threshold. When a difference between the voltage conversion time of the recalculated first output voltage waveform and the voltage conversion time of the previous first output voltage waveform is not less than the convergence threshold, continuously performing iterative calculation to obtain the second output voltage waveform, obtaining a new effective capacitance and recalculating the first output voltage waveform.

9. A delay analysis system for implementing a delay analysis method according to any one of claims 1-8, characterized in that, Including: A data processing module, configured to provide an output voltage waveform of a device unit to be analyzed in a circuit, and divide a range between a low-level voltage value and a high-level voltage value of the output voltage waveform into a plurality of voltage intervals; A calculation module, configured to provide current sampling points adjacent to endpoints of the voltage intervals, and perform interpolation calculation on the current sampling points by an interpolation method introducing derivative values of the current sampling points to obtain current values at the endpoints of the voltage intervals; A delay analysis module, configured to provide an effective capacitance of the device unit, calculate voltage jump times of the voltage intervals through the current values in combination with the effective capacitance, and calculate a voltage conversion time and a delay time of the device unit through the voltage jump times.

10. A storage medium, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements a delay analysis method as described in any one of claims 1-8.

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