Packaging method for reducing RDSON resistance value of chip based on multi-layer metal structure

Abstract

The invention discloses a packaging method for reducing the RDSON resistance value of a chip based on a multi-layer metal structure, and relates to the technical field of chip packaging, a chip packaging structure based on the multi-layer metal structure comprises a chip base layer, a multi-layer metal layer and an electroplated layer which are arranged in a linear direction, and the multi-layer metal layer comprises an adhesion layer, a connection layer and a combination layer; comprising the following steps that cleaning pretreatment is conducted in a plasma cleaning mode, variation detection and analysis are conducted, and first-step variation analysis and / or second-step variation analysis are / is conducted after detection data are obtained; sputtering deposition of the multiple metal layers is carried out through the physical vapor deposition technology, and sputtering parameters are intelligently adjusted; coating photoresist on the surface of the top end of the multi-layer metal layer, and performing exposure and development; depositing thick copper by using an electroplating process; according to the method, the deposition quality of each metal layer can be improved, so that the stability and the performance of the multi-layer metal structure are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically to a packaging method for reducing the RDSON resistance value of a chip based on a multi-layer metal structure. Background Art

[0002] Wafer-Level Chip Scale Packaging (WLCSP) is an advanced semiconductor packaging technology; its characteristic lies in directly completing most or all of the packaging process steps on the wafer. The size of the single package obtained after final cutting is almost the same as the size of the chip itself, that is, the chip size, and the lead frame or substrate and bonding wires commonly used in traditional packaging are omitted.

[0003] In addition, the size of the RDSON of a WLCSP chip is one of the important indicators for judging the performance of the chip. That is, reducing the RDSON resistance value also increases the conduction current of the chip. Specifically, WLCSP reduces the RDSON resistance value of the chip in the following aspects: one is omitting the bonding wire resistance, the second is constructing a three-dimensional low-resistance path through copper pillars and a Redistribution Layer (RDL), and the third is optimizing heat dissipation.

[0004] Currently, a multi-layer metal sputtering combined with electroplating process is used for the packaging of chip RDSON. However, how to accurately control the thickness and quality of each metal layer to ensure the stability and performance of the multi-layer metal structure has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a packaging method for reducing the RDSON resistance value of a chip based on a multi-layer metal structure to solve the problems raised in the above background art.

[0006] To solve the above technical problems, the present invention provides the following technical solution: A packaging method for reducing the RDSON resistance value of a chip based on a multi-layer metal structure, including the following steps: S1: Perform cleaning pretreatment by means of plasma cleaning, and conduct abnormal detection and analysis. After obtaining the detection data, conduct the first abnormal analysis and / or the second abnormal analysis; S2: Use physical vapor deposition technology to perform sputtering deposition of multi-layer metal layers, and intelligently adjust the sputtering parameters. The sputtering parameters include sputtering power P and working pressure F, and both the sputtering power and the working pressure are positively correlated with the deposition rate.

[0007] The chip packaging structure based on a multi-layer metal structure includes a chip base layer, multi-layer metal layers, and an electroplating layer arranged in a straight line direction. When performing pre-cleaning, the plasma technology in the cleaning chamber is used to remove contaminants such as oxides and / or organic substances on the surface of the chip base layer to ensure the adhesion of the multi-layer metal layers. Subsequently, a vacuum manipulator is used to send the chip base layer into a magnetron sputtering device for subsequent deposition processes.

[0008] The fixed movement path that the chip base layer passes through during the process of moving from the pre-cleaning process to the sputtering deposition process is determined and denoted as the movement path distance L. A p point is set on the movement path distance L. The position of the p point is used for the first mutation analysis, and several detection points corresponding to the surface of the chip base layer are set at the position of the p point. The p value is the ratio of the distance from the starting point to the ending point of the movement path, and 0 < p ≤ 1. The first mutation analysis is used to judge the qualified situation of the oxide layer thickness at each detection point of the chip base layer and the normal situation of the corresponding total mutation value. The second mutation analysis calculates the terminal oxidation data of the chip base layer based on the condition that p is not equal to 1 and the total mutation value is normal, and then compares it with the oxide layer thickness limit value and the total mutation limit value respectively to select the corresponding process. The corresponding processes include sputtering, replacement, and local cleaning.

[0009] The present invention further describes that it also includes: S3: Apply photoresist on the top surface of the multi-layer metal layer and perform exposure and development. S4: Deposit thick copper using electroplating technology, and then peel and anneal. S5: Prepare solder bumps for connecting the PCB board, then perform wafer dicing, and conduct corresponding electrical performance tests.

[0010] The present invention further describes that the pre-cleaning uses a cleaning chamber, the sputtering deposition of the multi-layer metal layer uses a magnetron sputtering device. A vacuum manipulator is arranged between the cleaning chamber and the magnetron sputtering device. A multi-target sputtering chamber is set in the magnetron sputtering device. Argon ions are continuously bombarded on the metal target to continuously deposit different materials. The adhesion layer is used to block the diffusion of copper atoms, the connection layer can be used as the seed layer for copper electroplating to provide a conductive substrate, and the bonding layer is used to reduce the starting resistance of electroplating to ensure the uniform growth of the electroplated copper layer.

[0011] The present invention further describes that a first detection module is set at one place in the fixed movement path of the vacuum manipulator. The first detection module is composed of several ranging units. The outer dimension of the first detection module is consistent with the chip base layer, and several ranging units are evenly laid inside the outer circle. The ranging unit uses infrared emission and reception technology to detect the oxidation degree of the surface of the chip base layer.

[0012] The present invention is further described as follows. The first detection module is used to measure the thickness change of the chip base layer, which is denoted as the total abnormal change value. The statistical formula for the total abnormal change value of the chip base layer is ; n is the total number of distance measurement units laid outside the outer circle of the first detection module, i is the marking serial number of the distance measurement unit, i takes an integer between 1 and n, and h i represents the thickness of the oxide layer measured by the distance measurement unit with the marking serial number i.

[0013] The present invention is further described as follows. It is set that h s is the limit value of the oxide layer thickness. When h i > h s , it indicates that the thickness of the oxide layer at the i-th place of the chip base layer is unqualified; It is set that s is the limit value of the total abnormal change. When is between 0 - s, it indicates that the total abnormal change value is normal; the moving path distance L corresponds to the distance between the suction point of the vacuum manipulator in the cleaning chamber as the starting point of the moving path and the placement point of the magnetron sputtering equipment as the end point of the moving path. The p is the proportion of the path distance from the starting point to the position point where the first detection module is located in the moving path distance L.

[0014] The present invention is further described as follows. The content of the first-step abnormal change analysis is: Case I: If h i ≤ h s , 0 ≤ ≤ s, it indicates that the thickness of the oxide layer at each detection point of the chip base layer is qualified, and the total abnormal change value is normal; Case II: If h i ≤ h s , > s, it indicates that the thickness of the oxide layer at each detection point of the chip base layer is qualified, but the total abnormal change value exceeds the normal range; Case III: If there is at least one place where h i > h s , 0 ≤ ≤ s, it indicates that there is at least one detection point on the chip base layer where the thickness of the oxide layer is unqualified, but the total abnormal change value is normal; Case IV: If there is at least one place where h i > h s , > s, it indicates that there is at least one detection point on the chip base layer where the thickness of the oxide layer is unqualified, and the total abnormal change value exceeds the normal range.

[0015] The present invention further illustrates that the second step of mutation analysis includes: When p is not equal to 1 and 0≤ ≤ s, the second step of asynchronous analysis is required; For cases I and III, calculate the terminal oxidation data, and then compare them with the oxide layer thickness limit and the total variation limit to further determine the case: when , 0≤ ≤ When s, it still belongs to case I, and the sputtering process in S2 is performed; When there is , 0≤ ≤ At s, it still belongs to situation III. The vacuum robot will drive the chip substrate back to the cleaning chamber to perform plasma local cleaning at the chip substrate position corresponding to i, and then perform the sputtering process in S2.

[0016] The present invention further states that when p is equal to 1 or when p is not equal to 1 and > s, the second step of asynchronous analysis is not performed.

[0017] The present invention further states that the ideal layer thickness of the corresponding metal layer is recorded as A, A=V*T+§, where V is the deposition rate, T is the deposition time, and § is the compensation coefficient used to obtain the ideal layer thickness under the set deposition time; During the sputtering process, an ellipsometer is used to monitor the actual layer thickness of the corresponding metal layer in real time, recorded as As. During the monitoring process, the actual layer thickness As is compared with the ideal layer thickness A, and the power and / or working pressure are adjusted in real time according to the comparison results.

[0018] Compared with the prior art, the beneficial effects achieved by the present invention are: vacuum transfer is used to transfer the chip substrate between the cleaning chamber and the magnetron sputtering equipment of the present invention, oxidation data is pre-detected during the transfer process, and the first step variation analysis and / or the second step variation analysis are performed; not only can the position point where the oxide layer thickness is unqualified be clearly located, but the terminal oxidation data of the chip substrate can also be inferred during the movement path of the vacuum manipulator, and remedial measures can be inferred in advance, which can not only save processing time but also ensure the adhesion of multiple metal layers in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 It is a schematic diagram of the chip packaging structure of the present invention; Figure 2 is a schematic diagram of the encapsulation method of the present invention; Figure 3 is a schematic diagram of the first detection module of the present invention; Figure 4 is a schematic diagram of the moving path of the vacuum manipulator of the present invention; In the figure: 1. Chip base layer; 2. Multilayer metal layer; 21. Adhesion layer; 22. Connection layer; 23. Bonding layer; 3. Plating layer; 4. First detection module; 41. Distance measurement unit. Specific embodiments

[0020] The following further non-limiting detailed description of the technical solution of the present invention is made in conjunction with the preferred embodiments and their accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] Please refer to Figure 1 , the present invention provides a technical solution: an encapsulation method for reducing the RDSON resistance value of a chip based on a multilayer metal structure. This encapsulation method is applied to a chip encapsulation structure based on a multilayer metal structure, including a chip base layer 1. A multilayer metal layer 2 is provided on the top surface of the chip base layer 1, and a plating layer 3 with a certain thickness is provided on the upper surface of the multilayer metal layer 2. Refer to Figure 1 , the multilayer metal layer 2 includes an adhesion layer 21, a connection layer 22, and a bonding layer 23 arranged in sequence above the chip base layer 1. The adhesion layer 21 is preferably made of Ti metal, the connection layer 22 is preferably a Ni metal layer, and the bonding layer 23 is preferably an Ag metal layer. The thickness of the adhesion layer 21 is designed as a, the thickness of the connection layer 22 is designed as 2a, and the bonding layer 23 is designed as 3a - 5a; wherein, the multilayer metal layer 2 is formed in a magnetron sputtering device, and a physical vapor deposition technology is adopted, that is, the movement of electrons is constrained by an orthogonal electromagnetic field to improve the gas ionization rate, thereby enhancing the sputtering efficiency; based on the above-mentioned multilayer metal sputtering and electroplating processes, the deposition of the multilayer metal layer 2 and the plating layer 3 is realized, so as to achieve ultra-low resistance vertical interconnection of copper pillar bumps, cancel the bonding wires in the traditional encapsulation, and thus effectively reduce the RDSON resistance value of the chip.

[0022] Refer to Figure 2 , the specific encapsulation method for reducing the RDSON resistance value of the chip based on the multilayer metal structure is as follows: S1: Use plasma cleaning method for cleaning pretreatment, and perform abnormal detection and analysis.

[0023] The cleaning chamber for the pre - cleaning of the chip substrate 1 and the magnetron sputtering equipment for the deposition of the multi - layer metal layer 2 can be designed in a cluster or separately; however, a vacuum transfer method is selected to transfer the chip substrate 1 between the cleaning chamber and the magnetron sputtering equipment. The cleaning chamber uses a low - pressure environment, and the magnetron sputtering equipment uses a vacuum environment; During the pre - cleaning process, plasma technology in the cleaning chamber is used to remove pollutants such as oxides and / or organic substances on the surface of the chip substrate 1 to ensure the adhesion of the multi - layer metal layer 2; subsequently, a vacuum manipulator is used to send the chip substrate 1 into the magnetron sputtering equipment for subsequent deposition processes.

[0024] Among them, the pressure inside the vacuum manipulator is not higher than 10 -5 Pa. A first detection module 4 is set at one place in the fixed movement path of the vacuum manipulator to measure the thickness change of the chip substrate 1, which is recorded as the total abnormal change value , reference Figure 3 , the first detection module consists of several ranging units 41. The outer - ring size of the first detection module 4 is consistent with that of the chip substrate 1. The several ranging units 41 are evenly laid inside the outer ring. The ranging unit 41 uses infrared emission and reception technology to detect the oxidation degree of the surface of the chip substrate 1. The surface oxidation degree is determined according to the total abnormal change value to ensure the deposition effect of the subsequent multi - layer metal layer 2; Specifically, the statistical formula for the total abnormal change value of the chip substrate 1 is , where n is the total number of ranging units 41 laid inside the outer ring of the first detection module 4, i is the label serial number of the ranging unit 41, i takes an integer between 1 and n, h i represents the thickness of the oxide layer measured by the ranging unit 41 with the label serial number i, and the ideal value of h i is 0, so the ideal value of the abnormal change thickness is also 0.

[0025] Set h s as the oxide layer thickness limit value. Usually, h s is not greater than 3 angstroms, which is specifically set according to requirements; when h i > h s , it indicates that the thickness of the oxide layer at the i - th place of the chip substrate 1 is unqualified, and this place can be sent back to the plasma equipment for local cleaning at this place to ensure the qualification of the oxide layer thickness through supplementary cleaning; Set s as the total abnormal change limit value. When is between 0 - s, it indicates that the total abnormal change value is normal; Specifically, after obtaining the detection data, the first - step abnormal change analysis and the second - step abnormal change analysis will be carried out; Perform the first mutation analysis on the mutation detection results of the chip base layer 1: Case I: If h i ≤h s ,0≤ ≤ s, it indicates that the oxide layer thickness of each detection point on the chip base layer 1 is qualified, and the total mutation value is normal; Case II: If h i ≤h s , > s, it indicates that the oxide layer thickness of each detection point on the chip base layer 1 is qualified, but the total mutation value exceeds the normal range; Case III: If there is at least one h i >h s ,0≤ ≤ s, it indicates that there is at least one detection point on the chip base layer 1 with an unqualified oxide layer thickness, but the total mutation value is normal; Case IV: If there is at least one h i >h s , > s, it indicates that there is at least one detection point on the chip base layer 1 with an unqualified oxide layer thickness, and the total mutation value exceeds the normal range; Refer to Figure 4 ,L corresponds to the distance between the suction point of the vacuum manipulator in the cleaning chamber as the starting point of the moving path and the placement point of the magnetron sputtering equipment as the ending point of the moving path, p is the proportion of the path distance from the starting point to the position point of the first detection module in the moving path distance L, 0 < p ≤ 1; Perform the second mutation analysis on the mutation detection results of the chip base layer 1: After the back-end processor calculates the predicted value of the terminal oxide layer thickness and the predicted value of the total terminal mutation ,thereby calculating the terminal oxidation data of the chip base layer 1, that is, the predicted value of the terminal oxide layer thickness and the predicted value of the total terminal mutation, and then comparing them with the oxide layer thickness limit value and the total mutation limit value respectively; First, when p is equal to 1, the second asynchronous analysis is not performed, and only Case I and II meet the sputtering standard among the above four cases; therefore, execute the sputtering process in S2; Secondly, when p is not equal to 1 and > s, the second mutation analysis is not performed either, because the > appears in Case II and Case IVWhen it is s, it is inferred that the mobile environmental parameters need to be adjusted, and the calculation of the terminal oxidation data is meaningless. The generation amount of the oxide layer is reduced by adjusting the environmental parameters, including but not limited to adjustments such as vacuum upgrade, low temperature, and / or plasma reduction, to achieve effective oxidation prevention and control in the mobile environment where the vacuum manipulator is located, and ensure that the later RDSON and interconnect resistance reach the theoretical design values. The degree of adjustment is related to is positively correlated; therefore, directly replace the chip base layer 1, re-preprocess the new chip base layer 1 by cleaning, and apply it to the adjusted mobile environment; After that, when p is not equal to 1 and 0 ≤ ≤ s, the second-step asynchronous analysis needs to be performed. Specifically, calculate the terminal oxidation data for cases I and III, and then compare them with the oxide layer thickness limit value and the total abnormal change limit value respectively to further determine the belonging situation: When , 0 ≤ ≤ s, it still belongs to case I, and the sputtering process in S2 is executed; When there exists , 0 ≤ ≤ s, it still belongs to case III, and the vacuum manipulator will drive the chip base layer 1 back to the cleaning chamber to perform local plasma cleaning at the position point corresponding to the chip base layer 1 for i, and then execute the sputtering process in S2; Compared with the case of p = 1, through the setting of the first-step abnormal change analysis and the second-step abnormal change analysis, not only can the position points where the oxide layer thickness is unqualified be clearly located. It should be noted that the more n is, the more accurate the positioning is; in addition, the terminal oxidation data of the chip base layer 1 can be inferred during the movement path of the vacuum manipulator, and early inference and remedial measures can be made, which can not only save processing time but also ensure the adhesion of the multi-layer metal layer 2 in the subsequent process.

[0026] S2: Use physical vapor deposition process to perform sputter deposition of the multi-layer metal layer 2 and intelligently adjust the sputtering parameters.

[0027] A multi-target sputtering chamber is set in the magnetron sputtering equipment. Argon ions are continuously bombarded on the metal target to continuously deposit different materials. The adhesion layer 21 is used to block the diffusion of copper atoms, the connection layer 22 can be used as the seed layer for copper electroplating to provide a conductive substrate, and the bonding layer 23 is used to reduce the initial resistance of electroplating to ensure the uniform growth of the electroplated copper layer.

[0028] The above sputtering parameters include sputtering power P and working pressure F; both the sputtering power and the working pressure are positively correlated with the deposition rate; The ideal hierarchical thickness of the corresponding metal layer is denoted as A, where A = V * T + §, V is the deposition rate, T is the deposition time, and § is the compensation coefficient, which is at the same unit level as a and is usually taken as 0 to 0.1 times, determined according to the specific sputtering environment, and is used to obtain the ideal hierarchical thickness under the set deposition time. Among them, under the set parameters of V and T, the parameters in the actual sputtering process fluctuate. To ensure the ideal accuracy of the obtained data, the range of the ideal hierarchical thickness of the corresponding metal layer is determined by setting the compensation coefficient, which is convenient for subsequent comparison.

[0029] Before the sputtering process starts, the vacuum manipulator moves the chip substrate 1 to the substrate mounting position and completes the installation, and then sputters the multi-layer metal layer 2 in sequence under the setting of the initial sputtering parameters; during the sputtering process, the ellipsometric spectrometer is used to monitor the actual hierarchical thickness of the corresponding metal layer in real time, denoted as As; during the monitoring process, by comparing the actual hierarchical thickness As with the ideal hierarchical thickness A, the power and / or working pressure are adjusted in real time according to the comparison result; When sputtering the first metal layer, i.e., the adhesion layer 21, when the actual hierarchical thickness As at the first set time point does not reach the corresponding ideal hierarchical thickness A, first determine the thickness difference ∆A, and then the sputtering power is adjusted to increase, and the specific increase value is positively correlated with the thickness difference ∆A, so that the first metal layer can reach the ideal hierarchical thickness within the preset deposition time; When sputtering the second metal layer, i.e., the connection layer 22, if there is a problem that the actual hierarchical thickness As at the second set time point does not reach the corresponding ideal hierarchical thickness A, first further adjust the working pressure F, and then keep the sputtering power after the adjustment setting to carry out the deposition process of the second metal layer. After the working pressure F is adjusted, it is ensured that the deposited thickness that can make up for the missing thickness difference in the front is achieved. If the ideal hierarchical thickness is still not reached at another set third set time point, an alarm is processed, the subsequent hierarchical sputtering is not carried out, and the magnetron sputtering equipment is maintained and inspected to find the reason for the sputtering failure; Otherwise, after the multi-level metal layer 2 realizes the sputtering of the ideal hierarchical thickness in sequence in the unadjusted or adjusted process, the magnetron sputtering equipment will be taken out and the next process will be carried out.

[0030] S3: Apply photoresist on the top surface of the multi-layer metal layer, perform exposure and development, and determine the electroplating area and form a micron-level window.

[0031] S4: Deposit thick copper using the electroplating process, and then strip and anneal; The thickness of the electroplated copper layer is 20 - 25 microns, and the copper layer on the bonding layer 23 is deposited using the electroplating process; then the above-mentioned photoresist is removed, and the electroplating stress is eliminated by thermal annealing to enhance the bonding strength of copper grains.

[0032] S5: Prepare solder bumps for connecting the PCB board, then perform wafer dicing and corresponding electrical performance tests to verify whether the reduction of the RDSON value meets the standard.

[0033] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0034] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure, which is applied to a chip packaging structure based on a multi-layer metal structure. The structure includes a chip base layer, a multi-layer metal layer, and a plating layer arranged along a straight line direction. The multi-layer metal layer includes an adhesion layer, a connection layer, and a bonding layer. It is characterized in that: The following steps are involved: S1: Perform cleaning pretreatment using plasma cleaning, and perform mutation detection and analysis. After obtaining the detection data, perform the first mutation analysis and / or the second mutation analysis; S2: Using a physical vapor deposition process to perform sputtering deposition of multiple metal layers, and intelligently adjusting sputtering parameters, including sputtering power P and working pressure F, which are both positively correlated with the deposition rate; The fixed movement path of the chip substrate during the process of moving from the cleaning pretreatment step to the sputtering deposition step is determined and recorded as the movement path distance L. A point p is set on the movement path distance L. The position of point p is used for the first step of the abnormality analysis. At the position of point p, there are several detection points corresponding to the surface of the chip substrate. The value of p is the ratio of the distance between the starting point of the movement path and the end point of the movement path, and 0<p≤1; The first step of variation analysis is used to determine the qualified status of the oxide layer thickness at each detection point of the chip substrate and the normal status of the corresponding total variation value; the second step of variation analysis calculates the terminal oxidation data of the chip substrate based on the fact that p is not equal to 1 and the total variation value is normal, and then compares it with the oxide layer thickness limit and the total variation limit respectively to select the corresponding process, which includes sputtering, replacement, and local cleaning.

2. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 1, wherein: Also includes: S3: applying photoresist on the top surface of the multi-layer metal layer and performing exposure and development; S4: depositing thick copper using electroplating, followed by stripping and annealing; S5: Prepare solder bumps for connecting to PCB boards, then cut the wafers and perform corresponding electrical performance tests.

3. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 1, characterized in that: The cleaning pretreatment uses a cleaning chamber, the sputtering deposition of the multi-layer metal layer uses a magnetron sputtering device, and a vacuum manipulator is provided between the cleaning chamber and the magnetron sputtering device.

4. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 3, wherein: A first detection module is provided at position p in the fixed moving path of the vacuum manipulator. The first detection module is composed of a plurality of distance measuring units. The outer circle size of the first detection module is consistent with the chip substrate, and the plurality of distance measuring units are evenly laid inside the outer circle.

5. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 4, wherein: The first detection module is used to measure the thickness change of the chip base layer, which is recorded as the total abnormal change value , and the statistical formula for the total abnormal change value of the chip base layer is ; n is the total number of distance measurement units laid outside the inner circle of the first detection module, i is the marking serial number of the distance measurement unit, i takes an integer between 1 and n, h i represents the thickness of the oxide layer measured by the distance measurement unit with the marking serial number i.

6. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 5, characterized in that: Set h s as the oxide layer thickness limit. When h i > h s it indicates that the oxide layer thickness at the i-th location of the chip base layer is unqualified; Setting s is the limit value of the total abnormal change. When is between 0 - s, it indicates that the total abnormal change value is normal; the moving path distance L corresponds to the distance between the suction point of the vacuum manipulator in the cleaning chamber as the starting point of the moving path and the placement point of the magnetron sputtering equipment as the end point of the moving path, and p is the proportion of the path distance from the starting point to the position point of the first detection module in the moving path distance L.

7. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 6, wherein: The first step of mutation analysis is as follows: Case I: If h i ≤ h s , 0 ≤ ≤ s, it indicates that the oxide layer thickness at each detection point of the chip base layer is qualified and the total abnormal change value is normal; Case II: If h i ≤ h s , > s, it indicates that the oxide layer thickness at each detection point of the chip base layer is qualified, but the total mutation value is higher than the normal range; Case III: If there is at least one h i > h s , 0 ≤ ≤ s, it indicates that the oxide layer thickness of at least one detection point on the chip base layer is unqualified, but the total value of the anomalies is normal; Case IV: If there is at least one h i > h s , > s, it indicates that the oxide layer thickness at at least one detection point of the chip base layer is unqualified, and the total value of the anomalies exceeds the normal range.

8. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 7, characterized in that: The second step of mutation analysis is as follows: When p is not equal to 1 and 0 ≤ ≤ s, the second asynchronous analysis needs to be performed; For cases I and III, calculate the terminal oxidation data, and then compare them with the oxide layer thickness limit and the total variation limit to further determine the case: When and 0 ≤ ≤ s, it still belongs to Case I, and then perform the sputtering process in S2; When there is , 0 ≤ ≤ s, it still belongs to Case III. The vacuum manipulator will drive the chip base layer back to the cleaning chamber to perform plasma local cleaning at the position point of the chip base layer corresponding to i, and then perform the sputtering process in S2.

9. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 7, characterized in that: When p equals 1 or when p does not equal 1 and > s, the second asynchronous analysis is not performed.

10. The packaging method for reducing the RDSON resistance of a chip based on a multi-layer metal structure according to claim 1 or 9, characterized in that: The ideal layer thickness of the corresponding metal layer is recorded as A, A=V*T+§, where V is the deposition rate, T is the deposition time, and § is the compensation coefficient used to obtain the ideal layer thickness under the set deposition time; During the sputtering process, an ellipsometer is used to monitor the actual layer thickness of the corresponding metal layer in real time, recorded as As. During the monitoring process, the actual layer thickness As is compared with the ideal layer thickness A, and the power and / or working pressure are adjusted in real time according to the comparison results.

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