Chip

Abstract

A chip for a semiconductor device is disclosed. The chip includes a substrate formed of a semiconductor material, an epitaxial layer formed of a semiconductor material, an insulating layer, a passivation layer, a first recess, and a second recess extending into a first major surface of the insulating layer and at least to a first major surface of the epitaxial layer. And at least one part of the second groove is arranged on the inner side of the first groove. The second recess is inside the periphery of the chip and extends around the periphery of the chip. At least a portion of the passivation layer extends into the first recess. At least a portion of the passivation layer extends into the second recess.

Description

Technical Field

[0001] The present invention relates to a chip for a semiconductor device. The present invention also relates to a method of manufacturing a chip for a semiconductor device. Background Art

[0002] Chips for semiconductor devices such as MOSFET devices include a passivation layer. The purpose of the passivation layer is to protect the chip from the external environment, for example to reduce the likelihood of moisture and / or dust contacting the chip. Separation of the passivation layer from the chip is undesirable as this would be a potential entry point for dust and / or moisture.

[0003] There is a need to overcome the disadvantages associated with existing chips of semiconductor components, whether identified herein or otherwise. Summary of the Invention

[0004] In a first aspect of the present invention, there is provided a chip for a semiconductor device. The chip includes a substrate formed of a semiconductor material. The substrate defines a first major surface and a second major surface, the second major surface being opposite to the first major surface. The chip further includes an epitaxial layer formed of a semiconductor material. The epitaxial layer defines a first major surface and a second major surface, the second major surface being opposite to the first major surface. The second major surface of the epitaxial layer is fixed to the first major surface of the substrate. The chip further includes an insulating layer. The insulating layer defines a first major surface and a second major surface, the second major surface being opposite to the first major surface. The second major surface of the insulating layer is fixed to the first major surface of the epitaxial layer. The chip further includes a passivation layer. The passivation layer defines a first major surface and a second major surface, the second major surface being opposite to the first major surface. The second major surface of the passivation layer is fixed to the first major surface of the insulating layer. The chip further includes a first groove that extends into the first major surface of the insulating layer and at least into the first major surface of the epitaxial layer. The first groove is a continuous groove that is inside the periphery of the chip and extends around the periphery of the chip. The chip further includes a second groove that extends into the first major surface of the insulating layer and at least into the first major surface of the epitaxial layer. At least a portion of the second groove is disposed inside the first groove. The second groove is inside the periphery of the chip and extends around the periphery of the chip. At least a portion of the passivation layer extends into the first groove. At least a portion of the passivation layer extends into the second groove.

[0005] The so-called first groove and second groove extending around the periphery of the chip can be understood to mean that these grooves are disposed in the edge region of the chip.

[0006] One or more functional circuits may be disposed on the epitaxial layer. One or more functional circuits may be disposed inside the first groove and inside the second groove.

[0007] All of the grooves may have the same depth.

[0008] The first groove and the second groove may extend at least partially into the epitaxial layer.

[0009] The first groove may extend around the entire periphery of the chip.

[0010] The second groove may extend around the entire periphery of the chip.

[0011] The second groove may not be adjacent to the first groove.

[0012] During operation, the chip is subject to temperature fluctuations due to, for example, varying environmental conditions and / or heat generated by the semiconductor device itself. These temperature fluctuations cause the chip to expand and contract, which subjects the chip to internal stress. The internal stress increases the likelihood of delamination of the components of the chip. Since the chip includes the first and second grooves into which the passivation layer extends, the likelihood of separation of the passivation layer from the insulating layer is advantageously reduced. This is because the grooves increase the contact area between the passivation layer and the insulating layer. Increasing the contact area between the passivation layer and the insulating layer increases the bonding strength between the two layers, which reduces the likelihood of separation of the passivation layer from the insulating layer.

[0013] During fabrication, the chip is separated from a wafer that includes an array of chips. Typically, this is done using a sawing tool. Cracks may be generated during separation. Advantageously, since the first groove is continuous, the likelihood of any crack propagation that may be initiated during separation of the chip from the wafer is reduced. This improves manufacturing efficiency since fewer defective chips are produced.

[0014] The second groove may be discontinuous.

[0015] The second groove being discontinuous may be understood to mean that the second groove is formed by a plurality of groove segments spaced apart from each other.

[0016] In the case where the second groove is discontinuous, the likelihood of propagation of separation of the passivation layer from the insulating layer is advantageously reduced. This is because, in the case where the passivation layer separates from the insulating layer in the region of one of the segments of the second groove, the likelihood that such separation continues to an adjacent segment of the second groove is reduced. This is compared to the case where each segment of the second groove extends continuously from an adjacent segment. In terms of the integrity of the chip, separation of a limited portion of the passivation layer from the insulating layer is acceptable. Thus, in the case where the second groove is discontinuous, the robustness of the chip is advantageously improved.

[0017] Furthermore, in the case where the second groove is discontinuous, the surface area of the second groove may be greater than in the case where the second groove is continuous. This further increases the bonding strength between the passivation layer and the insulating layer, which further reduces the likelihood of separation of the passivation layer from the insulating layer.

[0018] The second groove may be formed by a plurality of groove segments. In a plan view, each groove segment may be circular, polygonal, annular, cross-shaped, dot-shaped, or linear.

[0019] The above geometric shape of each groove segment of the second groove is particularly effective for achieving the advantages of the present invention.

[0020] The plan view can be understood to refer to a view of the insulating layer perpendicular to the main surface of the insulating layer.

[0021] In this document, a shape can be understood to have at least two dimensions of equal size.

[0022] The first groove may follow a waveform path.

[0023] In the case where the first groove defines a waveform path, compared with a linear path, the contact area between the passivation layer and the first groove increases. Therefore, in the case where the first groove defines a waveform path, the possibility of separation between the passivation layer and the insulating layer is advantageously further reduced.

[0024] The first groove may follow a sinusoidal path, a square wave path, a triangular wave path, or a sawtooth wave path.

[0025] The above geometric shape of the first groove is particularly effective for achieving the advantages of the present invention.

[0026] Each groove segment of the plurality of groove segments of the second groove may be provided between the inner end and the outer end of the path defined by the first groove.

[0027] In the case where each groove segment of the second groove is linear in a plan view, each groove segment of the second groove may extend parallel or non-parallel to an adjacent portion of the first groove.

[0028] Each groove segment of the second groove may extend perpendicular to an adjacent portion of the first groove.

[0029] The above arrangement is particularly effective for achieving the advantages of the present invention.

[0030] The chip may further include a third groove that extends into the first main surface of the insulating layer. The third groove may be inside the periphery of the chip and extend around the periphery of the chip. At least a portion of the passivation layer may extend into the third groove. The third groove is a continuous groove.

[0031] The third groove may be provided outside one or more functional circuits of the epitaxial layer.

[0032] In the case where the third groove is provided, the contact area between the passivation layer and the insulating layer is further increased. This further reduces the possibility of separation between the passivation layer and the insulating layer.

[0033] The third groove may be provided inside the first groove. The third groove may be provided inside the second groove. Each groove segment of the second groove does not extend parallel to the adjacent part of the first groove. Each groove segment of the second groove may be adjacent to the first groove and the third groove and extend between the first groove and the third groove.

[0034] The third groove may be provided outside the first groove.

[0035] The second groove may be continuous.

[0036] In the case where the second groove is continuous, the contact area between the passivation layer and the first and second grooves is increased compared to the case where the second groove is discontinuous. This increases the bonding strength between the passivation layer and the insulating layer, which reduces the possibility of separation between the passivation layer and the insulating layer.

[0037] The first groove may follow a waveform path defining a plurality of vertices. The second groove may follow a waveform path defining a plurality of vertices. Alternative vertices of the first groove may be adjacent to alternative vertices of the second groove.

[0038] The plurality of vertices of the first groove may be understood as the peaks or valleys defined by the waveform path followed by the first groove. The plurality of vertices of the second groove may be understood as the peaks or valleys defined by the waveform path followed by the second groove. In other words, the plurality of vertices may refer to the inner and outer ends of the paths followed by the first groove and the second groove.

[0039] The second groove may be provided inside the first groove.

[0040] The entire second groove may be provided inside the first groove.

[0041] As described above, when the first groove is continuous, the possibility of crack propagation is reduced. The second groove being provided inside the first groove further reduces this, especially in the case where the second groove is discontinuous. This is because the discontinuity of the second groove may allow crack propagation. Therefore, the first groove being located outside the second groove further reduces the possibility of crack propagation.

[0042] The passivation layer may be formed of polyimide.

[0043] Polyimide is an ideal material for the passivation layer because, compared with other materials that can be used for the passivation layer such as silicon nitride, polyimide is less prone to cracking during use. Cracking of the passivation layer is undesirable because it can lead to failures of the chip and the semiconductor device of which the chip forms a part, for example due to the ingress of moisture. Therefore, forming the passivation layer from polyimide increases the robustness of the chip.

[0044] In addition, the difference between the coefficient of thermal expansion of polyimide and that of the cover layer applied to the clip during the assembly of the semiconductor device is smaller than that of conventional passivation layer materials. In the case of reducing this difference, the internal stress suffered by the device during use is reduced, which reduces the possibility of delamination between the cover layer and the passivation layer.

[0045] In a second aspect of the present invention, there is provided a method of fabricating a chip for a semiconductor device. The method includes providing a substrate that defines a first major surface and a second major surface, the second major surface being generally opposite to the first major surface. The substrate is formed of a semiconductor material. The method further includes providing an epitaxial layer that defines a first major surface and a second major surface, the second major surface being generally opposite to the first major surface. The epitaxial layer is formed of a semiconductor material. The epitaxial layer includes a plurality of active cells. The epitaxial layer is provided such that the second major surface of the epitaxial layer is fixed to the first major surface of the substrate. The method further includes providing an insulating layer that defines a first major surface and a second major surface, the second major surface being generally opposite to the first major surface. The method further includes fixing the second major surface of the insulating layer to the first major surface of the epitaxial layer. The method further includes applying a first photoresist layer to the first major surface of the insulating layer and then patterning the first photoresist layer. The method further includes forming a plurality of recesses that extend through the insulating layer and at least reach the epitaxial layer. The positions of the plurality of recesses correspond to respective ones of the plurality of active cells. The method further includes forming a first groove that extends into the first major surface of the insulating layer and at least extends into the epitaxial layer. The first groove is a continuous groove that is inside the periphery of the chip and extends around the periphery of the chip. The method further includes forming a second groove that extends into the first major surface of the insulating layer and at least extends into the epitaxial layer. At least a portion of the second groove is disposed inside the first groove. The second groove is inside the periphery of the chip and extends around the periphery of the chip. The pattern applied to the first photoresist layer corresponds to the plurality of recesses, the first groove, and the second groove. The method further includes removing the first photoresist layer. The method further includes providing a conductive layer that defines a first side and a second side. The first side of the conductive layer is fixed to the first major surface of the insulating layer and extends into the plurality of recesses, the first groove, and the second groove. The method further includes applying a second photoresist layer to the first side of the conductive layer and then patterning the second photoresist layer. The method further includes removing the conductive layer from one or more regions corresponding to the first groove and the second groove, and from inside the first groove and the second groove. The pattern applied to the second photoresist layer corresponds to one or more regions corresponding to the first groove and the second groove. The method further includes removing the second photoresist layer. The method further includes providing a passivation layer. The passivation layer is fixed to the second side of the conductive layer and extends into the first groove and the second groove.

[0046] The conductive layer may be formed of a plurality of constituent layers or portions. Each layer or portion may be formed of a different conductive material.

[0047] Patterning of the photoresist layer involves removing one or more portions of the photoresist layer.

[0048] The plurality of recesses may extend into the epitaxial layer.

[0049] The pattern applied to the first photoresist layer corresponding to one or more regions of the plurality of recesses, the first groove, and the second groove can be understood to mean that when observed in a plan view, the one or more portions removed correspond in shape to the plurality of recesses, the first groove, and the second groove.

[0050] The pattern applied to the second photoresist layer corresponding to one or more regions of the first groove and the second groove can be understood to mean that when observed in a plan view, the one or more portions removed correspond in shape to the first groove and the second groove.

[0051] The plurality of recesses, the first groove, and the second groove can be formed via a dry etching process such as plasma etching.

[0052] The conductive layer can be removed via a dry etching process such as plasma etching. The conductive layer can be removed via a wet etching process such as acid etching.

[0053] The conductive layer can be removed from one or more regions corresponding to the first groove and the second groove and from within the first groove and the second groove via etching, preferably via wet etching or isotropic dry etching.

[0054] After removing the conductive layer and before providing the passivation layer, an adhesive layer that can be formed of silicon nitride can be applied to the first groove and the second groove.

[0055] The plurality of recesses can be formed via etching. The first groove can be formed via etching. The second groove can be formed via etching.

[0056] It should be understood that features discussed with respect to one aspect of the present invention can be combined with different aspects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Embodiments of the present invention will now be described with reference to the accompanying drawings, wherein:

[0058] Figure 1 A perspective view of a semiconductor device according to an embodiment of the present invention is shown;

[0059] Figure 2 Shows Figure 1 A cross-sectional view of a portion of a chip of the semiconductor device;

[0060] Figure 3 Shows [[ID=4...]] Figure 2 A plan view of the chip;

[0061] Figures 4 to 8 Shows a portion of a groove that can be implemented in the chip of Figure 2 and 3 the chip;

[0062] Figure 9a and 9b shows a chip 6 having another alternative groove geometry; and

[0063] Figures 10 to 17 shows a method of manufacturing Figure 2 and 3 the chip. DETAILED DESCRIPTION

[0064] Figure 1 shows a semiconductor device 2. The semiconductor device 2 is a MOSFET. The semiconductor device 2 includes a lead frame 4. The semiconductor device 2 includes a chip 6. The semiconductor device 2 includes clips 8. The semiconductor device 2 includes a cover layer ( Figure 1 not shown in).

[0065] The lead frame 4 serves as a base for the semiconductor device 2, to which the other components of the device are attached. The lead frame 4 is made of a conductive material such as copper (including copper alloys).

[0066] The chip 6 is fixed to the lead frame 4. The chip 6 is fixed to the lead frame 4 by a first solder layer 10. The chip 6 can be a single component or can include multiple constituent components. The chip 6 is made of a semiconductor material. For example, the chip 6 can be made of silicon, silicon carbide, or gallium nitride or any other suitable material. The chip 6 has functional circuits fabricated thereon. The chip 6 is typically rectangular, but can also be any other suitable shape. The chip 6 is in the form of a plate.

[0067] In Figure 1 the embodiment shown, the clip 8 includes two constituent parts 8a, 8b such that the device 2 is a three-terminal device. However, in some embodiments, the clip 8 can include any suitable number of constituent parts. For example, the clip 8 can include only a single constituent part such that the device 2 is a two-terminal device. In some embodiments, the clip 8 need not be provided and a wire can be used in its place such that the device 2 is a wire-bonded device.

[0068] The cover layer encapsulates the remaining components of the semiconductor device 2 (i.e., the lead frame 4, the chip 6, and the clip 8). The cover layer can also be referred to as an isolator, a housing, or an encapsulant. Multiple leads 7 of the clip 8 (only one of which is labeled in Figure 1 ) extend through the cover layer. This allows the leads 7 to be connected to an external circuit (not shown). The cover layer can be made of any suitable electrically insulating material such as epoxy resin.

[0069] Now referring to Figure 2 , a cross-sectional view of the peripheral portion of the chip 6 is shown. The chip 6 defines a periphery 21.

[0070] Chip 6 includes a substrate 11. The substrate 11 defines a first major surface 13. The substrate 11 includes a second major surface 15. The second major surface 15 is generally opposite to the first major surface 13. The substrate 11 is formed of a semiconductor material such as silicon, for example.

[0071] Chip 6 further includes an epitaxial layer 12. The epitaxial layer 12 defines a first major surface 14. The epitaxial layer 12 includes a second major surface 16. The second major surface 16 is generally opposite to the first major surface 14. The second major surface 16 of the substrate 12 is fixed to the first major surface 13 of the epitaxial layer 11. The epitaxial layer 12 is formed of a semiconductor material such as silicon, for example. Active units 18 are formed in the epitaxial layer 12. Although only one active unit 18 is visible in Figure 2 the view, the epitaxial layer 12 may include multiple active units. It should be understood that Figure 2 the view only shows a part of chip 6, and thus additional active units that are not visible in the Figure 2 view are also provided. The active unit 18 includes a first gate 20 and a second gate 22. The second gate 22 is disposed outside the first gate 20. That is, the second gate 22 is disposed closer to the periphery 21 of the chip 6 than the first gate 20.

[0072] Chip 6 further includes an insulating layer 24. The insulating layer 24 may also be referred to as an interlayer dielectric. The insulating layer 24 includes a first portion 24a and a second portion 24b. The first portion 24a may be formed of phosphorous-doped silicon glass. The second portion 24b may be formed of undoped silicon glass. The insulating layer 24 defines a first major surface 26. The insulating layer defines a second major surface 28. The first major surface 26 of the insulating layer 24 is generally opposite to the second major surface 28 of the insulating layer 24.

[0073] A first recess 30a extends through the insulating layer 24 and at least partially into the epitaxial layer 12. The first recess 30a is disposed between the first gate 20 and the second gate 22 of the active unit 18. A second recess 30b extends through the insulating layer 24 and at least partially into the epitaxial layer 12. The second recess 30b is disposed adjacent to and outside the first gate 20 of the active unit. The second recess 30b is the outermost (i.e., the one closest to the periphery 21 of the chip 6) recess. The region of the chip 6 outside the second recess 30b may be referred to as the non-active region 25 of the chip 6. The region of the chip 6 that includes the second recess 30b and is inside it may be referred to as the active region 27 of the chip 6.

[0074] The chip 6 further includes a conductive layer 32. The conductive layer defines a first side 31 and a second side 33. The second side 33 is generally opposite to the first side 31. The conductive layer 32 includes a first portion 32a, a second portion 32b, and a third portion 32c. The third portion 32c defines the first side 31 of the conductive layer 32. The second portion 32b defines the second side 33 of the conductive layer 32. The first portion 32a of the conductive layer 32a is disposed within the first recess 30a and the second recess 30b of the active unit 18. The first portion 32a of the conductive layer 32 is formed of tungsten. However, any other suitable material may be used. The first portion 32a of the conductive layer 32 includes two components. Each portion of the first portion 32a of the conductive layer 32 may be referred to as a plug.

[0075] The second portion 32b of the conductive layer 32b is fixed to the first major surface 26 of the insulating layer 24. The second portion 32b of the conductive layer 32 also extends into the first recess 30a and the second recess 30b of the active unit 18. The second portion 32b of the conductive layer 32 interfaces with the surfaces of the recesses 30a, 30b. The second portion 32b of the conductive layer 32 is fixed to the surfaces of the recesses 20a, 20b. The second portion 32b of the conductive layer 32 is in contact with the first portion 32a of the conductive layer 32. The second portion 32b of the conductive layer 32 is made of titanium or titanium nitride. However, any suitable material may be used.

[0076] The third portion 32c of the conductive layer 32 is fixed to the second portion 32b of the conductive layer 32 and the first portion 32a of the conductive layer 32. The third portion 32c of the conductive layer is at least partially disposed within the recesses 30a, 30b, but this is not necessary. The third portion 32c of the conductive layer 32 is preferably formed of an aluminum-copper composite.

[0077] The chip 6 further includes a first groove 34. The first groove 34 is disposed within the non-active region 25 of the chip 6. The first groove 34 extends into the insulating layer 24. In particular, the first groove 34 extends into the first major surface 26 of the insulating layer 24. The first groove 34 extends all the way through the insulating layer 24. The first groove 34 partially extends into the epitaxial layer 12. The first groove 34 extends into the first major surface 14 of the epitaxial layer 12. However, in some embodiments, the first groove 34 only needs to extend at least into the epitaxial layer 12. That is, the bottom surface of the first groove 34 may be defined by the first major surface 14 of the epitaxial layer 12. As will be discussed in more detail below, the first groove 34 is a continuous groove and extends around the periphery of the chip 6 and inside the periphery of the chip. Because the first groove 34 is a continuous groove, the likelihood of any crack propagation that may be initiated at the periphery 21 of the chip is advantageously reduced.

[0078] As used herein, the term 'continuous' with respect to a groove may be understood to mean that there is no discontinuity in the channel defined by the groove.

[0079] The chip 6 further includes a second groove 36. The second groove 36 is provided in the non-active region 25 of the chip 6. The second groove 36 extends into the first major surface 26 of the insulating layer 24. The second groove 36 is provided inside the first groove 34. The second groove 36 extends all the way through the insulating layer 24. The second groove 36 partially extends into the epitaxial layer 12. The second groove 36 extends into the first major surface 14 of the epitaxial layer. However, in some embodiments, the second groove 36 only needs to extend into the epitaxial layer 12. That is to say, the bottom surface of the second groove 36 may be defined by the first major surface 14 of the epitaxial layer 12. The second groove 36 surrounds the periphery of the chip 6 and extends inside the periphery of the chip. In this embodiment, the second groove 36 is a discontinuous groove. However, in other embodiments, the second groove may be a continuous groove.

[0080] As used herein, the term 'discontinuous' with respect to a groove can be understood to mean that the groove is formed of a plurality of separately formed portions.

[0081] The chip 6 further includes a passivation layer 38. Preferably, the passivation layer 38 is formed of polyimide. However, any suitable material can be used for the passivation layer, such as polybenzoxazole (PBO). The passivation layer 38 defines a first side 40, which may also be referred to as the first major surface of the passivation layer. The passivation layer defines a second side 42, which may also be referred to as the second major surface of the passivation layer. The second side 42 is generally opposite to the first side 40. The second side 42 of the passivation layer 38 is fixed to the first major surface 26 of the insulating layer 24. The second side 42 of the passivation layer 38 is also fixed to the third portion 32c of the conductive layer 32. At least a portion of the passivation layer 38 extends into the first groove 34 and into the second groove 26. Preferably, the first groove 34 and the second groove 36 are filled with the passivation layer 38.

[0082] The purpose of the first groove 34 and the second groove 36 is to improve the adhesion between the passivation layer 38 and the insulating layer 24. The provision of the two grooves advantageously increases the contact area between the passivation layer and the insulating layer 24. This advantageously reduces the possibility of the passivation layer 38 separating from the insulating layer 24.

[0083] In some embodiments, an adhesive layer (not shown) may be provided between the passivation layer 38 and the insulating layer 24. The adhesive layer may be formed of silicon dioxide or silicon nitride. When provided, the adhesive layer improves the adhesion between the passivation layer 38 and the insulating layer 24.

[0084] Figure 3 A plan view of the chip 6 is shown. In Figure 3For clarity, the passivation layer 38, the conductive layer 32, and the active unit 18 are not depicted. In this embodiment, the entire second groove 36 is disposed inside the first groove 34. It can also be seen that, as discussed above, the first groove 34 is a continuous groove. The first groove 34 is linear. The first groove 34 is disposed inside the periphery 21 of the chip 6. The second groove 36 is discontinuous. Thus, the second groove 36 is formed by a plurality of separately formed groove segments 36a, 36b, 36c (only three of which are labeled in Figure 3 ). Each of the groove segments 36a-c of the second groove 36 is linear. Each of the plurality of groove segments 36a-c extends parallel to an adjacent portion of the first groove 34. However, in some embodiments discussed below, at least a portion of the second groove 36 need not extend parallel to an adjacent portion of the first groove 34. Each of the groove segments 36a-c of the second groove 36 is in the form of a dash. The geometries of the first groove 34 and the second groove 36, including the paths followed by the first groove 34 and the second groove 36, can vary to optimize this adhesion. Additionally, although only two grooves 34, 36 are depicted in Figure 2 and 3 , additional grooves can be provided.

[0085] Figure 4 Figures 10 to 9 show alternative groove geometries. Each geometry can be implemented in the chip 6 shown in Figures 1 to 3 . Only a portion of each geometry is shown. For each geometry, when applied to the chip, the grooves extend around the periphery of the chip 6 (i.e., around the entire periphery of the chip 6). Each geometry is shown in a plan view. In this context, the term plan view can be understood to refer to a view of the grooves perpendicular to the first major surface of the insulating layer.

[0086] Figure 4Shows a first alternative geometry. In this embodiment, both the first groove 34 and the second groove 36 are continuous grooves. The first groove 34 follows a waveform path. As depicted, the waveform of the path followed by the first groove 34 is a triangular waveform path. However, in other embodiments, the path followed by the first groove 34 can be a sinusoidal path, a square waveform path, a sawtooth waveform path, or any other waveform. The second groove 36 follows a waveform path. As depicted, the waveform of the path followed by the second groove 36 is a triangular waveform path. However, in other embodiments, the path followed by the second groove 36 can be a sinusoidal path, a square waveform path, or a sawtooth waveform path. The waveform of the path followed by the first groove 34 does not have to be the same as the waveform of the path followed by the second groove 36. For example, the first groove 34 can follow a sinusoidal path, and the second groove 36 can follow a square waveform path. When applied to the chip 6, the amplitude direction of the wave path defined by the grooves 34, 36 generally extends parallel to the first major surface of the insulating layer ( Figure 4 not shown in).

[0087] The first groove defines a plurality of vertices 44 (only one of which is labeled in Figure 4 ). The second groove 36 defines a plurality of vertices 46 (only one of which is labeled in Figure 4 ). The term vertex can be understood to refer to the peaks or valleys defined by the waveform paths followed by the grooves 34, 36. In other words, the plurality of vertices 44, 46 can refer to the inner and outer ends of the paths followed by the first groove 34 and the second groove 36. The first groove 34 and the second groove 36 are adjacent to each other. In particular, the alternative vertices of the plurality of vertices 44 of the first groove are adjacent to the alternative vertices of the plurality of vertices 46 of the second groove.

[0088] Figure 5 Shows another alternative groove geometry. The first groove 34 is a continuous linear groove. In some embodiments, the first groove 34 can follow a waveform path. The wave can take any form discussed above in connection with Figure 4 . In this embodiment, the second groove 36 is a discontinuous groove. In this embodiment, each of the plurality of groove segments 36a-c of the second groove 36 is cross-shaped in a plan view. The second groove 36 is not adjacent to the first groove 34, but can also be adjacent to the first groove in some embodiments.

[0089] Figure 6 Shows another alternative groove geometry. In this embodiment, the first groove is a continuous linear groove. In some embodiments, the first groove 34 can follow a waveform path. The wave can take any form discussed above in connection with Figure 4Any form of discussion. In this embodiment, the second groove 36 is a discontinuous groove and thus includes a plurality of groove segments 36a-c. Each of the plurality of groove segments 36a-c is polygonal in a plan view. In the depicted embodiment, the polygonal shape defined by each of the groove segments 36a-c is octagonal. However, any other suitable polygonal shape may be used. For example, each of the plurality of groove segments 36a-c may be triangular, square, or pentagonal in a plan view. Preferably, each segment is octagonal because this increases the surface area of each segment. In some non-depicted embodiments, each of the plurality of groove segments 36a-c may be circular in a plan view.

[0090] Figure 7 Another alternative groove geometry is shown. In this embodiment, the first groove 34 defines a continuous linear path. In some embodiments, the first groove 34 may follow a waveform path. The wave may take any form discussed above in connection with Figure 4 Any form of discussion. In this embodiment, the second groove 36 is a discontinuous groove. The second groove 36 of this embodiment is similar to Figure 6 The second groove of. In this embodiment, the central post 48 is included in each of the groove segments 36a-c of the second groove. The central post 48 of each of the plurality of groove segments 36a-c advantageously increases the surface area of each of the groove segments. This further improves the adhesion between the passivation layer ( Figure 7 Not shown) and the insulating layer ( Figure 7 Not shown). In a plan view, the periphery of each of the plurality of groove segments 36a-c of the second groove is polygonal. Each of the plurality of groove segments 36a-c of the second groove may be referred to as being annular.

[0091] Figure 8 Another alternative groove geometry is shown. In this embodiment, a third groove 50 is provided. The third groove 50 is disposed inside the first groove 34 and inside the second groove 36. The third groove 50 is a continuous groove. The third groove 50 is a linear groove. In this embodiment, the first groove 34 is a continuous linear groove. In some embodiments, the first groove 34 and / or the third groove 50 may follow a waveform path. The wave may take any form discussed above in connection with Figure 4Any form of discussion. In this embodiment, the second groove 36 is a discontinuous groove. Each groove segment 36a-c of the second groove 36 is linear. Each groove segment of the plurality of groove segments 36a-c of the second groove 36 extends perpendicular to an adjacent portion of the first groove 34. However, in other embodiments, each groove segment of the plurality of groove segments 36a-c of the second groove 36 may extend at any non-parallel angle with respect to an adjacent portion of the first groove 34, preferably at an interior angle of at least 25 degrees. Each groove segment of the plurality of groove segments 36a-c of the second groove 36 is perpendicular to an adjacent portion of the third groove 50. However, in other embodiments, each groove segment 36-c of the second groove 36 may extend at any non-parallel angle with respect to an adjacent portion of the third groove 50, preferably at an interior angle of at least 45 degrees. Each groove segment of the plurality of groove segments 36a-c of the second groove 36 abuts the first groove 34 and the third groove 50 and extends therebetween. In some embodiments, the third groove 50 need not be provided. In some embodiments, the second groove 34 may adopt any geometry referenced Figures 4 to 7 disclosed.

[0092] Figure 9a and 9b shows an alternative embodiment of the chip 6 having another alternative groove geometry. As with Figure 3 For clarity, the passivation layer 38, the conductive layer 32, and the active units 18 are not depicted. Figure 9a shows a plan view of the chip 6. Figure 9b shows Figure 9a a detailed view of a portion of Figure 4 discussed above. In this embodiment, the third groove 50 is also provided. The third groove 50 is disposed outside the first groove 34 and outside the second groove 36. The third groove 50 is a linear groove. The first groove 34 is a waveform groove. The waveform path followed by the first groove 34 is a square wave. However, the waveform followed by the first groove 34 may be any of the waveforms discussed above with respect to Figure 4 The vertices of the first groove 34 are rounded. This advantageously improves the flow of the passivation layer into the first groove 34, which improves the adhesion between the passivation layer and the first groove 34. The second groove 36 is a discontinuous groove. Each groove segment 36a-c of the second groove 36 is square in plan view. However, the groove segments 36a-c of the second groove may adopt any other suitable shape. Each groove segment of the plurality of groove segments 36a-c of the second groove 36 is disposed between the inner and outer ends of the first groove 34. The groove segments of the plurality of groove segments 36a-c of the second groove 36 may be referred to as intersecting the first groove. In some embodiments, the third groove 50 need not be provided.

[0093] Now reference will be made toFigures 10 to 16 Discuss the process of manufacturing chip 6. In Figure 10 the first step shown in, a substrate 11 and an epitaxial layer 12 are provided. The epitaxial layer 12 is fixed to the substrate 11. It can be seen that the epitaxial layer 12 has been provided with a first gate 20 and a second gate 22 of the active unit 18 in a conventional manner.

[0094] Next, as Figure 11 shown, an insulating layer is provided at 24 such that the second major surface 28 of the insulating layer 24 is fixed to the first major surface 14 of the epitaxial layer 12.

[0095] Next, as Figure 12 shown, a first photoresist layer 52 is applied to the first major surface 26 of the insulating layer 24. The first photoresist layer 52 is patterned and thus includes a plurality of holes 54 (only one of which is marked in Figure 12 ). The pattern of the first photoresist layer 52, that is, the positions of the openings 54, corresponds to the positions of a plurality of recesses and grooves (not present at this stage).

[0096] Next, as Figure 13 shown, a first recess 30a, a second recess 30b, a first groove 34, a second groove 36, and a third groove 50 are formed such that each of the recesses 30a, 30b and each of the grooves 34, 36, 50 extend into the first major surface 26 of the insulating layer 24. In the depicted embodiment, the recesses 30a, 30b and the grooves 34, 36, 50 also extend into the epitaxial layer 12. However, as discussed above, this may not be the case for the grooves 34, 36, 50, and they may only extend into the epitaxial layer 12. The first recess 30a, the second recess 30b, the first groove 34, the second groove 36, and the third groove 50 are formed via plasma etching. Since the first photoresist layer 52 is applied to the first major surface 26 of the insulating layer 24, the plasma etching process is only effective in the regions corresponding to the plurality of holes 54. Then, the first photoresist layer 52 is removed.

[0097] Next, as Figure 14 shown, a conductive layer 32 is provided. The conductive layer 32, particularly the second portion 32b of the conductive layer 32, is fixed to the first major surface 26 of the insulating layer 24. The second portion 32b of the conductive layer 32 extends into the first recess 30a, the second recess 30b, the first groove 34, the second groove 36, and the third groove 50. The first portion 32a of the conductive layer is disposed in the first recess 30a, the second recess 30b, the first groove 34, the second groove 36, and the third groove 50. A third portion 32c is fixed to the first portion 32a and the second portion 32b.

[0098] Next, as Figure 15As shown, a second photoresist layer 56 is applied to the first side 31 of the conductive layer 32. The second photoresist layer 56 is applied to the active region 27 of the chip 6.

[0099] Next, as Figure 16 shown, a first portion 32a of the conductive layer 32 is removed from the first groove 34, the second groove 36, and the third groove 50. This can be accomplished via a wet etching process such as acid etching. Alternative etching methods, such as plasma etching, can be used. Due to the selectivity of the etching, a photoresist layer is not required at this stage, which first removes the material of the first portion 32a of the conductive layer 32. Additionally, a second portion 32b of the conductive layer 32 is removed from the regions corresponding to the first groove 34, the second groove 36, and the third groove 50. The second portion 32b can be removed via an isotropic dry etching such as plasma etching. The removal of the second portion 32b occurs after the removal of the first portion 32a.

[0100] Next, as Figure 17 shown, a passivation layer 38 is provided. The passivation layer 38 is secured to the first side 31 of the conductive layer 32. The passivation layer 38 extends into the first groove 34, the second groove 36, and the third groove 50. The passivation layer also adheres to the first major surface 26 of the insulating layer 24.

[0101] Although the above discussion of the method of manufacturing the chip 6 is directed to providing three grooves, it should be understood that the above method is equally applicable to the case of providing only two grooves.

[0102] While specific embodiments of the invention have been described above, it should be understood that the invention may be practiced in a manner different from that described. The above description is intended to be illustrative, not restrictive. Thus, it will be apparent to those skilled in the art that the described invention may be modified without departing from the scope of the claims set forth below.

Claims

1. A chip for a semiconductor device, the chip comprising: A substrate formed of a semiconductor material, the substrate defining a first major surface and a second major surface, the second major surface being opposite to the first major surface; An epitaxial layer formed of a semiconductor material, the epitaxial layer defining a first major surface and a second major surface, the second major surface being opposite to the first major surface, wherein the second major surface of the epitaxial layer is fixed to the first major surface of the substrate; An insulating layer, the insulating layer defining a first major surface and a second major surface, the second major surface being opposite to the first major surface, wherein the second major surface of the insulating layer is fixed to the first major surface of the epitaxial layer; A passivation layer, the passivation layer defining a first major surface and a second major surface, the second major surface being opposite to the first major surface, the second major surface of the passivation layer being fixed to the first major surface of the insulating layer; A first groove extending into the first major surface of the insulating layer and at least into the first major surface of the epitaxial layer, the first groove being a continuous groove that extends inside the periphery of the chip and around the periphery of the chip; A second groove extending into the first major surface of the insulating layer and at least into the first major surface of the epitaxial layer, at least a portion of the second groove being disposed inside the first groove, wherein the second groove extends inside the periphery of the chip and around the periphery of the chip; Wherein at least a portion of the passivation layer extends into the first groove, and wherein at least a portion of the passivation layer extends into the second groove.

2. The chip according to claim 1, wherein the second groove is discontinuous.

3. The chip according to claim 1 or claim 2, wherein the second groove is formed of a plurality of groove segments, and wherein in a plan view, each groove segment is circular, polygonal, annular, cross-shaped, dot-shaped or linear.

4. The chip according to any one of the preceding claims, wherein the first groove follows a waveform path.

5. The chip according to any one of the preceding claims, wherein the first groove follows a sinusoidal path, a square wave path, a triangular wave path or a sawtooth wave path.

6. The chip according to claim 3, and claim 4 or claim 5, wherein each groove segment of the plurality of groove segments of the second groove is disposed between an inner end and an outer end of the path defined by the first groove.

7. The chip according to claim 3, wherein each groove segment of the second groove is linear in a plan view, and wherein each groove segment of the second groove extends parallel or non-parallel to an adjacent portion of the first groove.

8. The chip according to any one of the preceding claims, the chip further comprising a third groove extending into the first major surface of the insulating layer, wherein: The third groove extends inside the periphery of the chip and around the periphery of the chip At least a portion of the passivation layer extends into the third groove; and The third groove is a continuous groove.

9. The chip according to claims 7 and 8, wherein the third groove is disposed inside the first groove and inside the second groove, and wherein each groove segment of the second groove does not extend parallel to an adjacent portion of the first groove, and wherein each groove segment of the second groove abuts the first groove and the third groove and extends therebetween.

10. The chip according to any one of claims 1 to 7 and 8, wherein the third groove is disposed outside the first groove.

11. The chip according to claim 1, wherein the second groove is continuous.

12. The chip according to claim 11, wherein the first groove follows a waveform path defining a plurality of vertices, and the second groove follows a waveform path defining a plurality of vertices, and wherein alternative vertices of the first groove abut alternative vertices of the second groove.

13. The chip according to any one of the preceding claims, wherein the second groove is disposed inside the first groove. The chip according to any one of the preceding claims, wherein the passivation layer is formed of polyimide.

15. A method of manufacturing a chip for a semiconductor device, the method comprising: providing a substrate defining a first major surface and a second major surface, the second major surface being generally opposite the first major surface, wherein the substrate is formed of a semiconductor material; providing an epitaxial layer defining a first major surface and a second major surface, the second major surface being generally opposite the first major surface, wherein the epitaxial layer is formed of a semiconductor material and includes a plurality of active units, wherein the epitaxial layer is provided such that the second major surface of the epitaxial layer is fixed to the first major surface of the substrate; providing an insulating layer defining a first major surface and a second major surface, the second major surface being generally opposite the first major surface; fixing the second major surface of the insulating layer to the first major surface of the epitaxial layer; applying a first photoresist layer to the first major surface of the insulating layer and then patterning the first photoresist layer; forming a plurality of recesses extending through the insulating layer and into the substrate, the positions of the plurality of recesses corresponding to respective ones of the plurality of active units; forming a first groove extending into the first major surface of the insulating layer and at least into the epitaxial layer, the first groove being a continuous groove inside and surrounding the periphery of the chip; and forming a second groove extending into the first major surface of the insulating layer and at least into the epitaxial layer, at least a portion of the second groove being disposed inside the first groove, wherein the second groove is inside and surrounds the periphery of the chip; wherein the pattern applied to the first photoresist layer corresponds to the plurality of recesses, the first groove, and the second groove; wherein the method further comprises: removing the first photoresist layer; providing a conductive layer defining a first side and a second side, the first side of the conductive layer being fixed to the first major surface of the insulating layer and extending into the plurality of recesses, the first groove, and the second groove; applying a second photoresist layer to the first side of the conductive layer and then patterning the second photoresist layer; and removing the conductive layer from one or more regions corresponding to the first groove and the second groove, and from within the first groove and the second groove; wherein the pattern applied to the second photoresist layer corresponds to the one or more regions corresponding to the first groove and the second groove; wherein the method further comprises: removing the second photoresist layer; and providing a passivation layer fixed to the second side of the conductive layer and extending into the first groove and the second groove.

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