Multi-level heat dissipation structure based on TSV heterogeneous integration and preparation method thereof

Abstract

The invention relates to a multi-level heat dissipation structure based on TSV heterogeneous integration and a preparation method thereof, and belongs to the technical field of integrated circuit packaging heat dissipation, the multi-level heat dissipation structure comprises a base, a manifold chipset, a stacked chipset and a heat dissipation plate set, the base is internally provided with a liquid supply channel and a liquid return channel, and the liquid supply channel and the liquid return channel both penetrate through the two sides of the base; the bottom end of the manifold chipset is bonded to the top end of the base, and a plurality of manifold micro-channels are arranged in the manifold chipset. The bottom end of the stacked chip set is bonded to the top end of the manifold chip set, and a plurality of cooling micro-channels are arranged in the stacked chip set. The bottom end of the heat dissipation plate set is bonded to the top end of the stacked chip set, and a plurality of heat dissipation micro-channels penetrating through the two sides are arranged in the heat dissipation plate set. The inlet and the outlet of the manifold micro-channel, the inlet and the outlet of the cooling micro-channel and the inlet and the outlet of the heat dissipation micro-channel are respectively communicated with the outlet of the liquid supply channel and the inlet of the liquid return channel, so that the heat dissipation path can be greatly shortened, and independent and efficient working heat is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit package heat dissipation, and particularly to a multi-level heat dissipation structure based on TSV heterogeneous integration and a preparation method thereof. Background Art

[0002] As Moore's Law gradually approaches the physical limit, traditional planar integrated circuits face dual challenges in terms of performance improvement and power consumption control. The rapid development of fields such as artificial intelligence, 5G communication, and high-performance computing has put forward almost exponential growth requirements for chip computing power density and energy efficiency. The method of simply relying on process miniaturization to improve integration has become less realistic. The International Technology Roadmap for Semiconductors (ITRS) points out that three-dimensional heterogeneous integration technology is becoming the core path to continue the growth of computing power in the post-Moore era. This technology stacks chips vertically through Through-Silicon Vias (TSVs) and uses the third dimension to achieve three-dimensional integration, which can significantly reduce signal transmission delay and power consumption.

[0003] However, with the continuous increase in the number of stacked layers, the device power density has risen sharply. Under typical operating conditions, the heat flux density has exceeded the magnitude of 1 kW / cm2, and the local hot spot area will exceed 5 kW / cm2. This vertical stacking structure causes heat to continuously accumulate between chip layers, forming a significant thermal coupling effect, in which the intermediate functional layer far from the radiator has a significantly increased thermal resistance due to the circuitous and complex heat dissipation path, and the heat dissipation efficiency drops sharply, which far exceeds the processing range of traditional cooling methods. The thermal management problem has become the key bottleneck restricting the development of three-dimensional packaging technology.

[0004] The embedded microchannel liquid cooling technology directly integrates micron-level fluid channels inside the chip, eliminates the thermal conduction resistance and interface thermal resistance of the package shell and TIM, and shortens the heat transfer path from the chip heating area to the radiator, with extremely high heat dissipation efficiency.

[0005] However, in the three-dimensional stacked chip architecture, there is a contradiction in the spatial layout between TSVs and embedded microchannels. There is an urgent need to develop a three-dimensional stacked chip heat dissipation structure that can realize the collaborative integration of microchannels and TSVs to balance the requirements of high-density interconnection and high-efficiency heat dissipation. Summary of the Invention

[0006] The main purpose of this application is to provide a three-dimensional stacked chip dual-channel multi-level heat dissipation structure based on TSV heterogeneous integration and a preparation method thereof to solve the problem of insufficient heat dissipation efficiency caused by ultra-high density transistor integration in three-dimensional stacked chips. Through multi-level microchannel collaborative heat dissipation and three-dimensional thermal and electrical interconnection design, efficient heat dissipation and electrical signal transmission in the chip stacking structure are realized.

[0007] The technical solution of the present invention to solve the above technical problems is as follows. A multi-level heat dissipation structure based on TSV heterogeneous integration includes: a base, a manifold chip group, a stacked chip group, and a heat dissipation plate group.

[0008] A liquid supply channel and a liquid return channel are provided inside the base, and both the liquid supply channel and the liquid return channel penetrate through both sides of the base; the bottom end of the manifold chip group is bonded to the top end of the base, and a plurality of manifold micro-channels penetrating through both sides are provided inside it; the bottom end of the stacked chip group is bonded to the top end of the manifold chip group, and a plurality of cooling micro-channels penetrating through both sides are provided inside it; the bottom end of the heat dissipation plate group is bonded to the top end of the stacked chip group, and a TSV structure I is electrically connected between the heat dissipation plate group and the stacked chip group. A plurality of heat dissipation micro-channels penetrating through both sides are provided inside the heat dissipation plate group; the inlets and outlets of the manifold micro-channels, the inlets and outlets of the manifold micro-channels, the inlets and outlets of the cooling micro-channels, and the inlets and outlets of the heat dissipation micro-channels are respectively communicated with the outlet of the liquid supply channel and the inlet of the liquid return channel.

[0009] The beneficial effect of the present invention is: breaking through the heat dissipation efficiency limitation of traditional integrated circuit packaging, by using the inlets and outlets of the manifold micro-channels, the inlets and outlets of the manifold micro-channels, the inlets and outlets of the cooling micro-channels, and the inlets and outlets of the heat dissipation micro-channels to be respectively communicated with the outlet of the liquid supply channel and the inlet of the liquid return channel, the heat dissipation path can be greatly shortened, and the working heat of the manifold chip group and the stacked chip group can be independently and efficiently reduced.

[0010] On the basis of the above technical solution, the present invention can also be improved as follows.

[0011] Further, the base includes a lower substrate and an upper substrate. A liquid supply groove and a liquid return groove are provided at the top end of the lower substrate. A liquid supply inlet hole penetrating through the side part of the lower substrate is provided at the bottom of the liquid supply groove, and a liquid return outlet hole penetrating through the side part of the lower substrate is provided at the bottom of the liquid return groove; the bottom end of the upper substrate is bonded to the top end of the lower substrate, and a liquid supply outlet hole communicated with the liquid supply groove is provided on it, and a liquid return inlet hole communicated with the liquid return groove is provided on it; the liquid supply channel is composed of the liquid supply inlet hole, the liquid supply groove, and the liquid supply outlet hole; the liquid return channel is composed of the liquid return inlet hole, the liquid return groove, and the liquid return outlet hole; the bottom end of the manifold chip group is bonded to the top end of the upper substrate; the inlets and outlets of the manifold micro-channels, the inlets and outlets of the manifold micro-channels, the inlets and outlets of the cooling micro-channels, and the inlets and outlets of the heat dissipation micro-channels are respectively communicated with the liquid supply outlet hole and the liquid return inlet hole.

[0012] Further, the manifold chipset includes a manifold adapter board and high-power chips. The bottom end of the manifold adapter board is bonded to the top end of the upper substrate, and a heat dissipation groove is provided at the top end thereof. A liquid inlet hole and a liquid outlet hole are provided at the bottom of the heat dissipation groove. The bottom end of the high-power chip is bonded to the top end of the manifold adapter board, and a plurality of micro-rib members A distributed in an array are fixed to the bottom end thereof corresponding to the heat dissipation groove. The plurality of manifold micro-channels are the gaps between the plurality of micro-rib members A and the bottom of the heat dissipation groove. The liquid supply outlet hole is communicated with the liquid inlet hole. The liquid return inlet hole is communicated with the liquid outlet hole.

[0013] Further, the manifold chipset further includes a plurality of conductive rods. A plurality of first vertical holes are provided on the manifold adapter board. A plurality of second vertical holes are provided on the high-power chip, and the plurality of second vertical holes are respectively arranged opposite to the plurality of first vertical holes. Both ends of the plurality of conductive rods are respectively inserted and fixed in the opposite first vertical holes and second vertical holes.

[0014] Further, the stacked chipset includes a heat sink and an IC chip. The bottom end of the heat sink is bonded to the top end of the high-power chip, and a fixing groove is provided at the top end thereof. A liquid inlet hole A and a liquid discharge hole A are provided at the bottom of the fixing groove. A plurality of micro-rib members B distributed in an array are fixed to the bottom of the fixing groove, and TSV structures II are fixed on the micro-rib members B. The bottom end of the IC chip is bonded to the top end of the heat sink, and the top end thereof is connected to the bottom end of the heat sink group. The TSV structure II is electrically connected to the TSV structure I. The cooling micro-channel is the gap between the plurality of micro-rib members B, the bottom of the fixing groove and the bottom end of the IC chip. The liquid supply outlet hole is communicated with the liquid inlet hole A. The liquid return inlet hole is communicated with the liquid discharge hole A.

[0015] The beneficial effect of the above further improvement is that due to the limited space of the IC chip substrate, the heat sink and the IC chip layer are separately manufactured, and the heat sink integrated with TSV is modularly designed, so that the shape, density of the micro-needle ribs and the TSV layout strategy can be flexibly adjusted to adapt to different power consumption scenarios and signal transmission requirements.

[0016] Further, the heat sink and the IC chip are multiple and arranged in an interleaved manner.

[0017] The beneficial effect of the above further improvement is that the multiple cooling micro-channels formed by the interleaved heat sinks and IC chips are arranged in a two-way countercurrent manner for the multiple cooling micro-channels arranged up and down. By utilizing the vertical heat conduction of the IC chip, the decrease in the heat dissipation efficiency caused by the temperature rise of the fluid is effectively suppressed, ensuring uniform temperature distribution on the surface of the IC chip and improving the reliability of the system.

[0018] Further, the cover plate is made of a transparent material.

[0019] Further, the plurality of micro rib members A, the plurality of micro rib members B, and the plurality of micro rib members C are circular, airfoil-shaped, water droplet-shaped, rectangular, or triangular.

[0020] In addition, a preparation method of a multi-level heat dissipation structure based on TSV heterogeneous integration is provided, including a multi-level heat dissipation structure based on TSV heterogeneous integration. The specific steps are as follows:

[0021] S1. Form heat dissipation microchannels on a silicon substrate by deep reactive ion etching (DRIE), laser drill liquid inlet holes B and liquid discharge holes B, and seal them by bonding with a cover plate;

[0022] S2. Manufacture TSVs on an IC chip and a heat sink respectively by using the TSV process, then etch micro rib members B with a certain depth in the bottom of the heat sink through DRIE, embed the TSV structure II into the micro rib members B, and alternately stack and bond the IC chip and the heat sink by using low-temperature eutectic bonding;

[0023] S3. Directly etch manifold microchannels and second vertical holes on a high-power chip substrate by DRIE. Similarly, etch heat dissipation grooves, liquid inlet holes, liquid discharge holes, and first vertical holes on the first side of the manifold adapter plate, then bond the first side of the manifold adapter plate to the high-power chip substrate, align the second vertical holes with the first vertical holes, fill the second vertical holes and the first vertical holes by using a conductive rod or electroplating, and electroplate a redistribution layer (RDL) on the second side of the manifold adapter plate;

[0024] S4. Bond the obtained manifold chip group and stacked chip group by using the bump process and a sealing ring to achieve signal interconnection and sealing of the vertical flow path;

[0025] S5. Finally, package the three-dimensional stacked structure with a base. Description of the Drawings

[0026] Figure 1 It is an exploded structural schematic diagram of a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0027] Figure 2 It is an exploded structural schematic diagram of a heat dissipation plate group in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0028] Figure 3 It is an exploded structural schematic diagram of a stacked chip group in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0029] Figure 4 It is a partial sectional structure of a manifold chip group in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0030] Figure 5 It isFigure 4 Schematic diagram of the partially enlarged structure at location A;

[0031] Figure 6 Schematic diagram of the manifold adapter plate in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0032] Figure 7 Schematic diagram of a high-power chip in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention;

[0033] Figure 8 Schematic diagram of the exploded structure of the base in a multi-level heat dissipation structure based on TSV heterogeneous integration according to the present invention.

[0034] In the attached drawings, the list of components represented by each reference numeral is as follows:

[0035] 1. Base, 11. Lower substrate, 111. Liquid supply groove, 112. Liquid return groove, 12. Upper substrate, 121. Liquid supply outlet hole, 122. Liquid return inlet hole, 2. Manifold chip group, 21. Manifold adapter plate, 211. Heat dissipation groove, 212. Liquid inlet hole, 213. Liquid outlet hole, 214. First vertical hole, 22. High-power chip, 221. Micro-rib member A, 222. Second vertical hole, 3. Stacked chip group, 31. Heat sink, 311. Fixed groove, 312. Liquid inlet hole A, 313. Drain hole A, 314. Micro-rib member B, 32. IC chip, 4. Heat dissipation plate group, 41. Heat dissipation plate, 411. Installation groove, 412. Liquid inlet hole B, 413. Drain hole B, 414. Micro-rib member C, 42. Cover plate, 5. TSV structure I. Detailed implementation manners

[0036] The principles and features of the present invention will be described below with reference to the attached drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0037] As Figure 1 shown, a multi-level heat dissipation structure based on TSV heterogeneous integration includes: a base 1, a manifold chip group 2, a stacked chip group 3, and a heat dissipation plate group 4.

[0038] The inside of the base 1 is provided with a liquid supply channel and a liquid return channel, both of which penetrate through both sides of the base 1; the bottom end of the manifold chip group 2 is bonded to the top end of the base 1 and there are multiple manifold microchannels inside it that all penetrate through both sides; the bottom end of the stacked chip group 3 is bonded to the top end of the manifold chip group 2 and there are multiple cooling microchannels inside it that all penetrate through both sides; the bottom end of the heat dissipation plate group 4 is bonded to the top end of the stacked chip group 3 and a TSV structure I 5 is electrically connected between the heat dissipation plate group 4 and the stacked chip group 3, and there are multiple heat dissipation microchannels inside the heat dissipation plate group 4 that all penetrate through both sides; the inlets and outlets of the manifold microchannels, the inlets and outlets of the manifold microchannels, the inlets and outlets of the cooling microchannels, and the inlets and outlets of the heat dissipation microchannels are respectively communicated with the outlet of the liquid supply channel and the inlet of the liquid return channel.

[0039] As Figure 8 shown, in some specific embodiments, the base 1 may include a lower substrate 11 and an upper substrate 12. A liquid supply groove 111 and a liquid return groove 112 are provided at the top end of the lower substrate 11. A liquid supply inlet hole penetrating through the side part of the lower substrate 11 is provided at the bottom of the liquid supply groove 111, and a liquid return outlet hole penetrating through the side part of the lower substrate 11 is provided at the bottom of the liquid return groove 112; the bottom end of the upper substrate 12 is bonded to the top end of the lower substrate 11, and a liquid supply outlet hole 121 communicated with the liquid supply groove 111 is provided on it, and a liquid return inlet hole 122 communicated with the liquid return groove 112 is provided on it; the liquid supply channel is composed of the liquid supply inlet hole, the liquid supply groove 111 and the liquid supply outlet hole 121; the liquid return channel is composed of the liquid return inlet hole 122, the liquid return groove 112 and the liquid return outlet hole; the bottom end of the manifold chip group 2 is bonded to the top end of the upper substrate 12; the inlets and outlets of the manifold microchannels, the inlets and outlets of the manifold microchannels, the inlets and outlets of the cooling microchannels, and the inlets and outlets of the heat dissipation microchannels are respectively communicated with the liquid supply outlet hole 121 and the liquid return inlet hole 122.

[0040] As Figures 4 - 7 shown, in some specific embodiments, the manifold chip group 2 may include a manifold adapter plate 21 and a high-power chip 22. The bottom end of the manifold adapter plate 21 is bonded to the top end of the upper substrate 12 and a heat dissipation groove 211 is provided at its top end. A liquid inlet hole 212 and a liquid outlet hole 213 are provided at the bottom of the heat dissipation groove 211; the bottom end of the high-power chip 22 is bonded to the top end of the manifold adapter plate 21 and a plurality of micro rib members A221 distributed in an array are fixed at its bottom end corresponding to the heat dissipation groove 211; the multiple manifold microchannels are the gaps between the plurality of micro rib members A221 and the bottom of the heat dissipation groove 211; the liquid supply outlet hole 121 is communicated with the liquid inlet hole 212; the liquid return inlet hole 122 is communicated with the liquid outlet hole 213.

[0041] As Figure 5As shown, in some specific embodiments, the manifold chipset 2 may further include a plurality of conductive rods. The manifold adapter plate 21 is provided with a plurality of first vertical holes 214; the high-power chip 22 is provided with a plurality of second vertical holes 222, and the plurality of second vertical holes 222 are respectively arranged opposite to the plurality of first vertical holes 214; both ends of the plurality of conductive rods are respectively inserted and fixed in the oppositely arranged first vertical holes 214 and second vertical holes 222.

[0042] As Figure 3 shown, in some specific embodiments, the stacked chipset 3 may include a heat sink 31 and an IC chip 32. The bottom end of the heat sink 31 is bonded to the top end of the high-power chip 22 and its top end is provided with a fixing groove 311. The bottom of the fixing groove 311 is provided with a liquid inlet hole A312 and a liquid discharge hole A313. A plurality of micro ribs B314 distributed in an array are fixed on the bottom of the fixing groove 311 and TSV structures II are fixed on the micro ribs B314; the bottom end of the IC chip 32 is bonded to the top end of the heat sink 31 and its top end is connected to the bottom end of the heat sink plate group 4; the TSV structure II is electrically connected to the TSV structure I; the cooling microchannel is the gap between the plurality of micro ribs B314, the bottom of the fixing groove 311 and the bottom end of the IC chip 32; the liquid supply outlet hole 121 is communicated with the liquid inlet hole A312; the liquid return inlet hole 122 is communicated with the liquid discharge hole A313.

[0043] As Figure 3 shown, in some specific embodiments, the heat sink 31 and the IC chip 32 are multiple and arranged in an alternating manner, and the higher heat sink 31 is bonded to the lower IC chip 32 for connection.

[0044] As Figure 2 shown, in some specific embodiments, the heat sink plate group 4 may include a heat sink plate 41 and a cover plate 42. The bottom end of the heat sink plate 41 is bonded to the top end of the IC chip 32 and its top surface is provided with an installation groove 411. The bottom of the installation groove 411 is provided with a liquid inlet hole B412 and a liquid discharge hole B413 and a plurality of micro ribs C414 distributed in an array are fixed on its bottom; the bottom end of the cover plate 42 is bonded to the top end of the heat sink plate 41; the heat dissipation microchannel is the gap between the bottom of the installation groove 411, the plurality of micro ribs C414 and the cover plate 42; the liquid supply outlet hole 121 is communicated with the liquid inlet hole B412; the liquid return inlet hole 122 is communicated with the liquid discharge hole B413.

[0045] Specifically, the cover plate 42 may be made of a transparent material.

[0046] Specifically, the plurality of micro ribs A221, the plurality of micro ribs B314 and the plurality of micro ribs C414 are circular, wing-shaped, water-drop-shaped, rectangular or triangular.

[0047] In addition, a preparation method of a multi-level heat dissipation structure based on TSV heterogeneous integration is provided, which is characterized by including the multi-level heat dissipation structure based on TSV heterogeneous integration, and the specific steps are as follows:

[0048] S1. Form heat dissipation microchannels on a silicon substrate by deep reactive ion etching (DRIE), laser drill inlet and outlet holes B412 and drain hole B413, and bond and seal them with a cover plate 42.

[0049] S2. Use the TSV process to fabricate TSVs on the IC chip 32 and the heat sink 31 respectively. Then, etch micro ribs B314 with a certain depth in the bottom of the heat sink 31 through DRIE, embed the TSV structure II into the inside of the micro ribs B314, and alternately stack and bond the IC chip 32 and the heat sink 31 through low-temperature eutectic bonding.

[0050] S3. Directly etch a manifold microchannel and a second vertical hole 222 on the substrate of the high-power chip 22 through DRIE. Similarly, etch a heat dissipation groove 211, an inlet hole 212, an outlet hole 213 and a first vertical hole 214 on the first side of the manifold adapter plate 21. Then, bond the first side of the manifold adapter plate 21 to the substrate of the high-power chip 22, align the second vertical hole 222 with the first vertical hole 214, fill the second vertical hole 222 and the first vertical hole 214 by means of a conductive rod or electroplating, and electroplate a redistribution layer RDL on the second side of the manifold adapter plate 21.

[0051] S4. Bond the obtained manifold chip group 2 and stacked chip group 3 through the bump process and a sealing ring to achieve signal interconnection and sealing of the vertical flow path.

[0052] S5. Finally, package the three-dimensional stacked structure with the base 1.

[0053] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-level heat dissipation structure based on TSV heterogeneous integration, characterized in that, Including: A base (1), an internal liquid supply channel and a liquid return channel are provided inside the base (1), and both the liquid supply channel and the liquid return channel penetrate through both sides of the base (1); A manifold chip group (2), the bottom end of the manifold chip group (2) is bonded to the top end of the base (1), and a plurality of manifold micro-channels that penetrate through both sides are provided inside; A stacked chip group (3), the bottom end of the stacked chip group (3) is bonded to the top end of the manifold chip group (2), and a plurality of cooling micro-channels that penetrate through both sides are provided inside; A heat dissipation plate group (4), the bottom end of the heat dissipation plate group (4) is bonded to the top end of the stacked chip group (3), and a TSV structure I (5) is electrically connected between the heat dissipation plate group (4) and the stacked chip group (3), and a plurality of heat dissipation micro-channels that penetrate through both sides are provided inside the heat dissipation plate group (4); The inlets and outlets of the manifold micro-channels, the inlets and outlets of the manifold micro-channels, the inlets and outlets of the cooling micro-channels, and the inlets and outlets of the heat dissipation micro-channels are respectively communicated with the outlet of the liquid supply channel and the inlet of the liquid return channel.

2. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 1, wherein The base (1) includes a lower substrate (11) and an upper substrate (12). A liquid supply groove (111) and a liquid return groove (112) are provided at the top end of the lower substrate (11). A liquid supply inlet hole penetrating through the side part of the lower substrate (11) is provided at the bottom of the liquid supply groove (111), and a liquid return outlet hole penetrating through the side part of the lower substrate (11) is provided at the bottom of the liquid return groove (112); the bottom end of the upper substrate (12) is bonded to the top end of the lower substrate (11), and a liquid supply outlet hole (121) communicated with the liquid supply groove (111) is provided thereon, and a liquid return inlet hole (122) communicated with the liquid return groove (112) is provided thereon; the liquid supply channel is composed of the liquid supply inlet hole, the liquid supply groove (111) and the liquid supply outlet hole (121); the liquid return channel is composed of the liquid return inlet hole (122), the liquid return groove (112) and the liquid return outlet hole; the bottom end of the manifold chip group (2) is bonded to the top end of the upper substrate (12); the inlets and outlets of the manifold micro-channels, the inlets and outlets of the manifold micro-channels, the inlets and outlets of the cooling micro-channels, and the inlets and outlets of the heat dissipation micro-channels are respectively communicated with the liquid supply outlet hole (121) and the liquid return inlet hole (122).

3. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 2, characterized in that, The manifold chipset (2) includes a manifold adapter board (21) and high-power chips (22). The bottom end of the manifold adapter board (21) is bonded to the top end of the upper substrate (12), and its top end is provided with heat dissipation grooves (211). The bottom of the heat dissipation grooves (211) is provided with a liquid inlet hole (212) and a liquid outlet hole (213). The bottom end of the high-power chips (22) is bonded to the top end of the manifold adapter board (21), and a plurality of micro-rib members A (221) distributed in an array are fixed to the bottom end thereof corresponding to the heat dissipation grooves (211). The plurality of manifold micro-channels are the gaps between the plurality of micro-rib members A (221) and the bottom of the heat dissipation grooves (211). The liquid supply outlet hole (121) is communicated with the liquid inlet hole (212). The liquid return inlet hole (122) is communicated with the liquid outlet hole (213).

4. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 3, characterized in that The manifold chipset (2) further includes a plurality of conductive rods. The manifold adapter board (21) is provided with a plurality of first vertical holes (214). The high-power chips (22) are provided with a plurality of second vertical holes (222). The plurality of second vertical holes (222) are respectively arranged opposite to the plurality of first vertical holes (214). Both ends of the plurality of conductive rods are respectively inserted and fixed in the oppositely arranged first vertical holes (214) and second vertical holes (222).

5. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 3, characterized in that, The stacked chipset (3) includes a heat sink (31) and an IC chip (32). The bottom end of the heat sink (31) is bonded to the top end of the high-power chips (22), and its top end is provided with a fixing groove (311). The bottom of the fixing groove (311) is provided with a liquid inlet hole A (312) and a liquid discharge hole A (313). A plurality of micro-rib members B (314) distributed in an array are fixed to the bottom of the fixing groove (311), and TSV structures II are fixed to the micro-rib members B (314). The bottom end of the IC chip (32) is bonded to the top end of the heat sink (31), and its top end is connected to the bottom end of the heat sink group (4). The TSV structure II is electrically connected to the TSV structure I. The cooling micro-channels are the gaps between the plurality of micro-rib members B (314), the bottom of the fixing groove (311), and the bottom end of the IC chip (32). The liquid supply outlet hole (121) is communicated with the liquid inlet hole A (312). The liquid return inlet hole (122) is communicated with the liquid discharge hole A (313).

6. The multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 5, characterized in that, The heat sink (31) and the IC chip (32) are arranged in an alternating manner, and the high heat sink (31) is connected to the low IC chip (32) through the TSV structure I (5).

7. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 5, characterized in that, The heat dissipation plate group (4) includes a heat dissipation plate (41) and a cover plate (42). The bottom end of the heat dissipation plate (41) is bonded to the top end of the IC chip (32), and an installation groove (411) is provided on its top surface. A liquid inlet hole B (412) and a liquid discharge hole B (413) are provided at the bottom of the installation groove (411), and a plurality of micro-rib members C (414) distributed in an array are fixed to the bottom of the groove; the bottom end of the cover plate (42) is bonded to the top end of the heat dissipation plate (41); the heat dissipation micro-channel is the gap between the bottom of the installation groove (411), the plurality of micro-rib members C (414) and the cover plate (42); the liquid supply outlet hole (121) is communicated with the liquid inlet hole B (412); the liquid return inlet hole (122) is communicated with the liquid discharge hole B (413).

8. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 7, characterized in that, The cover plate (42) is made of a transparent material.

9. A multi-level heat dissipation structure based on TSV heterogeneous integration according to claim 7, characterized in that The plurality of micro-rib members A (221), the plurality of micro-rib members B (314) and the plurality of micro-rib members C (414) are circular, airfoil-shaped, water droplet-shaped, rectangular or triangular.

10. A preparation method of a multi-level heat dissipation structure based on TSV heterogeneous integration, characterized in that, It includes the multi-level heat dissipation structure based on TSV heterogeneous integration according to any one of claims 1-9, and the specific steps are as follows: S1. Form a heat dissipation micro-channel on the silicon substrate by deep reactive ion etching (DRIE), laser drill the liquid inlet hole B (412) and the liquid discharge hole B (413), and seal them by bonding with the cover plate (42); S2. Use the TSV process to manufacture TSVs on the IC chip (32) and the heat sink (31) respectively, and then etch micro-rib members B (314) with a certain depth in the bottom of the heat sink (31) by DRIE, so that the TSV structure II is embedded inside the micro-rib members B (314), and the IC chip (32) and the heat sink (31) are alternately stacked and bonded by low-temperature eutectic bonding; S3. Directly etch the manifold micro-channel and the second vertical hole (222) on the substrate of the high-power chip (22) by DRIE. Similarly, etch the heat dissipation groove (211), the liquid inlet hole (212), the liquid outlet hole (213) and the first vertical hole (214) on the first side of the manifold adapter plate (21), and then bond the first side of the manifold adapter plate (21) to the substrate of the high-power chip (22), align the second vertical hole (222) with the first vertical hole (214), and fill the second vertical hole (222) and the first vertical hole (214) by using a conductive rod or electroplating, and electroplate a redistribution layer (RDL) on the second side of the manifold adapter plate (21); S4. Bond the obtained manifold chip group (2) and stacked chip group (3) through the bump process and the sealing ring to achieve signal interconnection and sealing of the vertical flow path; S5. Finally, package the three-dimensional stacked structure with the base (1).

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