Bootstrap circuit, bootstrap voltage detection circuit and method thereof, and bootstrap voltage control circuit and method

Abstract

The invention discloses a bootstrap circuit in a BUCK circuit, a bootstrap voltage detection circuit and method thereof, and a control circuit and method thereof, the bootstrap circuit comprises a voltage stabilization detection circuit and an undervoltage detection circuit of the bootstrap circuit in the BUCK circuit, an undervoltage signal and a voltage stabilization signal can be output according to different bootstrap voltages, and when the bootstrap voltage is lower than a voltage stabilization threshold value, the undervoltage signal is output. Controlling the pull-up control circuit to charge the bootstrap capacitor; when the bootstrap voltage is lower than the under-voltage threshold value, an under-voltage protection signal is output to the logic module for processing and then protection measures are taken, and the under-voltage circuit has a hysteresis function. According to the invention, under-voltage and voltage stabilization control signals can be output according to the magnitude of the bootstrap voltage, so that the magnitude of the bootstrap voltage is controlled in time, and the BUCK circuit and the corresponding BUCK chip are protected.

Description

Technical Field

[0001] The present invention belongs to the field of bootstrap voltage detection and control in the bootstrap circuit of a BUCK circuit, and particularly relates to a bootstrap circuit, a bootstrap voltage detection circuit and method, a control circuit and method thereof. Background Art

[0002] DC-DC (Direct Current-Direct Current) power management chips are widely used in people's daily lives. As the most common type of power management chip, the BUCK (step-down) chip outputs a stable voltage by controlling the periodic conduction of a power switch transistor. The drain of the power switch transistor is usually directly connected to the input voltage, the source is connected to an off-chip inductor, and its gate voltage is generated by a control signal inside the BUCK chip. Some on-chip integrated power switch transistors are limited by the process and have a breakdown voltage limit. The gate-source voltage has a maximum value. Usually, a bootstrap circuit is required to generate a suitable voltage rail to supply the gate voltage control circuit, so as to generate a gate control signal to drive the power switch transistor.

[0003] In a mature BUCK chip, its bootstrap circuit needs to maintain a relatively stable voltage and has an undervoltage protection function when the bootstrap voltage is too small. Since the bootstrap circuit works on a floating power rail and its power rail is not very stable, there is still a lack of a specific and effective solution for how to detect the magnitude of the bootstrap voltage in real time, and charge and discharge the bootstrap capacitor according to the magnitude of the bootstrap voltage to timely adjust the magnitude of the bootstrap voltage.

[0004] As Figure 1 shown, CN112436488A discloses an undervoltage protection circuit for a DC-DC bootstrap power supply, which consists of an undervoltage detection circuit, a spike control circuit, and a pull-down circuit. The N-divided signal CLK_NT of the DC-DC system clock is used as the clock signal of the spike control circuit. When the bootstrap power supply is undervoltage, during the period when the bootstrap power supply voltage reaches the recovery threshold of undervoltage protection, the pull-down circuit is in a periodic intermittent working mode, that is, within every N CLK cycles, the pull-down circuit is only turned on for a fixed time within one CLK cycle to charge the bootstrap capacitor, and within the remaining time of every N CLK cycles, the upper switch transistor is normally turned on and off under the control of the system loop. In this way, when the bootstrap power supply is undervoltage under large duty cycle or even 100% duty cycle conditions, the undervoltage protection circuit of the bootstrap power supply can charge the bootstrap capacitor while still allowing the upper switch transistor to have enough time to conduct, so that after the undervoltage release of the bootstrap power supply, the DC-DC output voltage will not have a large "spike".

[0005] Although CN112436488A discloses that when the bootstrap power supply is under-voltage, during the period when the bootstrap power supply voltage reaches the recovery threshold of under-voltage protection, the pull-down circuit is in a periodic intermittent working mode, this solution is limited to the implementation of the under-voltage protection circuit of the bootstrap power supply and does not involve the detection of the magnitude of the bootstrap voltage and under-voltage detection.

[0006] As Figure 2 shown, CN110994996B discloses an asynchronous buck DC-DC chip and a bootstrap circuit based on the asynchronous buck DC-DC chip. As Figure 2 shown, the DC-DC chip includes an input terminal, a first output terminal and a second output terminal. The input terminal is connected to the input voltage. The voltage difference between the first output terminal and the second output terminal is V BOOT , where: a plurality of first MOS transistors are provided between the input terminal and the first output terminal; a BOOT reference voltage unit is provided between the gate of the first MOS transistor and the second output terminal; a second MOS transistor is provided between the second output terminal and the reference potential, and the second MOS transistor is driven by a logic control unit. The bootstrap circuit includes: an asynchronous buck DC-DC chip; a bootstrap capacitor; an inductor; an output capacitor and a load resistor. By connecting the lower end of the BOOT reference voltage unit to the second output terminal SW, the problem that the bootstrap capacitor C BOOT cannot be charged under light load conditions is solved.

[0007] Although CN110994996B discloses that by connecting the lower end of the BOOT reference voltage unit to the second output terminal SW, the problem that the bootstrap capacitor C BOOT cannot be charged under light load conditions is solved; by controlling the state of the second MOS transistor, sufficient voltage space can be provided to charge the bootstrap capacitor C BOOT , which is applicable to application conditions with a very low input voltage, and can control the number of charging operations of the bootstrap capacitor C BOOT , reducing the disturbance to normal operation, but like CN112436488A, it does not involve the detection of the magnitude of the bootstrap voltage and under-voltage detection.

[0008] In summary, for the bootstrap circuit in the existing BUCK chip, generally, according to the magnitude of different bootstrap voltages, the charging and discharging of the bootstrap capacitor are controlled under different working conditions of the BUCK chip. However, the prior art does not output under-voltage and voltage stabilization control signals according to the magnitude of the bootstrap voltage, so the magnitude of the bootstrap voltage cannot be controlled in time. Summary of the Invention

[0009] The object of the present invention is to provide a bootstrap circuit, a bootstrap voltage detection circuit and method, a control circuit and method in a BUCK circuit, aiming at the deficiencies of the above-mentioned prior art.

[0010] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A bootstrap voltage detection circuit for a bootstrap circuit in a BUCK circuit, characterized by comprising a current generation circuit, an undervoltage detection circuit, and / or a voltage regulation detection circuit; wherein, Current generation circuit: used to output a mirror current reference source I1 proportional to V BST to the undervoltage detection circuit; and / or, output a mirror current reference source I2 proportional to V BST to the voltage regulation detection circuit; wherein, V BST is the voltage difference between BST and SW; Undervoltage detection circuit: used to receive I1 and output an identification signal Z2 when V BST is lower than the undervoltage threshold; Voltage regulation detection circuit: used to receive I2 and output an identification signal Z3 when V BST is lower than the voltage regulation threshold.

[0011] Furthermore, the current generation circuit: is also used to output an identification signal Z1; wherein, when the I1 and / or I2 output by the current generation circuit is unstable, Z1 is at a high level; when the I1 and / or I2 output by the current generation circuit is stable, Z1 is at a low level.

[0012] Based on the same inventive concept, the present invention also provides a method for detecting the bootstrap voltage of a bootstrap circuit in a BUCK circuit, characterized by using the above-mentioned bootstrap voltage detection circuit; including: The current generation circuit outputs a mirror current reference source I1 proportional to V BST to the undervoltage detection circuit; the undervoltage detection circuit receives I1 and outputs an identification signal Z2 when V BST is lower than the undervoltage threshold; and / or, The current generation circuit outputs a mirror current reference source I2 proportional to V BST to the voltage regulation detection circuit; the voltage regulation detection circuit receives I2 and outputs an identification signal Z3 when V BST is lower than the voltage regulation threshold.

[0013] Furthermore, it also includes: The current generation circuit outputs an identification signal Z1; wherein, when the I1 and / or I2 output by the current generation circuit is unstable, Z1 is at a high level; when the I1 and / or I2 output by the current generation circuit is stable, Z1 is at a low level.

[0014] Based on the same inventive concept, the present invention also provides a bootstrap voltage control circuit for a bootstrap circuit in a BUCK circuit, characterized by including the above-mentioned bootstrap voltage detection circuit; wherein: The identification signal Z2 is used to turn off the high-side switch transistor and control the conduction of the bootstrap voltage pull-up transistor to charge the BOOT capacitor. The identification signal Z3 is used to control the charging of the BOOT capacitor when the high-side switch transistor is turned off.

[0015] Furthermore, the current generation circuit: is also used to output the identification signal Z1; wherein, when I1 and / or I2 output by the current generation circuit are unstable, Z1 is at a high level, and Z1 is used to turn off the high-side switch transistor and control the turn-off of the bootstrap voltage pull-up transistor; when I1 and / or I2 output by the current generation circuit are stable, Z1 is at a low level.

[0016] Based on the same inventive concept, the present invention also provides a method for controlling the bootstrap voltage of a bootstrap circuit in a BUCK circuit, which is characterized by using the said bootstrap voltage control circuit, including: When V BST is lower than the undervoltage threshold, the identification signal Z2 turns off the high-side switch transistor and controls the conduction of the bootstrap voltage pull-up transistor to charge the BOOT capacitor; When V BST is lower than the regulated voltage threshold, the identification signal Z3 controls the charging of the BOOT capacitor when the high-side switch transistor is turned off.

[0017] Furthermore, when I1 and / or I2 output by the current generation circuit are unstable, the current generation circuit outputs the identification signal Z1, Z1 is at a high level, and Z1 turns off the high-side switch transistor and controls the turn-off of the bootstrap voltage pull-up transistor.

[0018] Based on the same inventive concept, the present invention also provides a bootstrap circuit in a BUCK circuit, which is characterized by including the said bootstrap voltage detection circuit.

[0019] Based on the same inventive concept, the present invention also provides a BUCK circuit, which is characterized by including the said bootstrap circuit.

[0020] Compared with the prior art, the present invention includes a regulated voltage detection circuit and an undervoltage detection circuit for the bootstrap circuit in the BUCK circuit, and can output an undervoltage signal and a regulated voltage signal according to different magnitudes of the bootstrap voltage. When the bootstrap voltage is lower than the regulated voltage threshold, it controls the pull-up control circuit to charge the bootstrap capacitor; when the bootstrap voltage is lower than the undervoltage threshold, it outputs an undervoltage protection signal to the logic module for processing and then takes protection measures, and the undervoltage circuit has a hysteresis function. The present invention can output undervoltage and regulated voltage control signals according to the magnitude of the bootstrap voltage, so as to control the magnitude of the bootstrap voltage in a timely manner and protect the BUCK circuit and the corresponding BUCK chip. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the undervoltage protection circuit of the DC-DC bootstrap power supply of the prior art I.

[0022] Figure 2 Schematic diagram of an asynchronous buck DC-DC chip of the prior art 2 and a bootstrap circuit based on the asynchronous buck DC-DC chip.

[0023] Figure 3 Schematic diagram of a bootstrap voltage detection circuit in the bootstrap circuit of the BUCK circuit of the present invention.

[0024] Figure 4 For Figure 3 Schematic diagram of a current generation circuit in

[0025] Figure 5 For Figure 3 Schematic diagram of an undervoltage detection circuit in

[0026] Figure 6 For Figure 3 Schematic diagram of a voltage regulation detection circuit in Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] The meanings of the Chinese and English symbols in the present invention are described as follows: DC-DC: Direct Current-Direct Current, direct current - direct current BUCK: Step-down BST: Boost bootstrap SW: Switch switch The purpose of the present invention is to provide a voltage regulation control circuit and an undervoltage detection circuit in an asynchronous peak current mode BUCK chip to solve the problem of the stability of the bootstrap voltage in the BUCK chip and provide a protection function for the BUCK circuit under undervoltage conditions. To achieve the above purpose, the solution provided by the present invention is as follows: As Figure 3 shown, the bootstrap voltage detection circuit of the bootstrap circuit in the BUCK circuit includes: Current generation circuit 1; an undervoltage detection circuit 2 for detecting whether the voltage difference V BST between BST and SW is lower than the undervoltage threshold; a voltage regulation detection circuit 3 for detecting whether the voltage difference V BST between BST and SW reaches a preset value (lower than the voltage regulation threshold).

[0029] Current generating circuit 1 is used to output the current with V BST The mirror current reference source I1 is proportional to the undervoltage detection circuit 2; the output is proportional to V BST The proportional mirror current reference source I2 is sent to the voltage stabilization detection circuit 3; where V BST is the voltage difference between BST and SW.

[0030] The current generating circuit 1 is further configured to output an identification signal Z1; when I1 and / or I2 output by the current generating circuit 1 is unstable, Z1 is at a high level; when I1 and / or I2 output by the current generating circuit 1 is stable, Z1 is at a low level.

[0031] Undervoltage detection circuit: used to receive I1 and BST When the voltage is lower than the undervoltage threshold, the identification signal Z2 is output.

[0032] Voltage stabilization detection circuit: used to receive I2 and BST When the voltage is lower than the voltage regulation threshold, an identification signal Z3 is output.

[0033] The current generating circuit 1 is at voltage V BST When it reaches a certain value, the current reference output is relatively stable, the output identification signal Z1 jumps from high level to low level, and the output mirror current reference source is sent to the control voltage stabilization detection circuit 3 and the undervoltage detection circuit 2 to start working. BST When the voltage is lower than the undervoltage threshold, the undervoltage flag signal Z2 jumps, controls the switch in the BUCK chip to turn off and controls the circuit to charge the BOOT capacitor; when V BST When the voltage is lower than the voltage regulation threshold, the voltage regulation identification signal Z3 jumps, controlling the BUCK chip to charge the BOOT capacitor when the switch tube is turned off until the VBST voltage reaches the voltage regulation threshold.

[0034] In this embodiment, the description of voltage stabilization and undervoltage is as follows: 1. Under normal working conditions, the gate-source drive voltage of the high-side switch tube - that is, the voltage from SW to BST V BST The voltage is usually maintained at around 5V. The voltage regulation detection is to ensure that the voltage from SW to BST is maintained at around 5V. When the voltage from SW to BST is lower than 5V, the flag signal Z3 output by the voltage regulation detection circuit 3 will control the circuit to charge the BOOT capacitor when the high-side switch is turned off. Charging will stop when it exceeds 5V.

[0035] In fact, when the duty cycle is relatively small, the turn-off time of the high-side switch tube is short, and the short charging time of the bootstrap capacitor will cause the voltage from SW to BST to be lower than 5V; the voltage range from 2.1V to 5V from SW to BST can make the high-side transistor conduct normally, and a voltage lower than 2.1V will cause the high-side switch tube to be in an abnormal switching state. Undervoltage detection is to detect whether the voltage from SW to BST is lower than 2.1V. When the voltage from SW to BST is lower than 2.1V, the identification signal Z2 output by the undervoltage detection circuit 2 will forcibly turn off the high-side switch tube and control the conduction of the bootstrap voltage pull-up tube to charge the BOOT capacitor.

[0036] 2. The detection range of the regulated voltage detection is about 5V, and the detection range of the undervoltage detection is about 2.1V. When the voltage from SW to BST is lower than 2.1V, both regulated voltage problems and undervoltage problems will be detected simultaneously.

[0037] In the present invention, Z1 indicates whether the current reference output reaches a stable state. When the current reference does not reach a stable state, the high-side operation of the circuit is unstable. At this time, Z1 will be at a high level and control the gate voltage of the high-side switch tube to be pulled down, and the entire buck circuit will not be controlled by feedback to switch the high-side switch tube.

[0038] When the current reference is not stable and Z1 is at a high level, the current reference will be normally mirrored and output to the undervoltage detection circuit 2 and the regulated voltage detection circuit 3. The output states of Z2 and Z3 may be incorrect, but at this time Z1 will perform a logical operation with Z2 and Z3 and mask Z2 and Z3, thereby directly turning off the high-side switch tube and controlling the bootstrap voltage pull-up tube to turn off.

[0039] As Figure 4 shown, specifically, the current generation circuit 1 is a self-biased current source generation circuit proportional to the voltage difference between BST and SW. Figure 4 The output currents I1 and I2 of the current generation circuit 1 in Figure 5 are respectively used as the current sources of the undervoltage detection circuit 2 and the regulated voltage detection circuit 3 and are correspondingly connected to the Figure 6 corresponding positions in

[0040] As Figure 4As shown, the current generation circuit 1 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M13, a fifth PMOS transistor M18, a sixth PMOS transistor M21, a first NMOS transistor M4, a second NMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9, a seventh PMOS transistor M10, a seventh NMOS transistor M11, an eighth NMOS transistor M12, a ninth NMOS transistor M14, a tenth NMOS transistor M15, an eleventh NMOS transistor M16, a twelfth NMOS transistor M17, a thirteenth NMOS transistor M19, a fourteenth NMOS transistor M20, a first resistor R1, a second resistor R2, and an OR gate OR1; where: The gate and drain of the first PMOS transistor M1 are connected, and are connected to the gate of the second PMOS transistor M2, the gate of the third PMOS transistor M3, the gate of the fourth PMOS transistor M13, the drain of the first NMOS transistor M4, and the drain of the second NMOS transistor M5. The source of the first PMOS transistor M1 is connected to the bootstrap voltage BST; The drain of the second PMOS transistor M2 is connected to the gate of the second NMOS transistor M5, the gates and drains of the third NMOS transistor M6 and the seventh NMOS transistor M11. The source of the second PMOS transistor M2 is connected to the bootstrap voltage BST; The drain of the third PMOS transistor M3 is connected to the gate of the fifth NMOS transistor M8, the gates and drains of the sixth NMOS transistor M9 and the eighth NMOS transistor M12, and the gates of the seventh PMOS transistor M10. The source of the third PMOS transistor M3 is connected to the bootstrap voltage BST; The drain of the fourth PMOS transistor M13 is connected to the gates and drains of the ninth NMOS transistor M14 and the eleventh NMOS transistor M16, and the gates of the thirteenth NMOS transistor M19. The source of the fourth PMOS transistor M13 is connected to the bootstrap voltage BST; The gate and drain of the fifth PMOS transistor M18 are connected, and are connected to the gate of the sixth PMOS transistor M21 and the drain of the thirteenth NMOS transistor M19. The source of the fifth PMOS transistor M18 is connected to the bootstrap voltage BST; The drain of the sixth PMOS transistor M21 outputs a current I2, which is the current mirror output of the first PMOS transistor M1, and Figure 6 is connected to the drain of the first NMOS transistor M7 in the voltage stabilization detection circuit 3, providing a current source for the operation of the voltage stabilization detection circuit 3. The source of the sixth PMOS transistor M21 is connected to the bootstrap voltage BST; The gate of the first NMOS transistor M4 is connected to the drain of the seventh PMOS transistor M10, the drain of the seventh NMOS transistor M11, and one end of the OR gate OR1. The source of the first NMOS transistor M4 is connected to the drain of the fourth NMOS transistor M7; The source of the second NMOS transistor M5 is connected to the drain of the fifth NMOS transistor M8; The source of the third NMOS transistor M6 is connected to the SW voltage; The source of the fourth NMOS transistor M7 is connected to the source of the fifth NMOS transistor M8 through a first resistor R1 and is connected to the SW voltage through a second resistor R2; The source of the sixth NMOS transistor M9 is connected to the SW voltage; The source of the seventh PMOS transistor M10 is connected to the bootstrap voltage BST; The source of the seventh NMOS transistor M11 is connected to the drain of the eighth NMOS transistor M12; The source of the eighth NMOS transistor M12 is connected to the SW voltage; The source of the ninth NMOS transistor M14 is connected to the gate and drain of the tenth NMOS transistor M15, the gate of the twelfth NMOS transistor M17, and the gate of the fourteenth NMOS transistor M20; The source of the tenth NMOS transistor M15 is connected to the SW voltage; The source of the eleventh NMOS transistor M16 is connected to the drain of the twelfth NMOS transistor M17. The drain of the eleventh NMOS transistor M16 outputs a current I1, which is the current mirror output of the first PMOS transistor M1, and Figure 5 is connected to the drain of the first PMOS transistor M1 in the undervoltage detection circuit 2, providing a current source for the operation of the undervoltage detection circuit 2.

[0041] The source of the twelfth NMOS transistor M17 is connected to the SW voltage; The source of the thirteenth NMOS transistor M19 is connected to the drain of the fourteenth NMOS transistor M20; The source of the fourteenth NMOS transistor M20 is connected to the SW voltage; The other input of the OR gate OR1 is connected to the enable signal ENN, and the output is connected to the output identification signal Z1.

[0042] As Figure 4 shown, the working process of the current generation circuit 1 is as follows: During the power-on process of the BUCK chip, when the power-on of the enable module ends, ENN is at a low level. The first NMOS transistor M4, the fourth NMOS transistor M7, the third NMOS transistor M6, the sixth NMOS transistor M9, the seventh PMOS transistor M10, the seventh NMOS transistor M11, the eighth NMOS transistor M12, and the second resistor R2 form a startup circuit. When V BSTWhen the voltage is small, the circuit current is very small. The gate voltage of the first PMOS transistor M1 is at a high level, and the first PMOS transistor M1, the second PMOS transistor M2, and the third PMOS transistor M3 are all turned off. The gate voltages of the seventh PMOS transistor M10 and the eighth NMOS transistor M12 are pulled low by the sixth NMOS transistor M9, the gate voltage of the seventh NMOS transistor M11 is pulled low by the third NMOS transistor M6, the gate voltage of the first NMOS transistor M4 is pulled high by the seventh PMOS transistor M10, the first NMOS transistor M4 is turned on and Z1 outputs a high level, controlling the switch transistor in the BUCK chip to turn off, charging the BOOT capacitor and not outputting the mirror current reference source to the voltage stabilization detection circuit 3 and the undervoltage detection circuit 2. As V BST increases, the gate voltage of the first NMOS transistor M4 increases accordingly. When the first NMOS transistor M4 is turned on, the first PMOS transistor M1, the first NMOS transistor M4, the fourth NMOS transistor M7, and the second resistor R2 form a conducting path, and the circuit starts. After pulling down the gate voltage of the first PMOS transistor M1, the first PMOS transistor M1, the second NMOS transistor M5, the fifth NMOS transistor M8, the first resistor R1, and the second resistor R2 also form a conducting path, and the gate voltage of the seventh PMOS transistor M10 is pulled high. The aspect ratio of the seventh PMOS transistor M10 is set very small, the gate voltage of the first NMOS transistor M4 is pulled low, and Z1 flips to a low level. At this time, the first PMOS transistor M1, the third PMOS transistor M3, the fifth NMOS transistor M8, the sixth NMOS transistor M9, the first resistor R1, and the second resistor R2 form a current bias independent of the power supply. The current on the first PMOS transistor M1 is:

[0043] Where is the leakage current of the first PMOS transistor M1, is the electron mobility, is the gate oxide capacitance per unit area, is the aspect ratio of the fifth NMOS transistor M8, is the impedance of the first resistor R1, is the impedance of the second resistor R2, is the ratio of the aspect ratios of the fifth NMOS transistor M8 and the sixth NMOS transistor M9.

[0044] When V BSTWhen the voltage is relatively large, the gate-source voltage of the seventh PMOS transistor M10 increases, and the gate voltage of the first NMOS transistor M4 increases, but it will not reach the OR gate threshold voltage. At this time, the path of the first PMOS transistor M1, the first NMOS transistor M4, the fourth NMOS transistor M7, and the second resistor R2 is turned on, and the voltage drop across the second resistor R2 is relatively large, causing the gate-source voltage of the fifth NMOS transistor M8 to decrease, and the current in the path of the first PMOS transistor M1, the second NMOS transistor M5, the fifth NMOS transistor M8, the first resistor R1, and the second resistor R2 gradually decreases. At this time, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the first NMOS transistor M4, the third NMOS transistor M6, the fourth NMOS transistor M7, the sixth NMOS transistor M9, the seventh PMOS transistor M10, the seventh NMOS transistor M11, the eighth NMOS transistor M12, and the second resistor R2 form a negative feedback loop. The width-to-length ratio of the sixth NMOS transistor M9 is much larger than that of the third NMOS transistor M6, the overdrive voltage of the third NMOS transistor M6 is much larger than that of the sixth NMOS transistor M9, the width-to-length ratio of the eighth NMOS transistor M12 is much larger than that of the seventh NMOS transistor M11, and the V DS will be very small. When V BST increases, the gate-source voltage of the seventh PMOS transistor M10 increases, resulting in an increase in the gate-source voltage of the first NMOS transistor M4 and an increase in the current in the circuit branch, thereby obtaining a current proportional to the V BST voltage.

[0045] As Figure 5 shown, specifically, the undervoltage detection circuit 2 is a detection circuit for detecting whether the voltage difference between BST and SW is lower than the undervoltage threshold.

[0046] As Figure 5 shown, the undervoltage detection circuit 2 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first NMOS transistor M5, a second NMOS transistor M6, a third NMOS transistor M7, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a current source I1 obtained by mirroring the current of the first PMOS transistor M1 by the eleventh NMOS transistor M16 of the current generation circuit 1 in Figure 4 ; where: The gate and drain of the first PMOS transistor M1 are connected, and are connected to the gate of the third PMOS transistor M3, the gate of the fourth PMOS transistor M4, and the current source I1. The source of the first PMOS transistor M1 is connected to the bootstrap voltage BST; The drain of the second PMOS transistor M2 is connected to the bootstrap voltage BST through the first resistor R1, and is connected to the gates of the first NMOS transistor M5 and the second NMOS transistor M6 through the third resistor R3. The source of the second PMOS transistor M2 is connected to the bootstrap voltage BST; The drain of the third PMOS transistor M3 is connected to the gate of the third NMOS transistor M7 and is connected to the SW voltage through the fourth resistor R4. The source of the third PMOS transistor M3 is connected to the bootstrap voltage BST; The drain of the fourth PMOS transistor M4 is connected to the drain of the third NMOS transistor M7. The first inverter INV1 is connected to the bootstrap voltage BST through the second resistor R2, is connected to the gate of the second PMOS transistor M2 through the first inverter INV1, the second inverter INV2, and is connected to the under-voltage protection identification signal Z2 through the third inverter INV3. The source of the fourth PMOS transistor M4 is connected to the bootstrap voltage BST; The source of the first NMOS transistor M5 is connected to the SW voltage; The drain of the second NMOS transistor M6 is connected to the source of the third NMOS transistor M7, and the source is connected to the SW voltage.

[0047] As Figure 5 shown, the working process of the under-voltage detection circuit 2 is as follows: When the magnitude of the V BST voltage is relatively low, all MOS transistors operate in the cut-off region and there is no current. The input of the first inverter INV1 is pulled high by the second resistor R2, and at this time the output of Z2 is low. When the magnitude of the V BST voltage rises to a certain magnitude, the first PMOS transistor M1 starts to conduct and provides a bias current for the circuit. The third PMOS transistor M3 and the fourth PMOS transistor M4 mirror the current of the first PMOS transistor M1 and a current proportional to the V BST voltage. At this time, the current flowing through the first NMOS transistor M5 is relatively small, and the second NMOS transistor M6 mirrors the current of the first NMOS transistor M5. Because the current mirrored by the fourth PMOS transistor M4 is greater than the current mirrored by the second NMOS transistor M6, the fourth PMOS transistor M4 operates in the linear region, V DS4 is very small, the input voltage of the first inverter INV1 is high level, the gate voltage of the second PMOS transistor M2 is also high level, and the second PMOS transistor M2 is turned off. At this time, the current i DS6 flowing through the second NMOS transistor M6 is:

[0048] Among them, is the voltage difference between BST and SW, is the gate-source voltage of the first NMOS transistor M5, is the impedance of the first resistor R1, is the impedance of the third resistor R3. When gradually becomes greater than , the undervoltage threshold is reached, the input voltage of the first inverter INV1 becomes low, and the Z2 signal becomes high. The fourth PMOS transistor M4 enters the saturation region, and the equivalent impedance is very small. affected by the voltage change is small, the second NMOS transistor M6 enters the linear region, and the excess current flows out from the second resistor R2.

[0049] When the voltage of V BST flips from high to low, there is a hysteresis, and its threshold value V BST can be obtained according to the following formula:

[0050] As Figure 6 shown, specifically, the voltage stabilization detection circuit 3 is a voltage stabilization detection circuit that detects whether the voltage difference between BST and SW reaches a preset value.

[0051] As Figure 6 shown, the voltage stabilization detection circuit 3 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor MIII, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a first NMOS transistor M7, a second NMOS transistor M8, a third NMOS transistor M9, a fourth NMOS transistor M10, a fifth NMOS transistor M11, a sixth NMOS transistor M12, a seventh NMOS transistor M13, an eighth NMOS transistor M14, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a Zener diode D1, and a current source I2 obtained by mirroring the current of the first PMOS transistor M1 by the sixth PMOS transistor M21 of the current generation circuit 1 in Figure 4 ; where: The gate and drain of the first PMOS transistor M1 are connected, and are connected to the gate of the second PMOS transistor M2, the gate of the third PMOS transistor M3, and the gate of the fourth PMOS transistor M4. The source of the first PMOS transistor M1 is connected to the bootstrap voltage BST through the first resistor R1. The drain of the second PMOS transistor M2 is connected to the source of the fifth PMOS transistor M5, and the source of the second PMOS transistor M2 is connected to the bootstrap voltage BST through the second resistor R2. The drain of the third PMOS transistor M3 is connected to the source of the sixth PMOS transistor M6, and the source of the third PMOS transistor M3 is connected to the bootstrap voltage BST through the third resistor R3. The drain of the fourth PMOS transistor M4 is connected to the regulated output identification signal Z3, and is also connected to the source of the seventh NMOS transistor M13 and the drain of the eighth NMOS transistor M14. The source of the fourth PMOS transistor M4 is connected to the bootstrap voltage BST through the fourth resistor R4. The gates of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are jointly connected to the enable signal ENN. The drain of the fifth PMOS transistor M5 is connected to the gate, drain of the fifth NMOS transistor M11, and the gate of the sixth NMOS transistor M12. The drain of the sixth PMOS transistor M6 is connected to the drain of the sixth NMOS transistor M12, the gate, drain of the seventh NMOS transistor M13, and the gate of the eighth NMOS transistor M14. The gate and drain of the first NMOS transistor M7 are connected, and are connected to the third NMOS transistor M9 and the current source I2. The source of the first NMOS transistor M7 is connected to the gate, drain of the second NMOS transistor M8, and the gate of the fourth NMOS transistor M10. The source of the second NMOS transistor M8 is connected to the SW voltage. The source of the third NMOS transistor M9 is connected to the drain of the fourth NMOS transistor M10. The source of the fourth NMOS transistor M10 is connected to the SW voltage. The source of the fifth NMOS transistor M11 is connected to the SW voltage through the fifth resistor R5. The source of the sixth NMOS transistor M12 is connected to the bootstrap voltage BST through the Zener diode D1, and is connected to the SW voltage through the sixth resistor R6. The source of the eighth NMOS transistor M14 is connected to the SW voltage.

[0052] As Figure 6 shown, the working process of the regulated voltage detection circuit 3 is as follows: V BST When the voltage magnitude is relatively low, all MOS transistors operate in the cut-off region and there is no current. V BST When the voltage magnitude rises to a certain level, the third NMOS transistor M9 and the fourth NMOS transistor M10 start to conduct, and the mirror current and the current proportional to the V BST voltage reach the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4. The fifth resistor R5 is set to be less than the sixth resistor R6. At this time, the Zener diode D1 does not conduct, and V GS11 is less than V GS12, the gate voltages of M13 and M14 are pulled low, and the voltage of Z3 is pulled high by the fourth PMOS transistor M4. When the voltage difference between BST and SW is large enough to turn on the Zener diode D1, the source voltage of M12 is pulled high, and the gate voltages of the seventh NMOS transistor M13 and the eighth NMOS transistor M14 rise. After the seventh NMOS transistor M13 and the eighth NMOS transistor M14 are turned on, the voltage of Z3 is pulled low.

[0053] Correspondingly, based on the same inventive concept, this embodiment also provides a method for detecting the bootstrap voltage of a bootstrap circuit in a BUCK circuit, a bootstrap voltage control circuit for a bootstrap circuit in a BUCK circuit, a method for controlling the bootstrap voltage of a bootstrap circuit in a BUCK circuit, a bootstrap circuit in a BUCK circuit, a BUCK circuit, and a BUCK chip.

[0054] In summary, the above embodiments have the following beneficial effects: The current generation circuit 1 proportional to the voltage difference between BST and SW has a startup circuit; it outputs a current independent of the voltage magnitude when the V BST voltage is small, and outputs a current proportional to the V BST voltage when the V BST voltage is large, ensuring the stable operation of the circuit; it multiplexes the startup circuit and the negative feedback structure for adjusting the current magnitude when the V BST voltage is large, and the circuit structure is concise; by switching the conducting branches at different V BST voltages, the current changes smoothly; the current proportional to the V BST voltage can be used to adjust the thresholds of voltage regulation and undervoltage.

[0055] The detection circuit for detecting whether the voltage difference between BST and SW is lower than the undervoltage threshold has a hysteresis function; when the V BST voltage is small, the signal is pulled up by the second resistor R2, and there will be no false triggering.

[0056] In the voltage regulation detection circuit for detecting whether the voltage difference between BST and SW reaches a preset value, the current mirror adopts the form of source resistance negative feedback, improving the linearity of the mirror transistor; by using the current-voltage characteristic of the Zener diode, the voltage regulation threshold is set within the required range.

[0057] The overall circuit structure is simple, without relatively complex structures such as a reference voltage source and a comparator. It has a fast response speed, saves chip area, reduces power consumption current, greatly reduces the application cost, and also enables the bootstrap voltage to consume less charge when not charged, allowing the enabling chip to operate closer to a 100% duty cycle. By using current as the comparison quantity, a scheme is realized that can stably judge the magnitude of the BST-SW pressure difference even when the bootstrap voltage keeps jumping under the condition that the switching transistor keeps switching. The circuit parameters can be adjusted more flexibly, and the mirrored current is a current proportional to the V BST voltage. The under-voltage and regulated-voltage thresholds can be adjusted by changing the resistance value and the current mirroring multiple. The overall circuit is less affected by the floating SW voltage, operates stably, and has strong portability.

[0058] Specifically, the magnitude of the first resistor R1 and the third resistor R3 in the under-voltage detection circuit 2 in Figure 5 can be modified to adjust the under-voltage detection threshold, and the magnitude of the fifth resistor R5 and the sixth resistor R6 in the regulated-voltage detection circuit 3 in Figure 6 can be modified to adjust the regulated-voltage detection threshold.

[0059] In addition, the multiple of the current mirroring in the current generation circuit 1 in Figure 4 can also be modified to adjust the magnitudes of the mirrored current sources I1 and I2 to adjust the under-voltage and regulated-voltage thresholds. The specific method is as follows: Modify the aspect ratio of the width-to-length ratio of the eleventh NMOS transistor M16, the twelfth NMOS transistor M17 and the ninth NMOS transistor M14, the tenth NMOS transistor M15 to adjust the mirroring multiple of the mirrored current source I1, modify the aspect ratio of the width-to-length ratio of the thirteenth NMOS transistor M19, the fourteenth NMOS transistor M20 and the ninth NMOS transistor M14, the tenth NMOS transistor M15 or modify the aspect ratio of the width-to-length ratio of the sixth PMOS transistor M21 and the fifth PMOS transistor M18 to adjust the mirroring multiple of the mirrored current source I2.

[0060] The bootstrap voltage is a floating voltage rail, and it is not easy to realize comparison by detecting voltage. Compared with the prior art, the present invention realizes under-voltage and regulated-voltage detection by means of current quantity. And the reference source in the circuit uses a current source proportional to the bootstrap voltage instead of a reference source independent of voltage, the circuit parameters can be adjusted more flexibly, and the portability is strong. The circuit does not include structures such as a bandgap or a comparator, has a simple structure, saves chip area, and reduces the power consumption of the chip.

[0061] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative rather than restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit of the present invention and the scope protected by the claims. All of these fall within the protection scope of the present invention.

Claims

1. A bootstrap voltage detection circuit for a bootstrap circuit in a BUCK circuit, characterized in that including a current generation circuit, an undervoltage detection circuit, and / or a voltage regulation detection circuit; wherein, Current generation circuit: for outputting a mirrored current reference source I1 proportional to V BST to the undervoltage detection circuit; and / or, outputting a mirrored current reference source I2 proportional to V BST to the voltage regulation detection circuit; where V BST is the voltage difference between BST and SW; Under-voltage detection circuit: used to receive I1 and output an identification signal Z2 when V BST is lower than the under-voltage threshold; Voltage stabilization detection circuit: used to receive I2 and output an identification signal Z3 when V BST is lower than the voltage stabilization threshold value.

2. The bootstrap voltage detection circuit of the bootstrap circuit in the BUCK circuit according to claim 1, wherein the current generation circuit: is further configured to output an identification signal Z1; wherein, when I1 and / or I2 output by the current generation circuit are unstable, Z1 is at a high level; when I1 and / or I2 output by the current generation circuit are stable, Z1 is at a low level.

3. A method for detecting the bootstrap voltage of a bootstrap circuit in a BUCK circuit, characterized in that, using the bootstrap voltage detection circuit according to claim 1 or 2; including: The current generation circuit outputs a mirror current reference source I1 proportional to V BST to the undervoltage detection circuit; the undervoltage detection circuit receives I1 and outputs an identification signal Z2 when V BST is lower than the undervoltage threshold; and / or, The current generation circuit outputs a mirror current reference source I2 proportional to V BST to the voltage regulation detection circuit; the voltage regulation detection circuit receives I2 and outputs an identification signal Z3 when V BST is lower than the voltage regulation threshold value.

4. The bootstrap voltage detection method of the bootstrap circuit in the BUCK circuit according to claim 3, characterized in that, further including: the current generation circuit outputs an identification signal Z1; wherein, when I1 and / or I2 output by the current generation circuit are unstable, Z1 is at a high level; when I1 and / or I2 output by the current generation circuit are stable, Z1 is at a low level.

5. A bootstrap voltage control circuit for a bootstrap circuit in a BUCK circuit, characterized in that, including the bootstrap voltage detection circuit according to claim 1 or 2; wherein: the identification signal Z2 is used to turn off the high-side switch transistor and control the conduction of the bootstrap voltage pull-up transistor to charge the BOOT capacitor; the identification signal Z3 is used to control the charging of the BOOT capacitor when the high-side switch transistor is turned off.

6. The bootstrap voltage control circuit of the bootstrap circuit in the BUCK circuit according to claim 5, characterized in that, the current generation circuit: is further configured to output an identification signal Z1; wherein, when I1 and / or I2 output by the current generation circuit are unstable, Z1 is at a high level, and Z1 is used to turn off the high-side switch transistor and control the turn-off of the bootstrap voltage pull-up transistor; when I1 and / or I2 output by the current generation circuit are stable, Z1 is at a low level.

7. A method for controlling the bootstrap voltage of a bootstrap circuit in a BUCK circuit, characterized in that, using the bootstrap voltage control circuit according to claim 5 or 6, including: At V BST When it is lower than the undervoltage threshold, the identification signal Z2 turns off the high-side switch and controls the boost voltage pull-up transistor to conduct to charge the BOOT capacitor; At V BST When below the regulated voltage threshold, the identification signal Z3 controls the charging of the BOOT capacitor when the high-side switch is turned off.

8. The bootstrap voltage control circuit of the bootstrap circuit in the BUCK circuit according to claim 7, characterized in that, when I1 and / or I2 output by the current generation circuit are unstable, the current generation circuit outputs an identification signal Z1, Z1 is at a high level, and Z1 turns off the high-side switch transistor and controls the turn-off of the bootstrap voltage pull-up transistor.

9. A bootstrap circuit in a BUCK circuit, characterized in that, including the bootstrap voltage detection circuit according to claim 1 or 2.

10. A BUCK circuit, characterized in that, including the bootstrap circuit according to claim 9.

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