High-speed decision device

Abstract

The invention discloses a high-speed decision device. The high-speed decision device comprises a comparison circuit, a latch reset circuit and an adjusting circuit, the comparison circuit comprises a first branch circuit and a second branch circuit; the first branch circuit and the second branch circuit are used for comparing the differential voltage of the input signal with the threshold voltage; the first branch and the second branch are connected in parallel to two input nodes of the latch reset circuit, and the latch reset circuit latches the comparison result; an adjusting circuit is connected in parallel to two input nodes of the latch reset circuit and is used for improving the response speed of the decision device in a comparison stage; in addition, by raising the substrate potential of an NMOS transistor in the decision device circuit, the working speed of the transistor itself is improved. According to the invention, the response time of the decision device is improved, so that the rate requirement of the high-speed DFE is met.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed data transmission, and particularly to a high-speed decision maker. Background Art

[0002] The rapid development and application of big data have continuously promoted the demand for high-speed data communication. In high-speed data communication, SERDES technology is the key to achieving efficient data transmission. As the data transmission rate continues to increase, data loss will be more serious, and the receiver often cascades a DFE (Decision Feedback Equalizer) after the CTLE to recover the data. The implementation of a high-speed DFE is affected by the delay of the critical timing path, and the high-speed decision maker is located in the critical timing path, and its delay time restricts the rate improvement of the DFE.

[0003] In the design of the DFE, the decision maker usually adopts a strong-arm latch comparator structure. As Figure 1 shown, the decision maker circuit includes a comparison circuit 101 and a latch reset circuit 102. When the clock is at a low level, the decision maker is in a reset state, and charges are quickly injected into the output node through transistors TP1 and TP2 to raise the differential output node voltage to the power supply voltage. When the clock is at a high level, the decision maker is in a comparison state, and the input pair of transistors starts to charge the internal node. When the input signal INP > INN, the discharge time of OUTN is faster than that of OUTP, and the voltage difference of the output node is further amplified through the positive feedback latch composed of transistors MP1, MP2, MN3, and MN4, and a full-swing signal is output.

[0004] The defect of this structure is that the voltage of the internal node is relatively high during the reset stage, and the charging current during the comparison stage is completely provided by the tail transistor controlled by the clock, and the available current is limited, resulting in a slow discharge time at the differential output end and a long overall delay time, which cannot meet the rate requirements of the high-speed DFE. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-speed decision maker to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a high-speed decision maker, including:

[0007] A comparison circuit, including a first branch and a second branch, the first branch providing a positive-phase data signal and a positive-phase reference voltage signal, and the second branch providing an anti-phase data signal and an anti-phase reference voltage signal; the comparison circuit compares the differential voltage of the input signal with the threshold voltage;

[0008] The latch reset circuit includes cross-connected inverters, and the cross-connected inverters form a positive feedback latch node to latch the comparison result of the comparison circuit.

[0009] The adjustment circuit includes two switching transistors respectively connected to two input nodes in the latch reset circuit, and is used to improve the response speed in the comparison stage of the decision maker.

[0010] In one embodiment, the first branch and the second branch are connected in parallel to two input nodes of the latch reset circuit; wherein,

[0011] The first branch includes a first input pair of transistors M1 and M2. The gate terminal of M1 is connected to the positive-phase data signal VINP, and the gate terminal of M2 is connected to the positive-phase reference voltage signal VREFP.

[0012] The second branch includes a second input pair of transistors M3 and M4. The gate terminal of M3 is connected to the inverted-phase data signal VINN, and the gate terminal of M4 is connected to the inverted-phase reference voltage signal VREFN.

[0013] The first input pair of transistors M1 and M2 are commonly connected to a first switching transistor, and the second input pair of transistors M3 and M4 are commonly connected to a second switching transistor; the switching states of the first switching transistor and the second switching transistor are controlled by the clock signal CLK; when the clock signal CLK is at a high level, the first switching transistor and the second switching transistor are closed, and the comparison circuit compares the differential voltage with the threshold voltage.

[0014] In one embodiment, the positive-phase reference voltage signal VREFP and the inverted-phase reference voltage signal VREFN are generated by a wide-range 6-bit current-steering DAC, realizing wide-range common-mode voltage and differential-mode voltage output, and are used to provide the decision maker threshold and calibrate the decision maker offset.

[0015] In one embodiment, in the latch reset circuit, the cross-connected inverters are composed of NMOS cross-pair transistors M5 and M6, and PMOS cross-pair transistors M7 and M8. The latch reset circuit further includes a third switching transistor and a fourth switching transistor, and the switching states of the third switching transistor and the fourth switching transistor are controlled by the clock signal CLK; when the clock signal CLK is at a low level, the third switching transistor and the fourth switching transistor are closed, and the high-speed decision maker operates in the reset stage.

[0016] In one embodiment, the adjustment circuit includes a fifth switching transistor and a sixth switching transistor. The fifth switching transistor and the sixth switching transistor are respectively connected to two input nodes of the latch reset circuit, and the switching states of the fifth switching transistor and the sixth switching transistor are controlled by a clock signal CLK; the switching states of the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are controlled by the same phase of the clock signal CLK.

[0017] In one embodiment, the high-speed discriminator has three working stages: a comparison stage, a latching stage, and a reset stage;

[0018] The working process of the comparison stage is as follows: when the clock signal CLK is at a high level, the first switching transistor and the second switching transistor are closed, the third switching transistor and the fourth switching transistor are open, the discriminator works in the comparison stage, the comparison circuit compares the differential voltage of the input signal with the threshold voltage, and at the same time, the fifth switching transistor and the sixth switching transistor are closed to inject an additional large current into the two input nodes of the latch reset circuit, accelerating the comparison process and prompting the discriminator to enter the latching stage more quickly;

[0019] The working process of the latching stage is as follows: in the latching stage, the first switching transistor and the second switching transistor are closed, the third switching transistor and the fourth switching transistor are open, the fifth switching transistor and the sixth switching transistor are closed, and the cross-connected inverters in the latch reset circuit form a positive feedback latch node to latch the comparison result of the comparison circuit to obtain a full-swing output signal;

[0020] The working process of the reset stage is as follows: when the clock signal CLK is at a low level, the first switching transistor and the second switching transistor are open, the third switching transistor and the fourth switching transistor are closed, and the discriminator works in the reset stage; the fifth switching transistor and the sixth switching transistor are open, and the current introduced by the adjustment circuit is only injected in the comparison stage.

[0021] In one embodiment, all NMOS transistors in the comparison circuit, the latch reset circuit, and the adjustment circuit are DNW NMOS transistors, and the substrate potential SUB is provided with a reference voltage by a separate bias circuit.

[0022] The high-speed discriminator provided by the present invention adds an adjustment branch, improving the response speed of the discriminator in the comparison stage; since the substrate potential of the NMOS transistor is lifted, the working speed of the transistor itself is increased; the present invention improves the response time of the discriminator, thereby meeting the rate requirements of high-speed DFE. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a conventional high-speed discriminator circuit;

[0024] Figure 2It is a schematic diagram of a high-speed decision circuit disclosed in an embodiment of the present invention;

[0025] Figure 3 It is a schematic diagram of a threshold voltage generation circuit of a high-speed decision device disclosed in an embodiment of the present invention. Specific embodiments

[0026] The following further elaborates on a high-speed decision device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a high-speed decision circuit, as Figure 2 shown, including a comparison circuit 201, a latch reset circuit 202, and an adjustment circuit 203.

[0028] The comparison circuit 201 includes a first branch and a second branch, and the first branch and the second branch are connected in parallel to the input nodes V1 and V2 of the latch reset circuit 202;

[0029] Among them, the first branch includes first input pairing transistors M1 and M2, M1 is used to provide the input end of the positive-phase data signal VINP, and M2 is used to provide the input end of the reference voltage signal VREFP; the second branch includes second input pairing transistors M3 and M4, M3 is used to provide the input end of the inverted-phase data signal VINN, and M4 is used to provide the input end of the reference voltage signal VREFN.

[0030] The reference voltage signals VREFP and VREFN are generated by a wide-range 6-bit current-steering DAC, as Figure 3 shown. By means of a 6-bit control word, the relative output current magnitudes of the current-steering DACs I1 and I2 can be adjusted. Through the different conduction conditions of the switch groups T1 and T3 and the switch groups T2 and T4, it is realized that the output reference voltage VREFP is greater than VREFN or VREFP is less than VREFN; at the same time, the input VREF voltage is adjustable, and this VREF voltage determines the common-mode voltage (VREFP + VREFN) / 2 of the output reference voltage signals VREFP and VREFN. This circuit is used to provide the decision threshold and calibrate the decision offset.

[0031] The first input pair of transistors M1 and M2 in the first branch are connected to the first switching transistor T1, and the second input pair of transistors M3 and M4 in the second branch are connected to the second switching transistor T2; the switching states of the first switching transistor T1 and the second switching transistor T2 are controlled by the clock signal CLK; when the clock signal CLK is at a high level, the first switching transistor T1 and the second switching transistor T2 are closed, and the comparison circuit 201 compares the differential voltage (VINP - VINN) with the threshold voltage (VREFP - VREFN).

[0032] The latch reset circuit 202 includes cross - connected inverters composed of NMOS cross - pair transistors M5 and M6 and PMOS cross - pair transistors M7 and M8. The cross - connected inverters form a positive - feedback latch node to latch the comparison result of the comparison circuit 201.

[0033] The latch reset circuit 202 includes a third switching transistor T3 and a fourth switching transistor T4. The switching states of the third switching transistor T3 and the fourth switching transistor T4 are controlled by the clock signal CLK; when the clock signal CLK is at a low level, the third switching transistor T3 and the fourth switching transistor T4 are closed, and the high - speed decision maker operates in the reset stage.

[0034] The adjustment circuit 203 includes a fifth switching transistor T5 and a sixth switching transistor T6. The fifth switching transistor T5 and the sixth switching transistor T6 are respectively connected to the input nodes V1 and V2 of the latch reset circuit 202. The switching states of the fifth switching transistor T5 and the sixth switching transistor T6 are controlled by the clock signal CLK; the switching states of the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, and the sixth switching transistor T6 are controlled by the same phase of the clock signal CLK.

[0035] All NMOS transistors in the comparison circuit 201, the latch reset circuit 202, and the adjustment circuit 203 use DNW NMOS transistors, and the substrate potential SUB is provided with a reference voltage by a separate bias circuit.

[0036] In addition, an embodiment of the present invention provides a method for improving the speed of a decision maker, including:

[0037] As Figure 2 The shown high - speed decision maker circuit has three working stages: a comparison stage, a latch stage, and a reset stage;

[0038] When the clock signal CLK is at a high level, the first switching transistor T1 and the second switching transistor T2 are turned on, and the third switching transistor T3 and the fourth switching transistor T4 are turned off. The decision circuit operates in the comparison stage. The comparison circuit 201 compares the differential voltage (VINP - VINN) with the threshold voltage (VREFP - VREFN). At the same time, the fifth switching transistor T5 and the sixth switching transistor T6 are turned on, injecting an additional large current into the input nodes V1 and V2 of the latch reset circuit 202 to accelerate the comparison process and prompt the decision circuit to enter the latch stage more quickly;

[0039] In the latch stage, the first switching transistor T1 and the second switching transistor T2 are turned on, the third switching transistor T3 and the fourth switching transistor T4 are turned off, and the fifth switching transistor T5 and the sixth switching transistor T6 are turned on. The cross-connected inverters in the latch reset circuit 202 form a positive feedback latch node to latch the comparison result of the comparison circuit 201 and obtain a full-swing output signal;

[0040] When the clock signal CLK is at a low level, the first switching transistor T1 and the second switching transistor T2 are turned off, the third switching transistor T3 and the fourth switching transistor T4 are turned on, and the decision circuit operates in the reset stage. The differential output voltage is reset to the power supply voltage VDD; the fifth switching transistor T5 and the sixth switching transistor T6 are turned off, and the current introduced by the adjustment circuit 203 is only injected in the comparison stage, without causing excessive power consumption;

[0041] Furthermore, all NMOS transistors in the comparison circuit 201, the latch reset circuit 202, and the adjustment circuit 203 are DNW NMOS transistors. The substrate potential SUB of the DNW NMOS transistor is provided with a reference voltage by a separate bias circuit. As the substrate potential SUB increases, the threshold voltage of the NMOS transistor decreases, thereby improving the operating speed of the transistor itself.

[0042] Based on the above technical means, the response time of the decision circuit is improved, thereby meeting the rate requirements of high-speed DFE.

[0043] After considering the specification and the practice disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the claims.

[0044] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A high-speed decision maker, characterized in that, Comprising: A comparison circuit, including a first branch and a second branch. The first branch provides a non-inverted data signal and a non-inverted reference voltage signal, and the second branch provides an inverted data signal and an inverted reference voltage signal. The comparison circuit compares the differential voltage of the input signal with the threshold voltage; A latch reset circuit, including cross-connected inverters, and the cross-connected inverters form a positive feedback latch node to latch the comparison result of the comparison circuit; An adjustment circuit, including two switching transistors respectively connected to two input nodes in the latch reset circuit, for improving the response speed in the comparison stage of the decision maker.

2. The high-speed decision device according to claim 1, wherein The first branch and the second branch are connected in parallel to two input nodes of the latch reset circuit; wherein, The first branch includes first input pair transistors M1 and M2. The gate terminal of M1 is connected to the non-inverted data signal VINP, and the gate terminal of M2 is connected to the non-inverted reference voltage signal VREFP; The second branch includes second input pair transistors M3 and M4. The gate terminal of M3 is connected to the inverted data signal VINN, and the gate terminal of M4 is connected to the inverted reference voltage signal VREFN; The first input pair transistors M1 and M2 are commonly connected to a first switching transistor, and the second input pair transistors M3 and M4 are commonly connected to a second switching transistor. The switching states of the first switching transistor and the second switching transistor are controlled by a clock signal CLK. When the clock signal CLK is at a high level, the first switching transistor and the second switching transistor are closed, and the comparison circuit compares the differential voltage with the threshold voltage.

3. The high-speed decision device according to claim 2, characterized in that, The non-inverted reference voltage signal VREFP and the inverted reference voltage signal VREFN are generated by a wide-range 6-bit current-steering DAC, realizing wide-range common-mode voltage and differential-mode voltage output, for providing the decision maker threshold and calibrating the decision maker offset.

4. The high-speed decision device according to claim 3, wherein In the latch reset circuit, the cross-connected inverters are composed of NMOS cross-pair transistors M5 and M6, and PMOS cross-pair transistors M7 and M8. The latch reset circuit further includes a third switching transistor and a fourth switching transistor. The switching states of the third switching transistor and the fourth switching transistor are controlled by the clock signal CLK. When the clock signal CLK is at a low level, the third switching transistor and the fourth switching transistor are closed, and the high-speed decision maker operates in the reset stage.

5. The high-speed decision device according to claim 4, wherein The adjustment circuit includes a fifth switching transistor and a sixth switching transistor. The fifth switching transistor and the sixth switching transistor are respectively connected to two input nodes of the latch reset circuit. The switching states of the fifth switching transistor and the sixth switching transistor are controlled by the clock signal CLK. The switching states of the first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are controlled by the same phase of the clock signal CLK.

6. The high-speed decision device according to claim 5, characterized in that The high-speed decision maker has three working stages: a comparison stage, a latch stage, and a reset stage; The working process of the comparison stage is as follows: when the clock signal CLK is at a high level, the first switch transistor and the second switch transistor are closed, the third switch transistor and the fourth switch transistor are open, the discriminator works in the comparison stage, the comparison circuit compares the differential voltage of the input signal with the threshold voltage, and at the same time the fifth switch transistor and the sixth switch transistor are closed to inject an additional large current into the two input nodes of the latch reset circuit, accelerating the comparison process and prompting the discriminator to enter the latch stage more quickly; The working process of the latch stage is as follows: in the latch stage, the first switch transistor and the second switch transistor are closed, the third switch transistor and the fourth switch transistor are open, the fifth switch transistor and the sixth switch transistor are closed, and the cross-connected inverters in the latch reset circuit form a positive feedback latch node to latch the comparison result of the comparison circuit to obtain a full swing output signal; The working process of the reset stage is as follows: when the clock signal CLK is at a low level, the first switch transistor and the second switch transistor are open, the third switch transistor and the fourth switch transistor are closed, and the discriminator works in the reset stage; the fifth switch transistor and the sixth switch transistor are open, and the current introduced by the regulation circuit is only injected in the comparison stage.

7. The high-speed decision device according to claim 1, wherein All NMOS transistors in the comparison circuit, the latch reset circuit, and the regulation circuit are DNW NMOS transistors, and the substrate potential SUB is provided with a reference voltage by a separate bias circuit.

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